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1 /
www.FlexTiles.biz
Real-time Processing SystemsHeterogeneous ArchitectureMultiprocessor FPGA and DSP450+ Flexible I/Os PortOpen-Source Core Design
2 /
SMT166 – FPGA Carrier Board
Mezzanine LVDS Bus
Serial Rocket IOs
Parallel Bus
An SLB cable can be used to link the SLB on the Master module to the SLB on the SMT166 while using RSLs.
PCIe cable connectors can be used as a link to a Host-PC. 1x lane and 4x lanes cables are available as well asHost Interface Board to communicate to a PC.
FPGA_0Virtex 6
LX130T-LX365TSX315T-SX475T
PSUSection
DDR3 MemoryBank 2
SLB/LPC-FMCMezzanine 0
SLB/Converter to FMC
PSU
SLB/LPC-FMCMezzanine 1
SLB/Converter to FMC
PSU
SLB/LPC-FMCMezzanine 2
SLB/Converter to FMC
PSU
SLB/LPC-FMCMezzanine 3
SLB/Converter to FMC
PSU
FPGA_1Virtex 6
LX130T-LX365TSX315T-SX475T
DDR3 MemoryBank 3
DDR3 MemoryBank 0
DDR3 MemoryBank 1
108x I/Oi 108x I/O
j108x
I/O
l
108x I/Ok
RSL x2
mRSL x2
n
54x I/On54x I/O
m
RSL x4
o i Channels x2
PCIeCable
x4
x4
l
MasterModule
SLB Connector
RSL
RSL
PCIeCable
x4
x4
j
PCIeCable
x1 x1
i
PCIeCable
x1x1
k
USB+CPLD +Flash
To configure Virtex6
FPGAs and access Master
Module Flash
ClockSynthesiser
Synchroniser
Top TIM Connector
Bottom TIM Connector
Dual SATA3.0
x2
q
Dual SATA3.0
x2
p
1Gigabit Ethernet
1Gigabit Ethernet
FlexTiles Block Diagram
3 /
Xilinx Virtex-6 LX135T or SX475T: 1156 I/O pins Speed Grade -2, as default
DDR3 memory: Micron;128 Mbytes per bank in two devices High speed (DDR3-1333) up to 5.2 Gbytes/s at 660MHz
Bank BBank A
2x128 Mbytes 2x128 Mbytes
Virtex-6 FPGA
FlexTiles’s Memory + FPGA
4 /
Memory Interface Each FPGA is connected to 2 banks of DDR3 Generated with Xilinx MIG tools (MPMC v6.05.a)
Virtex-6_0 Virtex-6_1
Bank A Bank B Bank A Bank B
FlexTiles’s Memory Interface
5 /
Inter-FPGA Serial Link: Communication between FPGAs can be made via 4 lanes of Serial Interface. Lanes are hardwired on the PCB in order to have two identical firmware, UCF
files, 2n, scalable, dynamic re-configurable and fault tolerant systems.
Virtex 6
Virtex 6
FlexTiles’s FPGA Serial Links
6 /
Inter-FPGA Serial Link: Standard Sundance RSLs can achieve up to 200Mb/s per lane on cables Xilinx transmission protocol (GTX) can achieve up to 600Mb/s per lane
FlexTiles’s FPGA Serial Links
Virtex 6
Virtex 6
7 /
Flash memory Bitstream files can be stored into Flash memory accessible from host PC/unit
via a USB 2.0 port The SMT6002 utility software tool takes care about generating the correct
offset/address while writing the bitstream files
SMT166 – Configuration
FPGA_0Virtex 6
LX130T-LX395T
FPGA_1Virtex 6
LX130T-LX395T
Flash
USB2.0 CPLD
Mode selection made via switches
Config.
Port
Configuration Port
Comport3 Master Module
JTAG
FlexTiles’s Programming
8 /
Connected USB Cypress USB IC device
The USB interface:
A USB interface is available to the CPLD for communication with a host controller. Used for read and write operation in the flash.
Can to interface to PC, move data, etc...
FlexTiles’s USB Interface
9 /
Connected to RS232
RS232 Serial interface: Two RS232 connections are available on the FDP One for each FPGA. Run a simple console terminal for debug Run Linux on the FPGA’s MicroBlaze!
FlexTiles’s RS232 Interface
10 /
Connected to an Ethernet interface
The Ethernet interface: Virtex-6 FPGA features built-in TEMAC blocks : 4 per FPGA. Will be dedicated to communicate to an external PHY
Up to 1Gbit/s Licenses needs to be acquired from Xilinx for full performance
FlexTiles’s Ethernet
11 /
Connected to a PCI Express Cabled Interface By 1x Lane
By 4x Lanes Allows to connect 2 or more FDP boards in a pipe One FDP and a Host PC Controller FPGAs populated on the FDP features two PCI Express blocks, which means
that both express interfaces can be used simultaneously
FlexTiles’s Cabled PCI Express
12 /
Connected to a SATA interface
SATA Interface Two SATA connectors are available per FPGA Virtex-6 Rocket-IO serial links have the ability to be configured at 3Gbit/s or
6Gbit/s SATA links A SATA 3.0 IP option (link) can be provided with the FDP board
FlexTiles’s SATA Interface
13 /
External clocks One External clock and one reference are fed to the board via MMCX connectors
(Huber-Suhner). They can be used to synchronise the on-board optional clock circuitry to an external system clock domain.
External clocks to SLB
mezzanine module, …
Oscillator
Clock chip
FlexTiles’s Clocks
14 /
Low-Voltage Powered Input Compatible with a standard ATX power supply unit All voltages are derived from a single 12VD to 48VDC power rail
Or
FlexTiles’s Power Supply
15 /
FlexTiles with SLB Slots
16 /
SLB (Sundance Local Bus) mezzanine modules The FDP can receive up to 4 SLB mezzanine cards (2 per FPGA). 120 I/O Pins on each Connector; Power Supply; Identical for both FPGAs
VIRTEX-6 #2
VIRTEX-6
#1
FlexTiles with SLB Slots
17 /
FlexTiles with FMC Slots
18 /
SMT372T Dual DSP Processing Module - Optional Two six fixed-point TMS320C6472 DSPs for Processing Virtex-5 FX70T FPGA for Interface to FDP
FlexTiles’s DSP Module
19 /
FDP Populated with one SMT372T DSP Module Twelve 700MHz DSP Cores with FPGAs for pre-processing
SMT372T
FlexTiles’s DSP Module
20 /
SMT372T Dual DSP Processing Module - Optional Two six fixed-point TMS320C6472 DSPs for Processing Virtex-5 FX70T FPGA for Interface to FDP
FlexTiles’s DSP Module
21 /
Software Defined Radio Platform
Multi-channel DAQ PlatformsUp to 16x 14-bit 250MSPS ADC channels: SMT166-141-xUp to 16x 14-bit 250MSPS ADC channels: SMT166-142-x4/8x 800MSPS DAC+ 250MSPS ADC channels: SMT166-143-x
Optional: 12x Fixed-Point DSP Cores: SMT372-FX70T
SMT166-141-1616x ADC Channels
SLB
External Trigger
ADS62P49Dual ADC Ch C & Ch D14-bit
250MSPS(2x 675mW)
Clock Synchronizer and Jitter cleaner Based on CDCE72010
(1.8W)
ADS62P49Dual ADC Ch A & Ch B14-bit
250MSPS(2x 675mW)
Channel A Signal
Conditioning (AC coupling)
Channel B Signal
Conditioning (AC coupling)
Channel D Signal
Conditioning (AC coupling)
ADC Input Ch A
MMCX50 Ohm
Channel C Signal
Conditioning (AC coupling)
ADCs External Clock in
Ext Ref Clock in
ADCs External
Clock
out
ADC Input Ch B
MMCX50 Ohm
ADC Input Ch C
MMCX50 Ohm
ADC Input Ch D
MMCX50 Ohm
4 Channels; 250MHz @ 14 bits
SLB
External Trigger
ADS62P49Dual ADC Ch C & Ch D14-bit
250MSPS(2x 675mW)
Clock Synchronizer and Jitter cleaner Based on CDCE72010
(1.8W)
ADS62P49Dual ADC Ch A & Ch B14-bit
250MSPS(2x 675mW)
Channel A Signal
Conditioning (AC coupling)
Channel B Signal
Conditioning (AC coupling)
Channel D Signal
Conditioning (AC coupling)
ADC Input Ch A
MMCX50 Ohm
Channel C Signal
Conditioning (AC coupling)
ADCs External Clock in
Ext Ref Clock in
ADCs External
Clock
out
ADC Input Ch B
MMCX50 Ohm
ADC Input Ch C
MMCX50 Ohm
ADC Input Ch D
MMCX50 Ohm
4 Channels; 250MHz @ 14 bits
SLB
External Trigger
ADS62P49Dual ADC Ch C & Ch D14-bit
250MSPS(2x 675mW)
Clock Synchronizer and Jitter cleaner Based on CDCE72010
(1.8W)
ADS62P49Dual ADC Ch A & Ch B14-bit
250MSPS(2x 675mW)
Channel A Signal
Conditioning (AC coupling)
Channel B Signal
Conditioning (AC coupling)
Channel D Signal
Conditioning (AC coupling)
ADC Input Ch A
MMCX50 Ohm
Channel C Signal
Conditioning (AC coupling)
ADCs External Clock in
Ext Ref Clock in
ADCs External
Clock
out
ADC Input Ch B
MMCX50 Ohm
ADC Input Ch C
MMCX50 Ohm
ADC Input Ch D
MMCX50 Ohm
4 Channels; 250MHz @ 14 bits
SLB
External Trigger
ADS62P49Dual ADC Ch C & Ch D14-bit
250MSPS(2x 675mW)
Clock Synchronizer and Jitter cleaner Based on CDCE72010
(1.8W)
ADS62P49Dual ADC Ch A & Ch B14-bit
250MSPS(2x 675mW)
Channel A Signal
Conditioning (AC coupling)
Channel B Signal
Conditioning (AC coupling)
Channel D Signal
Conditioning (AC coupling)
ADC Input Ch A
MMCX50 Ohm
Channel C Signal
Conditioning (AC coupling)
ADCs External Clock in
Ext Ref Clock in
ADCs External
Clock
out
ADC Input Ch B
MMCX50 Ohm
ADC Input Ch C
MMCX50 Ohm
ADC Input Ch D
MMCX50 Ohm
4 Channels; 250MHz @ 14 bits
SLB
SLB
SLB
SLB
FPGA_0Virtex 6 LX130T
or SX475T
DDR3 MemoryBank 04Gb/s
DDR3 MemoryBank 14Gb/s
PCIe Cablex1
PCIe Cablex4
Dual SATA 3.0
DSP TIM Mater Module2x RSL connectors
SLB
200 Mb/s
800 Mb/s
500 Mb/s
2 Gb/s
2 Gb/s
FPGA_1Virtex 6 LX130T
orSX475T
PCIe Cablex1
PCIe Cablex4
Dual SATA 3.0
200 Mb/s
800 Mb/s
500 Mb/s
2 Gb/s
2 Gb/s
DDR3 MemoryBank 24Gb/s
DDR3 MemoryBank 34Gb/s
2 x
2 G
b/s
800
Mb/
s
400
Mb/
s40
0 M
b/s
On board Power Supplies
USB, CPLD + Flash To configure Virtex 6 FPGAs and access Master Module
Flash
Configuration DIP Switches
FPGA & DSP JTAG in
Clock Synthesiser Syncroniser
RS23210/100/1000
Ethernet
RS23210/100/1000
Ethernet
22 /
FDP Populated with four SMT941 ADC SLBs 16 channels Data Acquisitions System
SMT941
SMT941
SMT372T
Software Defined Radio Platform
23 /
Quad ADC Add-On SLB (Sundance Local Bus) Module SMT941 Quad 250MSPS @ 14-bit ADC
Software Defined Radio Platform
24 /
MIMO RF Development Platform
Multichannel MIMO RF PlatformsMIMO 4x4 with 2.3-3.5GHz RF Front-ends: SMT166-903-2MIMO 4x4 with 2.4/5GHz RF Front-ends: SMT166-911-2MIMO 8x8 with 2.3-3.5GHz RF Front-ends: SMT166-903-4MIMO 8x8 with 2.4/5GHz RF Front-ends: SMT166-911-4
Optional: 12x Fixed-Point DSP Cores: SMT372-FX70T
SMT166-911-4RF-MIMO 8x8
SLB
SLB
SLB
SLB
FPGA_0Virtex 6 LX130T
or SX475T
DDR3 MemoryBank 04Gb/s
DDR3 MemoryBank 14Gb/s
PCIe Cablex1
PCIe Cablex4
Dual SATA 3.0
DSP TIM Master Module
2x RSL connectors(Optional)
SLB
200 Mb/s
800 Mb/s
500 Mb/s
2 Gb/s
2 Gb/s
FPGA_1Virtex 6 LX130T
orSX475T
PCIe Cablex1
PCIe Cablex4
Dual SATA 3.0
200 Mb/s
800 Mb/s
500 Mb/s
2 Gb/s
2 Gb/s
DDR3 MemoryBank 24Gb/s
DDR3 MemoryBank 34Gb/s
2 x
2 G
b/s
800
Mb/
s
400
Mb/
s40
0 M
b/s
On board Power Supplies
USB, CPLD + Flash To configure Virtex 6 FPGAs and access Master Module
Flash
Configuration DIP Switches
FPGA & DSP JTAG in
Clock Synthesiser Syncroniser
RS23210/100/1000
Ethernet
RS23210/100/1000
Ethernet
SLB
ADC/DACAD9863
Clock Distribution
RF Front EndSiGe 2543
RSSI ADC AD7476
ADC/DACAD9863
TransceiverMAX2829
RF Front EndSiGe 2543
RSSI ADC AD7476
40MHz Crystal
ExtClk
Tx
RxTransceiverMAX2829
Tx
Rx
SLB
ADC/DACAD9863
Clock Distribution
RF Front EndSiGe 2543
RSSI ADC AD7476
ADC/DACAD9863
TransceiverMAX2829
RF Front EndSiGe 2543
RSSI ADC AD7476
40MHz Crystal
ExtClk
Tx
RxTransceiverMAX2829
Tx
Rx
SLB
ADC/DACAD9863
Clock Distribution
RF Front EndSiGe 2543
RSSI ADC AD7476
ADC/DACAD9863
TransceiverMAX2829
RF Front EndSiGe 2543
RSSI ADC AD7476
40MHz Crystal
ExtClk
Tx
RxTransceiverMAX2829
Tx
Rx
SLB
ADC/DACAD9863
Clock Distribution
RF Front EndSiGe 2543
RSSI ADC AD7476
ADC/DACAD9863
TransceiverMAX2829
RF Front EndSiGe 2543
RSSI ADC AD7476
40MHz Crystal
ExtClk
Tx
RxTransceiverMAX2829
Tx
Rx
25 /
2.5GHz/5GHz RF Add-On SLB (Sundance Local Bus) Module SMT911 Dual Channel RF Transceiver
MIMO RF Development Platform
26 /
FDP Populated with four SMT911 RF SLBs 8 by 8 MIMO Development System
SMT911
SMT911
SMT372T
MIMO RF Development Platform
27 /
Multichannel Image Systems
Multi-channel Video/Image PlatformsUp to 128x PAL/NTSC Video Input channels: SMT166-909-xUp to 8x Camera-Link Image Input channels: SMT166-949-xUp to 4x DVI Display Input/Output channels: SMT166-939-x
Optional: 12x Fixed-Point DSP Cores: SMT372-FX70T
SMT166-909-4PAL/NTSC Video In
128 channels
SLB
SLB
SLB
SLB
FPGA_0Virtex 6 LX130T
or SX475T
DDR3 MemoryBank 04Gb/s
DDR3 MemoryBank 14Gb/s
PCIe Cablex1
PCIe Cablex4
Dual SATA 3.0
DSP TIM Master Module
2x RSL connectors(Optional)
SLB
200 Mb/s
800 Mb/s
500 Mb/s
2 Gb/s
2 Gb/s
FPGA_1Virtex 6 LX130T
orSX475T
PCIe Cablex1
PCIe Cablex4
Dual SATA 3.0
200 Mb/s
800 Mb/s
500 Mb/s
2 Gb/s
2 Gb/s
DDR3 MemoryBank 24Gb/s
DDR3 MemoryBank 34Gb/s
2 x
2 G
b/s
800
Mb/
s
400
Mb/
s40
0 M
b/s
On board Power Supplies
USB, CPLD + Flash To configure Virtex 6 FPGAs and access Master Module
Flash
Configuration DIP Switches
FPGA & DSP JTAG in
Clock Synthesiser Syncroniser
RS23210/100/1000
Ethernet
RS23210/100/1000
Ethernet
SLB
SAA71118 Video Decoder IP Conditioning
SAA71118 Video Decoder IP Conditioning
8 Configurable Video Inputs
8 Configurable Video Inputs
SLB
SAA71118 Video Decoder IP Conditioning
SAA71118 Video Decoder IP Conditioning
8 Configurable Video Inputs
8 Configurable Video Inputs
SLB
SAA71118 Video Decoder IP Conditioning
SAA71118 Video Decoder IP Conditioning
8 Configurable Video Inputs
8 Configurable Video Inputs
SLB
SAA71118 Video Decoder IP Conditioning
SAA71118 Video Decoder IP Conditioning
8 Configurable Video Inputs
8 Configurable Video Inputs
28 /
Video Add-On SLB (Sundance Local Bus) Module SMT909 16 CVBS video inputs
Multichannel Image Systems
29 /
FDP Populated with four SMT909 Video SLBs 64 channel CVBS Video Inputs System
SMT909
SMT909
SMT372T
Multichannel Image Systems