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http://www.bized.co.uk
Copyright 2006 – Biz/ed
Prepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud
Version 02 – October 2011
Session 6
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Copyright 2006 – Biz/ed
-Scrambler mini project discussion
-Finite State Machine
-What is FSM?
-Moore machine
-Mealy machine
-FSM in VHDL
6 Contents
2
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Scrambler mini project discussion
3
Session 6
B(i)=[b(i)+c(i)]mod2
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Session 6
FSM
4
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Any digital system consists of two part:
Data part
Responsible for the processing of data. The
processing is done through some blocks such as (full
adder, digital filter, decoder,…)
Control part
Describes how and when these blocks will
communicate with each other.
The control part is generally described using a finite
state machine.
Session 6
What is FSM
5
Data Part
Control Part
Inputs Outputs
Controls
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Finite State Machine
FSM is simply a finite number of states that
each state describes a certain set of control
outputs that are connected to the data part
blocks.
The transition between these states depends
mainly on the inputs of the FSM.
There are two main types of FSM:
Moore FSM
Mealy FSM
Session 6
What is FSM
6
S1
S2
S4
S3
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Assigning Moore Outputs
Use a combinational ‘process’ to model Output Logic Outputs are only dependant on the current state
Assigning Mealy Outputs Use a combinatorial ‘process’ to model Output Logic Outputs are dependant on the current state & the input
Session 6
FSM in VHDL
7
Outputs = f(Inputs, State)
Output
Logic
Output
Logic
Outputs = f(State)
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In a Moore finite state machine, the output of
the circuit is dependent only on the state of
the machine and not on its inputs.
Session 6
Moore FSM
8
Machine
State
Registers
Next
state
Present
state Outputs Inputs
Output
Logic
Next
State
Logic
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In a Mealy finite state machine, the output is
dependent both on the machine state as well
as on the inputs to the FSM.
Session 6
Mealy FSM
9
Machine
State
Registers
Next
state
Present
state Outputs Inputs
Output
Logic
Next
State
Logic
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Session 6
Moore FSM
10
state 1
state 2
transition
condition 1
transition
condition 2
state 1 state 2
transition condition 1 /
output 1
transition condition 2 /
output 2
Mealy FSM
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• Synchronous & asynchronous FSM
-Moore (Synchronous )
-Mealy(asynchronous )
11
Session 6
Example 26
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12
S0 / 0 S1 / 0 S2 / 1
0 1
1 0
reset
Meaning
of states:
S0: No
elements
of the
sequence
observed
S1: “1”
observed
S2: “10”
observed
Moore FSM that Recognizes Sequence “10”
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Session 6
13
Mealy FSM that Recognizes Sequence “10”
S0 S1
0 / 0 1 / 0 1 / 0
0 / 1 reset
Meaning
of states:
S0: No
elements
of the
sequence
observed
S1: “1”
observed
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Session 6
14
clock
input
Moore
Mealy
0 1 0 0 0
S0 S1 S2 S0 S0
S0 S1 S0 S0 S0
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-Finite State Machines Can Be Easily Described With Processes
-Synthesis Tools Understand FSM Description if Certain Rules Are Followed
-----State transitions should be described in a process sensitive to clock and asynchronous
reset signals only
-----Output function described using rules for combinational logic, i.e. as concurrent
statements or a process with all inputs in the sensitivity list
Session 6
3-FSM in VHDL
15
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The “3 Processes, 1 Clocked + separate transitions/actions” style
1-Process modeling “Next State Logic”
2-Process modeling "Current State Registers"
3-Process modeling “Output Logic”
Session 6
FSM in VHDL
16
State
Registers
Output
Logic
Next
State
Logic
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Next-State Logic Use a combinational ‘process’ to model next state logic process ( current_state, <in1>, <in2>, <in3> … )
Begin
case ( Current_State ) is
when <state1> =>
if ( <condition (<in1>, <in2>...)> ) then
Next_State <= <state2>;
elsif ( <condition (<in1>, <in2>...)> ) then
Next_State <= <state3>;
...
end process;
Session 6
FSM in VHDL
17
Next
State
Logic
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Current-State Use a sequential ‘process’ to describe current state logic* Process (clock)
Begin
if rising_edge (clock) then
if ( reset = '1' ) then -- synchronous reset
Current_State <= <reset_state>;
else
Current_State <= Next_State;
end if;
end if;
end process;
Session 6
FSM in VHDL
18
State
Registers
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• Vending Machine
-Moore
-Mealy
19
Session 6
Example 27
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Vending Machine
Specifications
-Deliver package of gum after 15 piaster deposited
-Single coin slot for 5 and 10 piasters
Step 1 : Understand the problem
Draw a block diagram
20
Session 6
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Step 2 : Draw a state diagram
21
Session 6
S3
S6
S8 S7
S5
S2
S4
S1
S0
N = 5 piaster
D = 10 piaster
N
N
N
N
D
D
D
D
open open
open open open
Reset
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Step 3 : State Minimization
22
Session 6
Reset
S2
S3
S1
N = 5 piaster
D = 10 piaster
D
open
S0
N
D
N
N,D
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Step 4
Write VHDL code (Moore)
Inputs and Outputs
23
Session 6
open
S2
S3
S1 D
open
S0
Reset
N
D
N
N,D
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vend_machine_moore is
Port (N : in STD_LOGIC;
D : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
tank_open : out STD_LOGIC);
end vend_machine_moore;
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Define the states
We need to define a new type for the names of the states
24
Session 6
open
S2
S3
S1 D
open
S0
Reset
N
D
N
N,D
architecture Behavioral of vend_machine_moore is
type states is (s0,s1,s2,s3);
signal n_state,p_state :states;
begin
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The transition process
Responsible for the transition of states from present state to next state.
25
Session 6
open
S2
S3
S1 D
open
S0
Reset
N
D
N
N,D
transition :process(clk,reset)
begin
if reset='1' then
p_state <=s0 ;
elsif rising_edge(clk) then
p_state <= n_state ;
end if;
end process transition;
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Next State logic process
Responsible for generating the next state logic.
26
Session 6
open
S2
S3
S1 D
open
S0
Reset
N
D
N
N,D
next_state :process(N,D,p_state)
--p_state in list to trigger process if ips are constants
begin
case p_state is
when s0 =>
if N='1' then
n_state <= s1;
elsif D='1' then
n_state <= s2;
else
n_state <= s0;
end if;
when s1 =>
if N='1' then
n_state <= s2;
elsif D='1' then
n_state <= s3;
else n_state <= s1;
end if;
when s2 =>
if N='1' then
n_state <= s3;
elsif D='1' then
n_state <= s3;
else n_state <= s2;
end if;
when s3 =>
n_state <= s0;
--------------
end case;
end process next_state;
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Output logic process
Responsible for generating the output logic.
27
Session 6
open
S2
S3
S1 D
open
S0
Reset
N
D
N
N,D
output_logic :process(p_state)
begin
case p_state is
when s0 => tank_open <='0';
when s1 => tank_open <='0';
when s2 => tank_open <='0';
when s3 => tank_open <='1';
end case;
end process output_logic ;
end Behavioral;
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Step 4
Write VHDL code (Mealy)
Note : the number of states in Mealy FSM 3 !!
28
Session 6
S2
S1 D, 0
S0
Reset
N, 0
N, 0
N/D, 1 D, 1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vend_machine_moore is
Port (N : in STD_LOGIC;
D : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
tank_open : out STD_LOGIC);
end vend_machine_moore;
architecture Behavioral of vend_machine_mealy is
type states is (s0,s1,s2);
signal n_state,p_state :states;
begin
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29
Session 6
transition :process(reset,clk)
begin
if clr='1' then
p_state <=s0 ;
elsif rising_edge(clk) then
p_state <= n_state ;
end if;
end process transition;
next_state :process(N,D,p_state)
begin
case p_state is
when s0 =>
if N='1' then
tank_open <='0';
n_state <= s1;
elsif D='1' then
n_state <= s2;
tank_open <='0';
else n_state <= s0;
tank_open <='0';
end if;
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30
Session 6
when s1 =>
if N='1' then
n_state <= s2;
tank_open <='0';
elsif D='1' then
n_state <= s0;
tank_open <='1';
else n_state <= s1;
tank_open <='0';
end if;
when s2 =>
if N='1' then
n_state <= s0;
tank_open <='1';
elsif D='1' then
n_state <= s0;
tank_open <='1';
else n_state <= s2;
tank_open <='0';
end if;
end case;
end process next_state;
end Behavioral;
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• Gumball Vending Machine
31
Session 6
lab 12
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32
Session 6
Exercise 6
• String Detector
to detect input sequence (1110)
draw state diagram
(Mealy and Moore)
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• String Detector
to detect input sequence (1110) Moore or Mealy
33
Session 6
lab 13
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Questions
Session-6
34
Session 6
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Take Your Notes Print the slides and take your notes here
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Session 6
35
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See You Next Session
Session 6
36