MOSFET SCALING CRISIS AND EVOLUTION OF NANOELECTRONIC

DEVICES

M ROSHINI 13PN02

MTECH NANOTECHNOLOGYPSG COLLEGE OF TECHNOLOGY

OBJECTIVE

• The development of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) scaling and its crisis.

• The evolution of the new nanoelectronic devices and their potential applications.

INTRODUCTION

• MOSFET scaling is mainly to increase the speed of devices and to increase the packaging density of integrated circuits.

• Nowadays, scaling down of MOSFET is approaching its limits.

• So there are recent developments in MOSFET scaling and new emerging devices available to overcome the limits.

• Working in different strategies to extend the Moore’s law.

• we able to fit these tiny devices onto a microchip to perform several billion operations in a single second, and that becomes double in the speed of these microchips every 18 months.

ADVANTAGES OF SCALING• More circuits are fabricated on each silicon wafer, this

leads to cheaper circuits.

• Smaller transistors and shorter interconnects lead to smaller capacitances and higher IC speed.

• Smaller transistors lead to reduced power supply voltages and power consumption.

• Without scaling, the single pc microprocessor chip requires the output of the electrical power plant to work.

PROBLEMS ON SCALING• Overheating and possible evaporation become major concerns.

• Increased electric field within the oxide and increased leakage gate-current.

• The classical physics does not work and quantum effects need to be employed for modeling device characteristics.

• Electrons, in quantum mechanics, are represented by traveling waves, the potential barrier becomes decaying functions.

• As the barrier thickness decreases the tunneling probability increases.

• The static and dynamic power consumption.

MOSFET SCALING IN NANO SCALE

1)STRAINED SILICON TECHNOLOGY(90nm)

• silicon atoms are stretched beyond their normal inter-atomic distance by putting the layer of silicon over a substrate of Silicon Germanium (SiGe).

• As the atoms in the silicon layer align with the atoms of the underlying SiGe layer the links between the silicon atoms become stretched - thereby leading to strained silicon.

STRAINED SILICON TECHNOLOGY

• 90nm process technology.

• Moving these silicon atoms farther apart reduces the atomic forces that interfere with the movement of electrons through the transistors.

• Thus better mobility resulting in better chip performance and lower energy consumption.

• These electrons can move 70% faster allowing strained silicon transistors to switch 35% faster.

STRAINED SILICON TECHNOLOGY

• Recent methods of inducing strain include doping the source and drain with lattice atoms such as germanium and carbon.

• Germanium doping of up to 20% in the PMOS source and drain causes uniaxial compressive strain in the channel, increasing hole mobility.

• Carbon doping as low as 0.25% in the NMOS source and drain causes uniaxial tensile strain in the channel, increasing electron mobility.

• Covering the NMOS transistor with a highly stressed silicon nitride layer is another way to create uniaxial tensile strain.

2)65nm TECHNOLOGY• The oxide thickness has been reduced from 300 nm for the

10 um technology to 1.2 nm for the 65 nm technology

• Manufacturing thin oxide is not easy. If the oxide is too thin, tunneling leakage gate current becomes serious.

• At 1.2 nm, SiO2 leaks 1000 A/cm2 .

• If an IC chip contains 1 mm2 total area of this thin dielectric, the chip oxide leakage current would be 10 A.

3)HIGH-K DIELECTRIC MATERIALS (45nm)

• High-k dielectric materials replaces SiO2 to reduce leakage gate current.

• Zirconium Dioxide (ZrO2), Aluminium Oxide (Al2O3) and Hafnium Oxide (HfO2) have relative dielectric constants higher than SiO2.

• For example a 6 nm thick HfO2 film is equivalent to a 1 nm SiO2 in the sense that both films give the same value of channel current.

• But with thicker oxide film the leakage gate current is several orders of magnitude less than in SiO2 films.

METAL GATES(45nm)

• The gate of MOSFET was made of polycrystalline silicon (poly-Si) because of its ability to withstand high temperatures without reacting with SiO2.

• The depletion in the semi metallic poly-Si adds “dielectric thickness” to the true SiO2, thus, increasing oxide thickness.

• Because of the high carrier density in metals, depletion effect is negligible. Hence the use of metals is preferred.

• After 2008, the trend is to introduce metal gates and replace SiO2 by high-k material.

Wet lithography

4)WET LITHOGRAPHY(32nm)• Optical Lithography removes specific areas of oxides, with a

photoresist, deep ultraviolet light and reduction optical lenses, different patterns can be printed.

• Suitable materials for lenses and masks at wavelength shorter than 193 nm, wet lithography is used to print the fine patterns.

• In wet lithography the gap between the lens and the wafer is filled with water.

• When the light enters the water its wavelength is reduced thus improving the resolution.

• Other liquids with higher refractive index can be used to improve the resolution.

5) FINFET(22nm)

FINFET allow gate length scaling beyond limit of conventional MOSFET.

• With Vgs < Vt, an N-channel MOSFET in off state. But leakage current still flow between the drain and the source causing a power consumption issue in standby operation.

• It is required to maximize the gate-to-channel capacitance and to minimize the drain-to-channel capacitance, to reduce drain leakage current.

• As the channel length is reduced, the drain-to-source and the drain-to channel distance is reduced and the influence of the drain will increase.

• To eliminate leakage, it is required to provide gate control from more than one side of the channel.

• Then structure called as multigate MOSFET or sometimes Fin-FET.

Source Drain

Gate

Source Drain

Gate

Source Drain

Gate

SUBSTRATE FIN-ETCH OXIDE DEPOSITION

PLANARIZATION

RECESS ETCH GATE OXIDEDEPOSITION OF THE GATE

SOI TRANSISTOR

FINFET(22nm)

GATE WRAPPED AROUND THE CHANNEL

SOI Ω-gate MOSFET

SOI Π-gate MOSFET

SOI gate-all-around MOSFET

bulk tri-gate MOSFET

SOI Fin-FET SOI triple-gate MOSFET

ADVANTAGES OF FINFET• Natural length represents length of the region of the channel that is controlled by

drain.

• the formula shows, natural length parameter depends on dielectric constant of gate oxide and silicon, thickness of silicon and gate oxide.

• By increasing,gate control from more than one side of the channel, natural length can be decreased.

TRANSISTOR DIMENSIONS

• 90-65 nm

• 65-45 nm

• 45-30 nm

PROBLEMS

• Performance

• Leakage current

• Effective output

SOLUTIONS

• Strained silicon, nickel silicide (NiSi), low-k dielectric (CDO) for interconnects

• high-k dielectric for a gate insulating layer

• Tri-gate transistors

OFET-based Flexible Display

NanoelectronicsStarts from here

NANO ELECTRONIC DEVICES : OFET• Organic semiconductors can be printed on plastic, flexible substrates at low

temperature by solution-based techniques, which would result in a practical use of flexible displays.

• Organic field-effect transistors (OFETs) also sometimes known as organic thin-film transistors.

• In an OFET, an organic semiconductor is deposited to bridge the source and drain electrodes, and is itself spaced from the gate electrode by an insulating gate dielectric layer.

• OFETs can be prepared either by vacuum evaporation of small molecules, by solution-casting of polymers or small molecules, or by mechanical transfer of a peeled single-crystalline organic layer onto a substrate.

• Four configurations based on relative placement of source–drain electrodes, the organic semiconductor layer, and the dielectric layer.

• relative placement of the source–drain electrodes, the organic semiconductor layer, and the dielectric layer, in OFETs, there are four possible configurations:

Single electron transistor

NANOELECTRONIC DEVICES: SINGLE ELECTRON TRANSISTOR

• The operation of SET is based on the behavior of small conducting particles surrounded by insulating material. These particles are called islands.

• Since the insulating layer that surrounds the island, the transport of electrons to and from the island is possible only by tunneling effect.

• A SET is formed of a drain, source, gate and an island.

• Its operation is similar to that of MOSFET except that electron conduction takes place one electron at a time while in MOSFET many electrons simultaneously take part in the conduction.

FABRICATION OF THE TI/TIOX SET BY THE STM NANO-OXIDATION PROCESS.

• A 3 nm thin titanium (Ti) metal film is deposited on a 100 nm thermally oxidized SiO2/n-Si substrate.

• The Ti surface was oxidized by anodization through the water adhered to the surface of the Ti from the atmosphere, using the STM tip as a cathode, forming nanometer size Ti oxide (TiOx) lines.

• Formation of island region by STM.

• Then ohmic contacts of source and drain can be formed.

SET

SET

• The single electron transistor is made of an island connected through two tunneling junctions to a drain and a source electrode, and through a capacitor to a gate electrode.

• In classical physics, when an electron is in a potential, it is unable to go anywhere where the potential is higher.

• A single electron transistor is based on the idea of quantum tunneling,where the electrons acts as the travelling wave.

• As this analysis of tunneling shows, as the width of your barrier increases, or the ratio in energies between your electron and the potential barrier decreases, the number of electrons that will be able to tunnel decreases very rapidly.

SET

• The drain current-voltage characteristics of the SET were measured at room temperature. The gate bias was set to 2 V.

• Between the drain bias of 0 V and -0.75 V, four clear Coulomb staircases with a ~150 mV period are observed.

• The conductance oscillates with the increase of the drain bias with almost the same 150 mV period.

• The Coulomb staircase may be attributed to the asymmetrical structure of the two tunneling junctions. One TiOx tunneling junction has a width of 18 nm, while the other junction is 27 nm wide.

• The height of the Coulomb steps becomes larger with larger applied drain bias. This may be attributed to the increase of the tunneling probability of the electron through the TiOx tunneling barrier.

SET

• The Coulomb energy is given by

Ec= e2/2C

• where e is the charge on an electron and C is the total capacitance of the source and drain junctions and the gate capacitor.

• When the bias between the source and drain is greater than e/C called the Coulomb gap voltage, electrons actively tunnel across the junctions, resulting in a current through the transistor independent of the gate bias.

• SET-based radio-frequency mixers, SET-based charge sensors, RF-SET ultrasensitive electrometers applicable in scientific instrumentation, metrology, and nanoelectromechanical (NEM) systems are also available.

CONCLUSION

• The conventional scaling trend for the device, i.e. scaling by reducing device size, is no longer valid for the future generation devices where quantum mechanical effect plays a great role and tunneling and leakage problems will severe the performance of devices. Therefore, scientists are working with different strategies to extend Moore’s Law, such as improving electrostatic control over channel by means of continued scaling with high K/Metal gate stack and multi gate structures for higher drive current by improving mobility of charge carriers that is done by adopting high mobility channel materials (using Ge or III-V materials) and strain engineering.

REFERENCES• 1] C.C. Hu, Modern Semiconductor Devices for Integrated Circuits, Pearson,

Boston, USA, 2010.

• [2] R. Waser (Editor), Nanoelectronics and Information Technology, Wiley-VCH GmbH, Wenheim, Germany, 2003.

• [3] B. Rogers, S. Pennathur and J. Adams, Nanotechnology, Understanding Small Systems, CRC Press, Taylor and Francis Group, Boca Raton, USA, 2008.

• physicsworld.com/cws/article/news/17742/1/SET2 1/

• luciano.stanford.edu/~shimbo/set.html

• vhosts.science.nus.edu.sg/organicelectronics/?p=512

• web.donga.ac.kr/seojh/Research_Transistors.html

• www.cstf.kyushu-u.ac.jp/~adachilab/lab/?page_id=3898

• http://ixbtlabs.com/articles2/intel-65nm/indexOLD.htm

• http://en.wikipedia.org/wiki/Strained_silicon

Questions?