14
Dr. S.Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal ICE 4010: MICRO ELECTRO MECHANICAL SYSTEMS (MEMS) Lecture #05 CMOS Logic Gates Dr. S. Meenatchi Sundaram Email: [email protected] 1

Lecture 05 cmos logic gates

Embed Size (px)

Citation preview

Page 1: Lecture 05   cmos logic gates

Dr. S.Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

ICE 4010: MICRO ELECTRO MECHANICAL SYSTEMS (MEMS)

Lecture #05

CMOS Logic Gates

Dr. S. Meenatchi Sundaram

Email: [email protected]

1

Page 2: Lecture 05   cmos logic gates

CMOS NAND Gate

2Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

A B Y

0 0

0 1

1 0

1 1

A

B

Y

Page 3: Lecture 05   cmos logic gates

CMOS NAND Gate

3Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

A B Y

0 0 1

0 1

1 0

1 1

A=0

B=0

Y=1

OFF

ON ON

OFF

Page 4: Lecture 05   cmos logic gates

CMOS NAND Gate

4Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

A B Y

0 0 1

0 1 1

1 0

1 1

A=0

B=1

Y=1

OFF

OFF ON

ON

Page 5: Lecture 05   cmos logic gates

CMOS NAND Gate

5Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

A B Y

0 0 1

0 1 1

1 0 1

1 1

A=1

B=0

Y=1

ON

ON OFF

OFF

Page 6: Lecture 05   cmos logic gates

CMOS NAND Gate

6Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

A B Y

0 0 1

0 1 1

1 0 1

1 1 0

Page 7: Lecture 05   cmos logic gates

CMOS NAND Gate

7Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

Page 8: Lecture 05   cmos logic gates

Series and Parallel

8

• nMOS: 1 = ON

• pMOS: 0 = ON

• Series: both must be ON

• Parallel: either can be ON

Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

(a)

a

b

a

b

g1

g2

0

0

a

b

0

1

a

b

1

0

a

b

1

1

OFF OFF OFF ON

(b)

a

b

a

b

g1

g2

0

0

a

b

0

1

a

b

1

0

a

b

1

1

ON OFF OFF OFF

(c)

a

b

a

b

g1 g2 0 0

OFF ON ON ON

(d) ON ON ON OFF

a

b

0

a

b

1

a

b

11 0 1

a

b

0 0

a

b

0

a

b

1

a

b

11 0 1

a

b

g1 g2

Page 9: Lecture 05   cmos logic gates

Compound Gates

9

• Compound gates can do any inverting function

• Ex:

Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

(AND-AND-OR-INVERT, AOI22)Y A B C D= +i i

A

B

C

D

A

B

C

D

A B C DA B

C D

B

D

YA

CA

C

A

B

C

D

B

D

Y

(a)

(c)

(e)

(b)

(d)

(f)

Page 10: Lecture 05   cmos logic gates

Compound Gates

10

• O3AI

• Ex:

Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

( )Y A B C D= + + i

A B

Y

C

D

DC

B

A

Page 11: Lecture 05   cmos logic gates

Compound Gates

11Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

Page 12: Lecture 05   cmos logic gates

Compound Gates

12Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

Page 13: Lecture 05   cmos logic gates

Compound Gates

13Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

a b ā �� T1 T2 T3 T4 T5 T6 T7 T8 Y

0 0 1 1 OFF ON ON ON OFF ON OFF OFF OFF

0 1 1 0 ON ON ON OFF OFF OFF OFF ON ON

1 0 0 1

1 1 0 0

T1

T2

T3

T4

T5

T6

T7

T8

Page 14: Lecture 05   cmos logic gates

Compound Gates

14

• A EXOR B

Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal