Term Paper On Intel R© 80486 MicroprocessorDARPAN DEKIVADIYA

09BCE008Department of Computer Science & Engineering

Institute of TechnologyNirma University

Ahmedabad 382 481Gujarat, India.

Email: 09BCE008@nirmauni.ac.in

JEMIS JIVANI09BCE017

Department of Computer Science & EngineeringInstitute of Technology

Nirma UniversityAhmedabad 382 481

Gujarat, India.Email: 09BCE017@nirmauni.ac.in

I. INTRODUCTION1) The 32-bit 80486 is the next evolutionary step up from

the 80386.

2) One of the most obvious feature included in 80486is a built in math co processor. This coprocessor isessentially the same as the 80386 but being integratedon the chip allows it to execute math instruction aboutthree times as fast as a 80386/387 combination.

3) 80486 is an 8kbyte code and cache

4) To make room for the additional signal, the 80486 ispacked in 168 pin, pin grid array package instead of132 pin PGA used for the 80386.

5) The 32-bit CPU 80486 from Intel is the first processorwith an inbuilt floating point unit.

Fig. 1. Intel 80486 Architecture

II. ARCHITECTURE

1) A 31- A2: Address outputs A31-A2 provide the memoryand I/O with the address during normal operation. Dur-ing a cache line invalidation A31-A4 are used to drivethe microprocessor.//

2) A20M3: The address bit 20 mask causes the 80486 towrap its address around from location 000FFFFFH to00000000H as in 8086. This provides a memory systemthat functions like the 1M byte real memory system inthe 8086 processors.

3) ADS: The address data strobe becomes logic zero toindicate that the address bus contains a valid memoryaddress.

4) AHOLD: The address hold input causes themicroprocessor to place its address bus connections attheir high-impedance state, with the remainder of thebuses staying active. It is often used by another busmaster to gain access for a cache invalidation cycle.

5) BREQ: This bus request output indicates that the 486has generated an internal bus request.

6) 3 0 BE-BE: Byte enable outputs select a bank ofthe memory system when information is transferredbetween the microprocessor and its memory and I/O.The BE3 signal enables D31 - D24, BE2 enablesD23-D16, BE1 enables D15 - D8 and BE0 enablesD7-D0.

7) BOFF: The Back-off input causes the microprocessorto place its buses at their high impedance state duringthe next cycle. The microprocessor remains in the bushold state until the BOFF pin is placed at logic 1 level.

8) NMI: The non-mask able interrupt input requests a type2 interrupt.

9) BRDY: The burst ready input is used to signal themicroprocessor that a burst cycle is complete.

10) KEN: The cache enable input causes the current bus tobe stored in the internal.

11) LOCK: The lock output becomes a logic 0 for anyinstruction that is prefixed with the lock prefix.

12) W / R: current bus cycle is either a read or a write.

13) IGNNE: The ignore numeric error input causes thecoprocessor to ignore floating point error and tocontinue processing data. The signal does not affect thestate of the FERR pin.

14) FLUSH: The cache flush input forces the microprocessorto erase the contents of its 8K byte internal cache.

15) EADS: The external address strobe input is used withAHOLD to signal that an external address is used toperform a cache invalidation cycle.

16) FERR: The floating point error output indicates thatthe floating point coprocessor has detected an errorcondition. It is used to maintain compatibility withDOS software.

17) 8 BS: The bus size 8, input causes the 80486 to structureitself with an 8-bit data bus to access byte-wide memoryand I/O components.

18) 16 BS: The bus size 16, input causes the 80486to structure itself with a 16-bit data bus to accessword-wide memory and I/O components.

19) PCHK: The parity check output indicates that a parityerror was detected during a read operation on the DP3- DP0 pin.

20) PLOCK: The pseudo-lock output indicates that currentoperation requires more than one bus cycle to perform.This signal becomes a logic 0 for arithmetic coprocessoroperations that access 64 or 80 bit memory data.

21) PWT: The page write through output indicates the stateof the PWT attribute bit in the page table entry or thepage directory entry.

22) RDY: The ready input indicates that a non-burst buscycle is complete. The RDY signal must be returnedor the microprocessor places wait states into its timinguntil RDY is asserted.

Fig. 2. pin diagram of 80486

Flag Registers1) The extended flag register EFLAG is illustrated in the

figure. The only new flag bit is the AC alignment check,used to Indicate that the microprocessor has accessed aword at an odd address or a double word boundary.

2) Efficient software and execution require that data bestored at Word or double word boundaries.

3) Other common flags between 80486-80386 likecarry flag(CF),parity flag(PF),auxiliary flag(AF),zeroflag(ZF), Sign flag(SF),trap flag(TF),interrupt flag(IF),direction flag(DF),overflow flag(OF) are set or resetaccording to 80486 instruction set and same as 80386.

4) In the common flags six are control flag and three flagsare conditional flags.

5) The 80486 has four control flag register which is sameas in 80386 microprocessor. Five extra bits are addedto the 80486 is :Alignment mask (AM), numeric error(NE), write protect (WP),cache disable (CD), not-writethrough (NW).

6) AM flag is set to 1 when data alignment is checkalignment mask in or set to 0 when alignment maskout. A double word of the data that is not stored at anaddress that is a multiple of four is said to be unaligned.If an unaligned double word storage location accessed,two memory bus cycles must be performed. The extrabus cycle introduce because the data is unalignedreduce overall system performance so, alignment checkflag are used to identify alignment.

7) CD and NW flags are used to enable and control theoperation of on the on chip cache memory. To enablethe cache memory for the operation, CD must becleared to 0.the NW flag enables write through andcache validation cycles to take place when it is set to 0. Fig. 3. flag register of 80486

General Purpose Reg.

Fig. 4. general purpose register of 80486

Features

• Addressing modes

1. Scaled indexed mode-Content of an index register are multiply by scale factorthat may be added further to get the operand offset.2. Based scaled indexed mode-Content of an index register are multiply by scalefactor that may be then added to base register to get theoperand offset.3.Based scaled indexed mode with displacement-Content of an index register are multiply by scalefactor and the result is added to a base register and adisplacement to get operand offeset.

• Interrupts

-80486 can handle 256(00 to FFh) hardware interruptson its INTR pin. The structure of the interrupt vectortable(IVT) is same as the 8086 and it is handled byinterrupt descriptor table which contain 256 possibleinterrupt vectors. Out of 256, 32 are used by Intel andremaining are free for user.

• Data types

1.Signed/unsigned data type-8-bit, 16-bit 32-bit signed/unsigned integer aresupported.2.Floating point data type-Single precision, double precision extended precisionreal data are supported3.BCD data type-It supports 8-bit packed and unpacked data4.String data type-String of bit, bytes, words and double words aresupported by CPU, each may contain up to 4GHz.5.ASCII data type-It is used for representation of characters.6.Pointer data type-48-bit pointers containing 32-bit offset at the LSB and16-bit selector at MSB are supported by CPU.

Memory System

1) The memory system for the 486 is identical to 386microprocessor. The 486 contains 4G bytes of memorybeginning at location 00000000H and ending atFFFFFFFFH.

2) The major change to the memory system is internalto 486 in the form of 8K byte cache memory, whichspeeds the execution of instructions and the acquisitionof data.

3) Another addition is the parity checker/ generator builtinto the 80486 microprocessor.

Parity Checker / Generator:• Parity is often used to determine if data are correctly

read from a memory location. INTEL has incorporatedan internal parity generator / decoder.

• Parity is generated by the 80486 during each write cycle.Parity is generated as even parity and a parity bit isprovided for each byte of memory. The parity check bitsappear on pins DP0-DP3, which are also parity inputsas well as parity outputs.

• These are typically stored in memory during each writecycle and read from memory during each read cycle.

• On a read, the microprocessor checks parity and generatesa parity check error, if it occurs on the PCHK pin. Aparity error causes no change in processing unless theuser applies the PCHK signal to an interrupt input.

• Interrupts are often used to signal a parity error inDS-based computer systems. This is same as 80386,except the parity bit storage.

• If parity is not used, Intel recommends that the DP0 -DP3 pins be pulled up to +5v.

Cache Memory• The cache memory system stores data used by a program

and also the instructions of the program. The cache isorganized as a 4 way set associative cache with eachlocation containing 16 bytes or 4 double words of data.

• Control register CR0 is used to control the cache with twonew control bits not present in the 80386 microprocessor.

Summary

1) Thus in sort 80486 is updated version of 80386.

2) It has 8Byte code and cache.

3) It is the processor with inbuilt floating point unit4) It has tightly coupled pipelining which allows 80486 to

complete an instruction like a simple ALU.

5) It has more no of flag registers then 8086 like AC,I/Opl, NT, RF VM.

6) It has the same memory system as 80386 have. Whichcontains the memory addresses from 00000000H toFFFFFFFFH.

7) It also has in built parity checker and parity generatorcircuit which is used to check that a data read frommemory is correct or not.

Reference

• The architecture of 80386-80486 microprocessor By Wal-ter A. Treble and Avtar Singh.

• www.microprocessor-assembly.com / 80486• www.ebooks.com/80486-processor