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The 4-bit processors
Intel 4004: first single-chip microprocessor
Introduced November 15, 1971
Clock rate 740 kHz[1]
0.07 MIPS
Bus Width 4 bits (multiplexed address/data due to limited pins)
PMOS
Number of Transistors 2,300 at 10 µm
Addressable Memory 640 bytes
Program Memory 4 KB (4 KB)
One of the earliest Commercial Microprocessors (cf. Four Phase Systems AL1, F14 CADC)
Originally designed to be used in Busicom calculator
MCS-4 Family:
4004-CPU
4001-ROM & 4 Bit Port
4002-RAM & 4 Bit Port
4003-10 Bit Shift Register
4008-Memory+I/O Interface
4009-Memory+I/O Interface
Intel 4040
MCS-40 Family:
4040-CPU
4101-1024-bit (256 × 4) Static RAM with separate I/O
4201-4 MHz Clock Generator
4207-General Purpose Byte I/O Port
4209-General Purpose Byte I/O Port
4211-General Purpose Byte I/O Port
4265-Programmable General Purpose I/O Device
4269-Programmable Keyboard Display Device
4289-Standard Memory Interface for MCS-4/40
4308-8192-bit (1024 × 8) ROM w/ 4-bit I/O Ports
4316-16384-bit (2048 × 8) Static ROM
4702-2048-bit (256 × 8) EPROM
4801–5.185 MHz Clock Generator Crystal for 4004/4201A or 4040/4201A
The 8-bit processors
8008
Introduced April 1, 1972
Clock rate 500 kHz (8008–1: 800 kHz)
0.05 MIPS
Bus Width 8 bits (multiplexed address/data due to limited pins)
Enhancement load PMOS logic
Number of Transistors 3,500 at 10 µm
Addressable memory 16 KB
1
Typical in early 8 bit microcomputers, dumb terminals, general calculators, bottling machines
Developed in tandem with 4004
Originally intended for use in the Datapoint 2200 microcomputer
Key volume deployment in Texas Instruments 742 microcomputer in >3,000 Ford dealerships
8080
Introduced April 1, 1974
Clock rate 2 MHz (very rare 8080B: 3 MHz)
0.64 MIPS
Bus Width 8 bits data, 16 bits address
Enhancement load NMOS logic
Number of Transistors 6,000
Assembly language downwards compatible with 8008.
Addressable memory 64 KB
Up to 10X the performance of the 8008
Used in the Altair 8800, Traffic light controller, cruise missile
Required six support chips versus 20 for the 8008
8085
Introduced March 1976
Clock rate 3 MHz [2]
0.37 MIPS
Bus Width 8 bits data, 16 bits address
Depletion load NMOS logic
Number of Transistors 6,500 at 3 µm
Binary compatible downwards with the 8080.
Used in Toledo scales. Also was used as a computer peripheral controller – modems, harddisks,printers, etc...
CMOS 80C85 in Mars Sojourner, Radio Shack Model 100 portable.
High level of integration, operating for the first time on a single 5 volt power supply, from 12 volts previously. Also featured serial
I/O,3 maskable interrupts,1 Non-maskable interrupt,1 externally expandable interrupt w/[8259],status,DMA.
MCS-85 Family:
8155-RAM+ 3 I/O Ports+Timer "Active Low CS"
8185-SRAM
8202-Dynamic RAM Controller
8203-Dynamic RAM Controller
8205-1 Of 8 Binary Decoder
8206-Error Detection & Correction Unit
8207-DRAM Controller
8210-TTL To MOS Shifter & High Voltage Clock Driver
8216-4 Bit Parallel Bidirectional Bus Driver
8219-Bus Controller
8222-Dynamic RAM Refresh Controller
8226-4 Bit Parallel Bidirectional Bus Driver
8232-Floating Point Processor
8237-DMA Controller
8251-Communication Controller
8253-Programmable Interval Timer
8254-Programmable Interval Timer
8255-Programmable Peripheral Interface
2
8256-Multifunction Support Controller
8257-DMA Controller
8259-Programmable Interrupt Controller
8271-Programmable Floppy Disk Controller
8272-Single/Double Density Floppy Disk Controller
8273-Programmable HDLC/SDLC Protocol Controller
8274-Multi-Protocol Serial Controller
8275-CRT Controller
8276-Small System CRT Controller
8279-KeyBoard/Display Controller
8283-8-bit Inverting Latch with Output Buffer
8291-GPIB Talker/Listener
8292-GPIB Controller
8293-GPIB Transceiver
8294-Data Encryption/Decryption Unit+1 O/P Port
8295-Dot Matrix Printer Controller
8296-GPIB Transceiver
8297-GPIB Transceiver
8355-16,384-bit (2048 × 8) ROM with I/O
8755-EPROM+2 I/O Ports
Microcontrollers
They are ICs with CPU,RAM,ROM (or PROM or EPROM),I/O Ports,Timers & Interrupts
Intel 8048
Single accumulator Harvard architecture
MCS-48 family:
8020-Single-Component 8-Bit Microcontroller
8021-Single-Component 8-Bit Microcontroller
8022-Single-Component 8-Bit Microcontroller With On Chip A/D Converter
8035-Single-Component 8-Bit Microcontroller
8039-Single-Component 8-Bit Microcontroller
8040-Single-Component 8-Bit Microcontroller
8041-Universal Peripheral Interface 8-Bit Slave Microcontroller
8641-Universal Peripheral Interface 8-Bit Slave Microcontroller
8741-Universal Peripheral Interface 8-Bit Slave Microcontroller
8042-Universal Peripheral Interface 8-Bit Slave Microcontroller
8742-Universal Peripheral Interface 8-Bit Slave Microcontroller
8243-Input/Output Expander
8048-Single-Component 8-Bit Microcontroller
8048-Single-Component 8-Bit Microcontroller 8748-Single-Component 8-Bit Microcontroller
8049-Single-Component 8-Bit Microcontroller
8048-Single-Component 8-Bit Microcontroller 8749-Single-Component 8-Bit Microcontroller
8050-Single-Component 8-Bit Microcontroller
Intel 8051
Single accumulator Harvard architecture
3
MCS-51 Family:
8031-8-Bit Control-Oriented Microcontroller
8032-8-Bit Control-Oriented Microcontroller
8044-High Performance 8-Bit Microcontroller
8344-High Performance 8-Bit Microcontroller
8744-High Performance 8-Bit Microcontroller
8051-8-Bit Control-Oriented Microcontroller
8052-8-Bit Control-Oriented Microcontroller
8054-8-Bit Control-Oriented Microcontroller
8058-8-Bit Control-Oriented Microcontroller
8351-8-Bit Control-Oriented Microcontroller
8352-8-Bit Control-Oriented Microcontroller
8354-8-Bit Control-Oriented Microcontroller
8358-8-Bit Control-Oriented Microcontroller
8751-8-Bit Control-Oriented Microcontroller
8752-8-Bit Control-Oriented Microcontroller
8754-8-Bit Control-Oriented Microcontroller
8758-8-Bit Control-Oriented Microcontroller
80151-8-Bit Control-Oriented Microcontroller
83151-8-Bit Control-Oriented Microcontroller
87151-8-Bit Control-Oriented Microcontroller
80152-8-Bit Control-Oriented Microcontroller
83152-8-Bit Control-Oriented Microcontroller
80251-8-Bit Control-Oriented Microcontroller
87251-8-Bit Control-Oriented Microcontroller
MCS-96 Family
8094-16-Bit Microcontroller (48-Pin ROMLess Without A/D)
8095-16-Bit Microcontroller (48-Pin ROMLess With A/D)
8096-16-Bit Microcontroller (68-Pin ROMLess Without A/D)
8097-16-Bit Microcontroller (68-Pin ROMLess With A/D)
8394-16-Bit Microcontroller (48-Pin With ROM Without A/D)
8395-16-Bit Microcontroller (48-Pin With ROM With A/D)
8396-16-Bit Microcontroller (68-Pin With ROM Without A/D)]
8397-16-Bit Microcontroller (68-Pin With ROM With A/D)
8794-16-Bit Microcontroller (48-Pin With EROM Without A/D)
8795-16-Bit Microcontroller (48-Pin With EROM With A/D)
8796-16-Bit Microcontroller (68-Pin With EROM Without A/D)
8797-16-Bit Microcontroller (68-Pin With EROM With A/D)
8098-16-Bit Microcontroller
8398-16-Bit Microcontroller
8798-16-Bit Microcontroller
80196-16-Bit Microcontroller
83196-16-Bit Microcontroller
87196-16-Bit Microcontroller
80296-16-Bit Microcontroller
The bit-slice processor
3000 Family
4
Intel D3002.
Introduced 3rd Qtr, 1974 Members of the family
3001-Microcontrol Unit
3002-2-bit Arithmetic Logic Unit slice
3003-Look-ahead Carry Generator
3205-High-performance 1 Of 8 Binary Decoder
3207-Quad Bipolar-to-MOS Level Shifter and Driver
3208-Hex Sense Amp and Latch for MOS Memories
3210-TTL-to-MOS Level Shifter and High Voltage Clock Driver
3211-ECL-to-MOS Level Shifter and High Voltage Clock Driver
3212-Multimode Latch Buffer
3214-Interrupt Control Unit
3216-Parallel,Inverting Bi-Directional Bus Driver
3222-Refresh Controller for 4K NMOS DRAMs
3226-Parallel,Inverting Bi-Directional Bus Driver
3232-Address Multiplexer and Refresh Counter for 4K DRAMs
3242-Address Multiplexer and Refresh Counter for 16K DRAMs
3245-Quad Bipolar TTL-to-MOS Level Shifter and Driver for 4K
3246-Quad Bipolar ECL-to-MOS Level Shifter and Driver for 4K
3404-High-performance 6-bit Latch
3408-Hex Sense Amp and Latch for MOS Memories
Bus Width 2-n bits data/address (depending on number of slices used)
The 16-bit processors: origin of x86
8086
Introduced June 8, 1978
Clock rates:
o 4.77 MHz with 0.33 MIPS[2]
o 8 MHz with 0.66 MIPS
o 10 MHz with 0.75 MIPS
The memory is divided into odd and even banks. It accesses both the banks simultaneuosly in order to read 16 bit of data in one
clock cycle.
Bus Width 16 bits data, 20 bits address
Number of Transistors 29,000 at 3 µm
5
Addressable memory 1 megabyte
Up to 10X the performance of 8080 (typically lower)
Used in portable computing, and in the IBM PS/2 Model 25 and Model 30. Also used in the AT&T PC6300 / Olivetti M24, a popular
IBM PC-compatible (predating the IBM PS/2 line.)
Used segment registers to access more than 64 KB of data at once, which many programmers complained made their work
excessively difficult.
8088
Introduced June 1, 1979
Clock rates:
o 4.77 MHz with 0.33 MIPS
o 8 MHz with 0.75 MIPS [2]
Internal architecture 16 bits
External bus Width 8 bits data, 20 bits address
Number of Transistors 29,000 at 3 µm
Addressable memory 1 megabyte
Identical to 8086 except for its 8 bit external bus (hence an 8 instead of a 6 at the end)
Used in IBM PCs and PC clones
MCS-86 Family
8086-CPU
8088-CPU
8087-Math Coprocessor
8089-Programmable DMA Coprocessor
8208-Dynamic RAM Controller
8284-Clock Generator & Driver
8286-Octal Bus Transceiver
8287-Octal Bus Transceiver
8288-Bus Controller
8289-Bus Arbiter
80130-iRMX 86 Operating System Processors
80186-CPU
80188-CPU
80286-CPU
80287-Math-Coprocessor
82050-Communication Controller
82062-Winchester Disk Controller
82064-Floppy Disk Controller
82091-Advanced Integrated Peripheral
82188-Bus Controller
82288-Bus Controller
82389-Message Passing Coprocessor
82503-Dual Serial Transceiver
82510-Communication Controller
82530-Serial Communication Controller
82577-PCI LAN Controller
82586-IEEE 802.3 EtherNET LAN CoProcessor
82596-LAN-CoProcessor
82720-Graphics Display Controller
82730-Text Coprocessor
80386-CPU
80387-Math-CoProcessor
6
80186
Introduced 1982
Clock rates
o 6 MHz with > 1 MIPS
Number of Transistors 29,000 at 2 µm
Included two timers, a DMA controller, and an interrupt controller on the chip in addition to the processor (These were at fixed
addresses which differed from the IBM PC, making it impossible to build a 100% PC-compatible computer around the 80186.)
Added a few opcodes and exceptions to the 8086 design; otherwise identical instruction set to 8086 and 8088.
Used mostly in embedded applications – controllers, point-of-sale systems, terminals, and the like
Used in several non-PC-Compatible MS-DOS computers including RM Nimbus, Tandy 2000
Later renamed the iAPX 186
80188
A version of the 80186 with an 8-bit external data bus
Later renamed the iAPX 188
80286
Introduced February 1, 1982
Clock rates:
o 6 MHz with 0.9 MIPS
o 8 MHz, 10 MHz with 1.5 MIPS
o 12.5 MHz with 2.66 MIPS
o 16 MHz, 20 MHz and 25 MHz available.
Bus Width: 16 bit data, 24 bit address.
Included memory protection hardware to support multitasking operating systems with per-process address space
Number of Transistors 134,000 at 1.5 µm
Addressable memory 16 MB (16 MB)
Added protected-mode features to 8086 with essentially the same instruction set
3-6X the performance of the 8086
Widely used in IBM-PC AT and AT clones contemporary to it
32-bit processors: the non-x86 microprocessors
iAPX 432
Introduced January 1, 1981 as Intel's first 32-bit microprocessor
Multi-chip CPU; Intel's first 32-bit microprocessor
Object/capability architecture
Microcoded operating system primitives
One terabyte virtual address space
Hardware support for fault tolerance
Two-chip General Data Processor (GDP), consists of 43201 and 43202
43203 Interface Processor (IP) interfaces to I/O subsystem
43204 Bus Interface Unit (BIU) simplifies building multiprocessor systems
43205 Memory Control Unit (MCU)
Architecture and execution unit internal data paths 32 bit
Clock rates:
o 5 MHz
o 7 MHz
o 8 MHz
7
i960 aka 80960
Introduced April 5, 1988
RISC-like 32-bit architecture
Predominantly used in embedded systems
Evolved from the capability processor developed for the BiiN joint venture with Siemens
Many variants identified by two-letter suffixes.
80386SX (chronological entry)
Introduced June 16, 1988
See main entry
80376 (chronological entry)
Introduced January 16, 1989
See main entry
i860 aka 80860
Introduced February 27, 1989
RISC 32/64-bit architecture, with floating point pipeline characteristics very visible to programmer
Used in the Intel iPSC/860 Hypercube parallel supercomputer
mid-life kicker in the i870 processor (primarily a speed bump, some refinement/extension of instruction set)
Used in the Intel Delta massively parallel supercomputer prototype, emplaced at California Institute of Technology
Used in the Intel Paragon massively parallel supercomputer, emplaced at Sandia National Laboratory
XScale
Introduced August 23, 2000
32-bit RISC microprocessor based on the ARM architecture
Many variants, such as the PXA2xx applications processors, IOP3xx I/O processors and IXP2xxx and IXP4xx network processors.
32-bit processors: the 80386 range
80386DX
Introduced October 17, 1985
Clock rates:
o 16 MHz with 5 to 6 MIPS
o 20 MHz with 6 to 7 MIPS, introduced February 16, 1987
o 25 MHz with 8.5 MIPS, introduced April 4, 1988
o 33 MHz with 11.4 MIPS (9.4 SPECint92 on Compaq/i 16K L2), introduced April 10, 1989
Bus Width 32 bit data, 32 bit address
Number of Transistors 275,000 at 1 µm
Addressable memory 4 GB (4 GB)
Virtual memory 64 TB (64 TiB)
First x86 chip to handle 32-bit data sets
Reworked and expanded memory protection support including paged virtual memory and virtual-86 mode, features required at
the time by Xenix and Unix. This memory capability spurred the development and availability of OS/2 and is a fundamental
requirement for modern operating systems like Linux, Vista, and Mac OS.
8
Used in Desktop computing
80960 (i960) (chronological entry)
Introduced April 5, 1988
See main entry
80386SX
Introduced June 16, 1988
Clock rates:
o 16 MHz with 2.5 MIPS
o 20 MHz with 2.5 MIPS, introduced January 25, 1989
o 25 MHz with 2.7 MIPS, introduced January 25, 1989
o 33 MHz with 2.9 MIPS, introduced October 26, 1992
Internal architecture 32 bits
External data bus width 16 bits
External address bus width 24 bits
Number of Transistors 275,000 at 1 µm
Addressable memory 16 MB
Virtual memory 32 GB
Narrower buses enable low-cost 32-bit processing
Used in entry-level desktop and portable computing
No Math Co-Processor
No commercial Software used for protected mode or virtual storage for many years
80376
The Intel i376 is an embedded version of the i386SX.
Introduced January 16, 1989; Discontinued June 15, 2001
Variant of 386SX intended for embedded systems
No "real mode", starts up directly in "protected mode"
Replaced by much more successful 80386EX from 1994
9
80860 (i860) (chronological entry)
Introduced February 27, 1989
See main entry
80486DX (chronological entry)
Introduced April 10, 1989
See main entry
80386SL
Introduced October 15, 1990
Clock rates:
o 20 MHz with 4.21 MIPS
o 25 MHz with 5.3 MIPS, introduced September 30, 1991
Internal architecture 32 bits
External bus width 16 bits
Number of Transistors 855,000 at 1 µm
Addressable memory 4 GB
Virtual memory 1 TB
First chip specifically made for portable computers because of low power consumption of chip
Highly integrated, includes cache, bus, and memory controllers
80486SX/DX2/SL, Pentium, 80486DX4 (chronological entries)
Introduced 1991–1994
See main entries
80386EX
Introduced August 1994
Variant of 80386SX intended for embedded systems
Static core, i.e. may run as slowly (and thus, power efficiently) as desired, down to full halt
On-chip peripherals:
o Clock and power mgmt
o Timers/counters
o Watchdog timer
o Serial I/O units (sync and async) and parallel I/O
o DMA
o RAM refresh
o JTAG test logic
Significantly more successful than the 80376
Used aboard several orbiting satellites and microsatellites
Used in NASA's FlightLinux project
32-bit processors: the 80486 range
80486DX
10
Introduced April 10, 1989
Clock rates:
o 25 MHz with 20 MIPS (16.8 SPECint92, 7.40 SPECfp92)
o 33 MHz with 27 MIPS (22.4 SPECint92 on Micronics M4P 128 KB L2), introduced May 7, 1990
o 50 MHz with 41 MIPS (33.4 SPECint92, 14.5 SPECfp92 on Compaq/50L 256 KB L2), introduced June 24, 1991
Bus Width 32 bits
Number of Transistors 1.2 million at 1 µm; the 50 MHz was at 0.8 µm
Addressable memory 4 GB
Virtual memory 1 TB
Level 1 cache of 8 KB on chip
Math coprocessor on chip
50X performance of the 8088
Used in Desktop computing and servers
Family 4 model 3
80386SL (chronological entry)
Introduced October 15, 1990
See main entry
80486SX
Introduced April 22, 1991
Clock rates:
o 16 MHz with 13 MIPS
o 20 MHz with 16.5 MIPS, introduced September 16, 1991
o 25 MHz with 20 MIPS (12 SPECint92), introduced September 16, 1991
o 33 MHz with 27 MIPS (15.86 SPECint92), introduced September 21, 1992
Bus Width 32 bits
Number of Transistors 1.185 million at 1 µm and 900,000 at 0.8 µm
Addressable memory 4 GB
Virtual memory 1 TB
Identical in design to 486DX but without math coprocessor. The first version was an 80486DX with disabled mathco in the chip
and different pin configuration. If the user needed math co capabilities, he must add 487SX which was actually an 486DX with
different pin configuration to prevent the user from installing a 486DX instead of 487SX, so with this configuration 486SX+487SX
you had 2 identical CPU's with only 1 turned on
Used in low-cost entry to 486 CPU desktop computing
Upgradable with the Intel OverDrive processor
Family 4 model 2
80486DX2
Introduced March 3, 1992
Runs at twice the speed of the external bus (FSB).
Clock rates:
o 40 MHz
o 50 MHz
o 66 MHz
o 100 MHz (This was only made a short time due to high failure rates.)
11
80486SL
Introduced November 9, 1992
Clock rates:
o 20 MHz with 15.4MIPS
o 25 MHz with 19 MIPS
o 33 MHz with 25 MIPS
Bus Width 32 bits
Number of Transistors 1.4 million at 0.8 µm
Addressable memory 4 GB
Virtual memory 1 TB
Used in notebook computers
Family 4 model 3
Pentium (chronological entry)
Introduced March 22, 1993
See main entry
80486DX4
Introduced March 7, 1994
Clock rates:
o 75 MHz with 53 MIPS (41.3 SPECint92, 20.1 SPECfp92 on Micronics M4P 256 KB L2)
o 100 MHz with 70.7 MIPS (54.59 SPECint92, 26.91 SPECfp92 on Micronics M4P 256 KB L2)
Number of Transistors 1.6 million at 0.6 µm
Bus width 32 bits
Addressable memory 4 GB
Virtual memory 64 TB
Pin count 168 PGA Package, 208 sq ftP Package
Used in high performance entry-level desktops and value notebooks
Family 4 model 8
32-bit processors: P5 microarchitecture
Original Pentium
Bus width 64 bits
System bus clock rate 60 or 66 MHz
Address bus 32 bits
Addressable Memory 4 GB
Virtual Memory 64 TB
Superscalar architecture
Runs on 5 volts
Used in desktops
16 KB of L1 cache
P5 – 0.8 µm process technology
o Introduced March 22, 1993
o Number of transistors 3.1 million
o Socket 4 273 pin PGA processor package
o Package dimensions 2.16" × 2.16"
o Family 5 model 1
12
o Variants
60 MHz with 100 MIPS (70.4 SPECint92, 55.1 SPECfp92 on Xpress 256 KB L2)
66 MHz with 112 MIPS (77.9 SPECint92, 63.6 SPECfp92 on Xpress 256 KB L2)
P54 – 0.6 µm process technology
o Socket 5 296/320 pin PGA package
o Number of transistors 3.2 million
o Variants
75 MHz Introduced October 10, 1994
90, 100 MHz Introduced March 7, 1994
P54CQS – 0.35 µm process technology
o Socket 5 296/320 pin PGA package
o Number of transistors 3.2 million
o Variants
120 MHz Introduced March 27, 1995
P54CS – 0.35 µm process technology
o Number of transistors 3.3 million
o 90 mm² die size
o Family 5 model 2
o Variants
o Socket 5 296/320 pin PGA package
133 MHz Introduced June 12, 1995
150, 166 MHz Introduced January 4, 1996
o Socket 7 296/321 pin PGA package
200 MHz Introduced June 10, 1996
Pentium with MMX Technology
P55C – 0.35 µm process technology
o Introduced January 8, 1997
o Intel MMX (instruction set) support
o Socket 7 296/321 pin PGA (pin grid array) package
o 32 KB L1 cache
o Number of transistors 4.5 million
o System bus clock rate 66 MHz
o Basic P55C is family 5 model 4, mobile are family 5 model 7 and 8
o Variants
166, 200 MHz Introduced January 8, 1997
233 MHz Introduced June 2, 1997
133 MHz (Mobile)
166, 266 MHz (Mobile) Introduced January 12, 1998
200, 233 MHz (Mobile) Introduced September 8, 1997
300 MHz (Mobile) Introduced January 7, 1999
32-bit processors: P6/Pentium M microarchitecture
Pentium Pro
Introduced November 1, 1995
Precursor to Pentium II and III
Primarily used in server systems
Socket 8 processor package (387 pins) (Dual SPGA)
Number of transistors 5.5 million
Family 6 model 1
13
0.6 µm process technology
o 16 KB L1 cache
o 256 KB integrated L2 cache
o 60 MHz system bus clock rate
o Variants
150 MHz
0.35 µm process technology, or 0.35 µm CPU with 0.6 µm L2 cache
o Number of transistors 5.5 million
o 512 KB or 256 KB integrated L2 cache
o 60 or 66 MHz system bus clock rate
o Variants
166 MHz (66 MHz bus clock rate, 512 KB 0.35 µm cache) Introduced November 1, 1995
180 MHz (60 MHz bus clock rate, 256 KB 0.6 µm cache) Introduced November 1, 1995
200 MHz (66 MHz bus clock rate, 256 KB 0.6 µm cache) Introduced November 1, 1995
200 MHz (66 MHz bus clock rate, 512 KB 0.35 µm cache) Introduced November 1, 1995
200 MHz (66 MHz bus clock rate, 1 MB 0.35 µm cache) Introduced August 18, 1997
Pentium II
Introduced May 7, 1997
Pentium Pro with MMX and improved 16-bit performance
242-pin Slot 1 (SEC) processor package
Slot 1
Number of transistors 7.5 million
32 KB L1 cache
512 KB ½ bandwidth external L2 cache
The only Pentium II that did not have the L2 cache at ½ bandwidth of the core was the Pentium II 450 PE.
Klamath – 0.35 µm process technology (233, 266, 300 MHz)
o 66 MHz system bus clock rate
o Family 6 model 3
o Variants
233, 266, 300 MHz Introduced May 7, 1997
Deschutes – 0.25 µm process technology (333, 350, 400, 450 MHz)
o Introduced January 26, 1998
o 66 MHz system bus clock rate (333 MHz variant), 100 MHz system bus clock rate for all models after
o Family 6 model 5
o Variants
333 MHz Introduced January 26, 1998
350, 400 MHz Introduced April 15, 1998
450 MHz Introduced August 24, 1998
233, 266 MHz (Mobile) Introduced April 2, 1998
333 MHz Pentium II Overdrive processor for Socket 8 Introduced August 10, 1998; Engineering Sample
Photo
300 MHz (Mobile) Introduced September 9, 1998
333 MHz (Mobile)
Celeron (Pentium II-based)
Covington – 0.25 µm process technology
o Introduced April 15, 1998
o 242-pin Slot 1 SEPP (Single Edge Processor Package)
o Number of transistors 7.5 million
o 66 MHz system bus clock rate
14
o Slot 1
o 32 KB L1 cache
o No L2 cache
o Variants
266 MHz Introduced April 15, 1998
300 MHz Introduced June 9, 1998
Mendocino – 0.25 µm process technology
o Introduced August 24, 1998
o 242-pin Slot 1 SEPP (Single Edge Processor Package), Socket 370 PPGA package
o Number of transistors 19 million
o 66 MHz system bus clock rate
o Slot 1, Socket 370
o 32 KB L1 cache
o 128 KB integrated cache
o Family 6 model 6
o Variants
300, 333 MHz Introduced August 24, 1998
366, 400 MHz Introduced January 4, 1999
433 MHz Introduced March 22, 1999
466 MHz
500 MHz Introduced August 2, 1999
533 MHz Introduced January 4, 2000
266 MHz (Mobile)
300 MHz (Mobile)
333 MHz (Mobile) Introduced April 5, 1999
366 MHz (Mobile)
400 MHz (Mobile)
433 MHz (Mobile)
450 MHz (Mobile) Introduced February 14, 2000
466 MHz (Mobile)
500 MHz (Mobile) Introduced February 14, 2000
Pentium II Xeon (chronological entry)
Introduced June 29, 1998
See main entry
Pentium III
Katmai – 0.25 µm process technology
o Introduced February 26, 1999
o Improved PII, i.e. P6-based core, now including Streaming SIMD Extensions (SSE)
o Number of transistors 9.5 million
o 512 KB ½ bandwidth L2 External cache
o 242-pin Slot 1 SECC2 (Single Edge Contact cartridge 2) processor package
o System Bus clock rate 100 MHz, 133 MHz (B-models)
o Slot 1
o Family 6 model 7
o Variants
450, 500 MHz Introduced February 26, 1999
550 MHz Introduced May 17, 1999
600 MHz Introduced August 2, 1999
15
533, 600 MHz Introduced (133 MHz bus clock rate) September 27, 1999
Coppermine – 0.18 µm process technology
o Introduced October 25, 1999
o Number of transistors 28.1 million
o 256 KB Advanced Transfer L2 Cache (Integrated)
o 242-pin Slot-1 SECC2 (Single Edge Contact cartridge 2) processor package, 370-pin FC-PGA (Flip-chip pin grid array)
package
o System Bus clock rate 100 MHz (E-models), 133 MHz (EB models)
o Slot 1, Socket 370
o Family 6 model 8
o Variants
500 MHz (100 MHz bus clock rate)
533 MHz
550 MHz (100 MHz bus clock rate)
600 MHz
600 MHz (100 MHz bus clock rate)
650 MHz (100 MHz bus clock rate) Introduced October 25, 1999
667 MHz Introduced October 25, 1999
700 MHz (100 MHz bus clock rate) Introduced October 25, 1999
733 MHz Introduced October 25, 1999
750, 800 MHz (100 MHz bus clock rate) Introduced December 20, 1999
850 MHz (100 MHz bus clock rate) Introduced March 20, 2000
866 MHz Introduced March 20, 2000
933 MHz Introduced May 24, 2000
1000 MHz Introduced March 8, 2000 (Not widely available at time of release)
1100 MHz
1133 MHz (first version recalled, later re-released)
400, 450, 500 MHz (Mobile) Introduced October 25, 1999
600, 650 MHz (Mobile) Introduced January 18, 2000
700 MHz (Mobile) Introduced April 24, 2000
750 MHz (Mobile) Introduced June 19, 2000
800, 850 MHz (Mobile) Introduced September 25, 2000
900, 1000 MHz (Mobile) Introduced March 19, 2001
Tualatin – 0.13 µm process technology
o Introduced July 2001
o Number of transistors 28.1 million
o 32 KB L1 cache
o 256 KB or 512 KB Advanced Transfer L2 cache (Integrated)
o 370-pin FC-PGA2 (Flip-chip pin grid array) package
o 133 MHz system bus clock rate
o Socket 370
o Family 6 model 11
o Variants
1133 MHz (256 KB L2)
1133 MHz (512 KB L2)
1200 MHz
1266 MHz (512 KB L2)
1333 MHz
1400 MHz (512 KB L2)
Pentium II and III Xeon
PII Xeon
16
o Variants
400 MHz Introduced June 29, 1998
450 MHz (512 KB L2 Cache) Introduced October 6, 1998
450 MHz (1 MB and 2 MB L2 Cache) Introduced January 5, 1999
PIII Xeon
o Introduced October 25, 1999
o Number of transistors: 9.5 million at 0.25 µm or 28 million at 0.18 µm
o L2 cache is 256 KB, 1 MB, or 2 MB Advanced Transfer Cache (Integrated)
o Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330
o System Bus clock rate 133 MHz (256 KB L2 cache) or 100 MHz (1 – 2 MB L2 cache)
o System Bus Width 64 bit
o Addressable memory 64 GB
o Used in two-way servers and workstations (256 KB L2) or 4- and 8-way servers (1 – 2 MB L2)
o Family 6 model 10
o Variants
500 MHz (0.25 µm process) Introduced March 17, 1999
550 MHz (0.25 µm process) Introduced August 23, 1999
600 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
667 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
733 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
800 MHz (0.18 µm process, 256 KB L2 cache) Introduced January 12, 2000
866 MHz (0.18 µm process, 256 KB L2 cache) Introduced April 10, 2000
933 MHz (0.18 µm process, 256 KB L2 cache)
1000 MHz (0.18 µm process, 256 KB L2 cache) Introduced August 22, 2000
700 MHz (0.18 µm process, 1 – 2 MB L2 cache) Introduced May 22, 2000
Celeron (Pentium III Coppermine-based)
Coppermine-128, 0.18 µm process technology
o Introduced March, 2000
o Streaming SIMD Extensions (SSE)
o Socket 370, FC-PGA processor package
o Number of transistors 28.1 million
o 66 MHz system bus clock rate, 100 MHz system bus clock rate from January 3, 2001
o 32 kB L1 cache
o 128 kB Advanced Transfer L2 cache
o Family 6 model 8
o Variants
533 MHz
566 MHz
600 MHz
633, 667, 700 MHz Introduced June 26, 2000
733, 766 MHz Introduced November 13, 2000
800 MHz Introduced January 3, 2001
850 MHz Introduced April 9, 2001
900 MHz Introduced July 2, 2001
950, 1000, 1100 MHz Introduced August 31, 2001
550 MHz (Mobile)
600, 650 MHz (Mobile) Introduced June 19, 2000
700 MHz (Mobile) Introduced September 25, 2000
750 MHz (Mobile) Introduced March 19, 2001
800 MHz (Mobile)
850 MHz (Mobile) Introduced July 2, 2001
17
600 MHz (LV Mobile)
500 MHz (ULV Mobile) Introduced January 30, 2001
600 MHz (ULV Mobile)
XScale (chronological entry)
Introduced August 23, 2000
See main entry
Pentium 4 (not 4EE, 4E, 4F), Itanium, P4-based Xeon, Itanium 2 (chronological entries)
Introduced April 2000 – July 2002
See main entries
Celeron (Pentium III Tualatin-based)
Tualatin Celeron – 0.13 µm process technology
o 32 KB L1 cache
o 256 KB Advanced Transfer L2 cache
o 100 MHz system bus clock rate
o Socket 370
o Family 6 model 11
o Variants
1.0 GHz
1.1 GHz
1.2 GHz
1.3 GHz
1.4 GHz
Pentium M
Banias 0.13 µm process technology
o Introduced March 2003
o 64 KB L1 cache
o 1 MB L2 cache (integrated)
o Based on Pentium III core, with SSE2 SIMD instructions and deeper pipeline
o Number of transistors 77 million
o Micro-FCPGA, Micro-FCBGA processor package
o Heart of the Intel mobile Centrino system
o 400 MHz Netburst-style system bus
o Family 6 model 9
o Variants
900 MHz (Ultra low voltage)
1.0 GHz (Ultra low voltage)
1.1 GHz (Low voltage)
1.2 GHz (Low voltage)
1.3 GHz
1.4 GHz
1.5 GHz
1.6 GHz
1.7 GHz
18
Dothan 0.09 µm (90 nm) process technology
o Introduced May 2004
o 2 MB L2 cache
o 140 million transistors
o Revised data prefetch unit
o 400 MHz Netburst-style system bus
o 21W TDP
o Family 6 model 13
o Variants
1.00 GHz (Pentium M 723) (Ultra low voltage, 5W TDP)
1.10 GHz (Pentium M 733) (Ultra low voltage, 5W TDP)
1.20 GHz (Pentium M 753) (Ultra low voltage, 5W TDP)
1.30 GHz (Pentium M 718) (Low voltage, 10W TDP)
1.40 GHz (Pentium M 738) (Low voltage, 10W TDP)
1.50 GHz (Pentium M 758) (Low voltage, 10W TDP)
1.60 GHz (Pentium M 778) (Low voltage, 10W TDP)
1.40 GHz (Pentium M 710)
1.50 GHz (Pentium M 715)
1.60 GHz (Pentium M 725)
1.70 GHz (Pentium M 735)
1.80 GHz (Pentium M 745)
2.00 GHz (Pentium M 755)
2.10 GHz (Pentium M 765)
Dothan 533 0.09 µm (90 nm) process technology
o Introduced Q1 2005
o Same as Dothan except with a 533 MHz NetBurst-style system bus and 27W TDP
o Variants
1.60 GHz (Pentium M 730)
1.73 GHz (Pentium M 740)
1.86 GHz (Pentium M 750)
2.00 GHz (Pentium M 760)
2.13 GHz (Pentium M 770)
2.26 GHz (Pentium M 780)
Stealey 0.09 µm (90 nm) process technology
o Introduced Q2 2007
o 512 KB L2, 3W TDP
o Variants
600 MHz (A100)
800 MHz (A110)
Celeron M
Banias-512 0.13 µm process technology
o Introduced March 2003
o 64 KB L1 cache
o 512 KB L2 cache (integrated)
o SSE2 SIMD instructions
o No SpeedStep technology, is not part of the 'Centrino' package
o Family 6 model 9
o Variants
310 – 1.20 GHz
320 – 1.30 GHz
330 – 1.40 GHz
19
340 – 1.50 GHz
Dothan-1024 90 nm process technology
o 64 KB L1 cache
o 1 MB L2 cache (integrated)
o SSE2 SIMD instructions
o No SpeedStep technology, is not part of the 'Centrino' package
o Variants
350 – 1.30 GHz
350J – 1.30 GHz, with Execute Disable bit
360 – 1.40 GHz
360J – 1.40 GHz, with Execute Disable bit
370 – 1.50 GHz, with Execute Disable bit
Family 6, Model 13, Stepping 8[3]
380 – 1.60 GHz, with Execute Disable bit
390 – 1.70 GHz, with Execute Disable bit
Yonah-1024 65 nm process technology
o 64 KB L1 cache
o 1 MB L2 cache (integrated)
o SSE3 SIMD instructions, 533 MHz front-side bus, execute-disable bit
o No SpeedStep technology, is not part of the 'Centrino' package
o Variants
410 – 1.46 GHz
420 – 1.60 GHz,
423 – 1.06 GHz (ultra low voltage)
430 – 1.73 GHz
440 – 1.86 GHz
443 – 1.20 GHz (ultra low voltage)
450 – 2.00 GHz
Intel Core
Yonah 0.065 µm (65 nm) process technology
o Introduced January 2006
o 533/667 MHz front side bus
o 2 MB (Shared on Duo) L2 cache
o SSE3 SIMD instructions
o 31W TDP (T versions)
o Family 6, Model 14
o Variants:
Intel Core Duo T2700 2.33 GHz
Intel Core Duo T2600 2.16 GHz
Intel Core Duo T2500 2 GHz
Intel Core Duo T2450 2 GHz
Intel Core Duo T2400 1.83 GHz
Intel Core Duo T2300 1.66 GHz
Intel Core Duo T2050 1.6 GHz
Intel Core Duo T2300e 1.66 GHz
Intel Core Duo T2080 1.73 GHz
Intel Core Duo L2500 1.83 GHz (Low voltage, 15W TDP)
Intel Core Duo L2400 1.66 GHz (Low voltage, 15W TDP)
Intel Core Duo L2300 1.5 GHz (Low voltage, 15W TDP)
Intel Core Duo U2500 1.2 GHz (Ultra low voltage, 9W TDP)
Intel Core Solo T1350 1.86 GHz (533 FSB)
20
Intel Core Solo T1300 1.66 GHz
Intel Core Solo T1200 1.5 GHz [4]
Dual-Core Xeon LV
Sossaman 0.065 µm (65 nm) process technology
o Introduced March 2006
o Based on Yonah core, with SSE3 SIMD instructions
o 667 MHz frontside bus
o 2 MB Shared L2 cache
o Variants
2.0 GHz
32-bit processors: NetBurst microarchitecture
Pentium 4
0.18 µm process technology (1.40 and 1.50 GHz)
o Introduced November 20, 2000
o L2 cache was 256 KB Advanced Transfer Cache (Integrated)
o Processor Package Style was PGA423, PGA478
o System Bus clock rate 400 MHz
o SSE2 SIMD Extensions
o Number of Transistors 42 million
o Used in desktops and entry-level workstations
0.18 µm process technology (1.7 GHz)
o Introduced April 23, 2001
o See the 1.4 and 1.5 chips for details
0.18 µm process technology (1.6 and 1.8 GHz)
o Introduced July 2, 2001
o See 1.4 and 1.5 chips for details
o Core Voltage is 1.15 volts in Maximum Performance Mode; 1.05 volts in Battery Optimized Mode
o Power <1 watt in Battery Optimized Mode
o Used in full-size and then light mobile PCs
0.18 µm process technology Willamette (1.9 and 2.0 GHz)
o Introduced August 27, 2001
o See 1.4 and 1.5 chips for details
Family 15 model 1
Pentium 4 (2 GHz, 2.20 GHz)
o Introduced January 7, 2002
Pentium 4 (2.4 GHz)
o Introduced April 2, 2002
0.13 µm process technology Northwood A (1.7, 1.8, 1.9, 2, 2.2, 2.4, 2.5, 2.6, 2.8(OEM),3.0(OEM) GHz)
o Improved branch prediction and other microcodes tweaks
o 512 KB integrated L2 cache
o Number of transistors 55 million
o 400 MHz system bus.
Family 15 model 2
0.13 µm process technology Northwood B (2.26, 2.4, 2.53, 2.66, 2.8, 3.06 GHz)
o 533 MHz system bus. (3.06 includes Intel's hyper threading technology).
0.13 µm process technology Northwood C (2.4, 2.6, 2.8, 3.0, 3.2, 3.4 GHz)
o 800 MHz system bus (all versions include Hyper Threading)
o 6500 to 10000 MIPS
21
Itanium (chronological entry)
Introduced 2001
See main entry
Xeon
Official designation now Xeon, i.e. not "Pentium 4 Xeon"
Xeon 1.4, 1.5, 1.7 GHz
o Introduced May 21, 2001
o L2 cache was 256 KB Advanced Transfer Cache (Integrated)
o Processor Package Style was Organic Land Grid Array 603 (OLGA 603)
o System Bus clock rate 400 MHz
o SSE2 SIMD Extensions
o Used in high-performance and mid-range dual processor enabled workstations
Xeon 2.0 GHz and up to 3.6 GHz
o Introduced September 25, 2001
Itanium 2 (chronological entry)
Introduced July 2002
See main entry
Mobile Pentium 4-M
0.13 µm process technology
55 million transistors
cache L2 512 KB
BUS a 400 MHz
Supports up to 1 GB of DDR 266 MHz Memory
Supports ACPI 2.0 and APM 1.2 System Power Management
1.3 V – 1.2 V (SpeedStep)
Power: 1.2 GHz 20.8 W, 1.6 GHz 30 W, 2.6 GHz 35 W
Sleep Power 5 W (1.2 V)
Deeper Sleep Power = 2.9 W (1.0 V)
o 1.40 GHz – 23 April 2002
o 1.50 GHz – 23 April 2002
o 1.60 GHz – 4 March 2002
o 1.70 GHz – 4 March 2002
o 1.80 GHz – 23 April 2002
o 1.90 GHz – 24 June 2002
o 2.00 GHz – 24 June 2002
o 2.20 GHz – 16 September 2002
o 2.40 GHz – 14 January 2003
o 2.50 GHz – 16 April 2003
o 2.60 GHz – 11 June 2003
Pentium 4 EE
22
Introduced September 2003
EE = "Extreme Edition"
Built from the Xeon's "Gallatin" core, but with 2 MB cache-
Pentium 4E
Introduced February 2004
built on 0.09 µm (90 nm) process technology Prescott (2.4A, 2.8, 2.8A, 3.0, 3.2, 3.4, 3.6, 3.8) 1 MB L2 cache
533 MHz system bus (2.4A and 2.8A only)
Number of Transistors 125 million on 1 MB Models
Number of Transistors 169 million on 2 MB Models
800 MHz system bus (all other models)
Hyper-Threading support is only available on CPUs using the 800 MHz system bus.
The processor's integer instruction pipeline has been increased from 20 stages to 31 stages, which theoretically allows for even
greater bandwidth.
7500 to 11000 MIPS
LGA 775 versions are in the 5xx series (32-bit) and 5x1 series (with Intel 64)
The 6xx series has 2 MB L2 cache and Intel 64
Pentium 4F
Introduced Spring 2004
same core as 4E, "Prescott"
3.2–3.6 GHz
starting with the D0 stepping of this processor, Intel 64 64-bit extensions has also been incorporated
64-bit processors: IA-64
New instruction set, not at all related to x86.
Before the feature was eliminated (Montecito, July 2006) IA-64 processors supported 32-bit x86 in hardware, but slowly (see its
2001 market reception and 2006 architectural changes).[dubious – discuss]
Itanium
Code name Merced
Family 0x07
Released May 29, 2001
733 MHz and 800 MHz
2MB cache
all recalled and replaced by Itanium-II
Itanium 2
Family 0x1F
Released July 2002
900 MHz – 1.6 GHz
McKinley 900 MHz 1.5MB cache, Model 0x0
McKinley 1 GHz, 3MB cache, Model 0x0
Deerfield 1 GHz, 1.5MB cache, Model 0x1
Madison 1.3 GHz, 3MB cache, Model 0x1
Madison 1.4 GHz, 4MB cache, Model 0x1
Madison 1.5 GHz, 6MB cache, Model 0x1
Madison 1.67 GHz, 9MB cache, Model 0x1
23
Hondo 1.4 GHz, 4MB cache, dual core MCM, Model 0x1
64-bit processors: Intel 64 – NetBurst microarchitecture
Intel Extended Memory 64 Technology
Mostly compatible with AMD's AMD64 architecture
Introduced Spring 2004, with the Pentium 4F (D0 and later P4 steppings)
Pentium 4F
Prescott-2M built on 0.09 µm (90 nm) process technology
2.8–3.8 GHz (model numbers 6x0)
Introduced February 20, 2005
Same features as Prescott with the addition of:-
o 2 MB cache
o Intel 64bit
o Enhanced Intel SpeedStep Technology (EIST)
Cedar Mill built on 0.065 µm (65 nm) process technology
3.0–3.6 (model numbers 6x1)
Introduced January 16, 2006
die shrink of Prescott-2M
Same features as Prescott-2M
Family 15 Model 4
Pentium D
Main article: List of Intel Pentium D microprocessors
Dual-core microprocessor
No Hyper-Threading
800(4×200) MHz front side bus
LGA 775 (Socket T)
Smithfield – 90 nm process technology (2.66–3.2 GHz)
o Introduced May 26, 2005
o 2.66–3.2 GHz (model numbers 805–840)
o Number of Transistors 230 million
o 1 MB × 2 (non-shared, 2 MB total) L2 cache
o Cache coherency between cores requires communication over the FSB
o Performance increase of 60% over similarly clocked Prescott
o 2.66 GHz (533 MHz FSB) Pentium D 805 introduced December 2005
o Contains 2x Prescott dies in one package
o Family 15 Model 4
Presler – 65 nm process technology (2.8–3.6 GHz)
o Introduced January 16, 2006
o 2.8–3.6 GHz (model numbers 915–960)
o Number of Transistors 376 million
o 2 MB × 2 (non-shared, 4 MB total) L2 cache
o Contains 2x Cedar Mill dies in one package
Pentium Extreme Edition
24
Dual-core microprocessor
Enabled Hyper-Threading
800(4×200) MHz front side bus
Smithfield – 90 nm process technology (3.2 GHz)
o Variants
Pentium 840 EE – 3.20 GHz (2 × 1 MB L2)
Presler – 65 nm process technology (3.46, 3.73)
o 2 MB × 2 (non-shared, 4 MB total) L2 cache
o Variants
Pentium 955 EE – 3.46 GHz, 1066 MHz front side bus
Pentium 965 EE – 3.73 GHz, 1066 MHz front side bus
Xeon
Nocona
o Introduced 2004
Irwindale
o Introduced 2004
Cranford
o Introduced April 2005
o MP version of Nocona
Potomac
o Introduced April 2005
o Cranford with 8 MB of L3 cache
Paxville DP (2.8 GHz)
o Introduced October 10, 2005
o Dual-core version of Irwindale, with 4 MB of L2 Cache (2 MB per core)
o 2.8 GHz
o 800 MT/s front side bus
Paxville MP – 90 nm process (2.67 – 3.0 GHz)
o Introduced November 1, 2005
o Dual-Core Xeon 7000 series
o MP-capable version of Paxville DP
o 2 MB of L2 Cache (1 MB per core) or 4 MB of L2 (2 MB per core)
o 667 MT/s FSB or 800 MT/s FSB
Dempsey – 65 nm process (2.67 – 3.73 GHz)
o Introduced May 23, 2006
o Dual-Core Xeon 5000 series
o MP version of Presler
o 667 MT/s or 1066 MT/s FSB
o 4 MB of L2 Cache (2 MB per core)
o LGA 771 (Socket J).
Tulsa – 65 nm process (2.5 – 3.4 GHz)
25
o Introduced August 29, 2006
o Dual-Core Xeon 7100-series
o Improved version of Paxville MP
o 667 MT/s or 800 MT/s FSB
64-bit processors: Intel 64 – Core microarchitecture
Xeon
Woodcrest – 65 nm process technology
o Server and Workstation CPU (SMP support for dual CPU system)
o Introduced June 26, 2006
o Dual-Core
o Intel VT-x, multiple OS support
o EIST (Enhanced Intel SpeedStep Technology) in 5140, 5148LV, 5150, 5160
o Execute Disable Bit
o TXT, enhanced security hardware extensions
o SSSE3 SIMD instructions
o iAMT2 (Intel Active Management Technology), remotely manage computers
o Variants
Xeon 5160 – 3.00 GHz (4 MB L2, 1333 MHz FSB, 80 W)
Xeon 5150 – 2.66 GHz (4 MB L2, 1333 MHz FSB, 65 W)
Xeon 5140 – 2.33 GHz (4 MB L2, 1333 MHz FSB, 65 W)
Xeon 5130 – 2.00 GHz (4 MB L2, 1333 MHz FSB, 65 W)
Xeon 5120 – 1.86 GHz (4 MB L2, 1066 MHz FSB, 65 W)
Xeon 5110 – 1.60 GHz (4 MB L2, 1066 MHz FSB, 65 W)
Xeon 5148LV – 2.33 GHz (4 MB L2, 1333 MHz FSB, 40 W) – Low Voltage Edition
Clovertown – 65 nm process technology
o Server and Workstation CPU (SMP support for dual CPU system)
o Introduced December 13, 2006
o Quad Core
o Intel VT-x, multiple OS support
o EIST (Enhanced Intel SpeedStep Technology) in E5365, L5335
o Execute Disable Bit
o TXT, enhanced security hardware extensions
o SSSE3 SIMD instructions
o iAMT2 (Intel Active Management Technology), remotely manage computers
o Variants
Xeon X5355 – 2.66 GHz (2×4 MB L2, 1333 MHz FSB, 105 W)
Xeon E5345 – 2.33 GHz (2×4 MB L2, 1333 MHz FSB, 80 W)
Xeon E5335 – 2.00 GHz (2×4 MB L2, 1333 MHz FSB, 80 W)
Xeon E5320 – 1.86 GHz (2×4 MB L2, 1066 MHz FSB, 65 W)
Xeon E5310 – 1.60 GHz (2×4 MB L2, 1066 MHz FSB, 65 W)
Xeon L5320 – 1.86 GHz (2×4 MB L2, 1066 MHz FSB, 50 W)-- Low Voltage Edition
Intel Core 2
Conroe – 65 nm process technology
o Desktop CPU (SMP support restricted to 2 CPUs)
o Two cores on one die
o Introduced July 27, 2006
o SSSE3 SIMD instructions
26
o Number of Transistors: 291 Million
o 64 KB of L1 cache per core (32+32 KB 8-way)
o Intel VT-x, multiple OS support
o TXT, enhanced security hardware extensions
o Execute Disable Bit
o EIST (Enhanced Intel SpeedStep Technology)
o iAMT2 (Intel Active Management Technology), remotely manage computers
o LGA 775
o Variants
Core 2 Duo E6850 – 3.00 GHz (4 MB L2, 1333 MHz FSB)
Core 2 Duo X6800 – 2.93 GHz (4 MB L2, 1066 MHz FSB)
Core 2 Duo E6750 – 2.67 GHz (4 MB L2, 1333 MHz FSB)
Core 2 Duo E6700 – 2.67 GHz (4 MB L2, 1066 MHz FSB)
Core 2 Duo E6600 – 2.40 GHz (4 MB L2, 1066 MHz FSB)
Core 2 Duo E6550 – 2.33 GHz (4 MB L2, 1333 MHz FSB)
Core 2 Duo E6420 – 2.13 GHz (4 MB L2, 1066 MHz FSB)
Core 2 Duo E6400 – 2.13 GHz (2 MB L2, 1066 MHz FSB)
Core 2 Duo E6320 – 1.86 GHz (4 MB L2, 1066 MHz FSB) Family 6, Model 15, Stepping 6
Core 2 Duo E6300 – 1.86 GHz (2 MB L2, 1066 MHz FSB)
Conroe XE – 65 nm process technology
o Desktop Extreme Edition CPU (SMP support restricted to 2 CPUs)
o Introduced July 27, 2006
o same features as Conroe
o LGA 775
o Variants
Core 2 Extreme X6800 – 2.93 GHz (4 MB L2, 1066 MHz FSB)
Allendale – 65 nm process technology
o Desktop CPU (SMP support restricted to 2 CPUs)
o Two CPUs on one die
o Introduced January 21, 2007
o SSSE3 SIMD instructions
o Number of Transistors 167 Million
o TXT, enhanced security hardware extensions
o Execute Disable Bit
o EIST (Enhanced Intel SpeedStep Technology)
o iAMT2 (Intel Active Management Technology), remotely manage computers
o LGA 775
o Variants
Core 2 Duo E4700 – 2.60 GHz (2 MB L2, 800 MHz FSB)
Core 2 Duo E4600 – 2.40 GHz (2 MB L2, 800 MHz FSB)
Core 2 Duo E4500 – 2.20 GHz (2 MB L2, 800 MHz FSB)
Core 2 Duo E4400 – 2.00 GHz (2 MB L2, 800 MHz FSB)
Core 2 Duo E4300 – 1.80 GHz (2 MB L2, 800 MHz FSB) Family 6, Model 15, Stepping 2
Merom – 65 nm process technology
o Mobile CPU (SMP support restricted to 2 CPUs)
o Introduced July 27, 2006
o Family 6, Model 15
o same features as Conroe
o Socket M / Socket P
o Variants
27
Core 2 Duo T7800 – 2.60 GHz (4 MB L2, 800 MHz FSB) (Santa Rosa platform)
Core 2 Duo T7700 – 2.40 GHz (4 MB L2, 800 MHz FSB)
Core 2 Duo T7600 – 2.33 GHz (4 MB L2, 667 MHz FSB)
Core 2 Duo T7500 – 2.20 GHz (4 MB L2, 800 MHz FSB)
Core 2 Duo T7400 – 2.16 GHz (4 MB L2, 667 MHz FSB)
Core 2 Duo T7300 – 2.00 GHz (4 MB L2, 800 MHz FSB)
Core 2 Duo T7250 – 2.00 GHz (2 MB L2, 800 MHz FSB)
Core 2 Duo T7200 – 2.00 GHz (4 MB L2, 667 MHz FSB)
Core 2 Duo T7100 – 1.80 GHz (2 MB L2, 800 MHz FSB)
Core 2 Duo T5600 – 1.83 GHz (2 MB L2, 667 MHz FSB) Family 6, Model 15, Stepping 6
Core 2 Duo T5550 – 1.83 GHz (2 MB L2, 667 MHz FSB, no VT)
Core 2 Duo T5500 – 1.66 GHz (2 MB L2, 667 MHz FSB, no VT)
Core 2 Duo T5470 – 1.60 GHz (2 MB L2, 800 MHz FSB, no VT)
Core 2 Duo T5450 – 1.66 GHz (2 MB L2, 667 MHz FSB, no VT)
Core 2 Duo T5300 – 1.73 GHz (2 MB L2, 533 MHz FSB, no VT)
Core 2 Duo T5270 – 1.40 GHz (2 MB L2, 800 MHz FSB, no VT)
Core 2 Duo T5250 – 1.50 GHz (2 MB L2, 667 MHz FSB, no VT)
Core 2 Duo T5200 – 1.60 GHz (2 MB L2, 533 MHz FSB, no VT)
Core 2 Duo L7500 – 1.60 GHz (4 MB L2, 800 MHz FSB) (Low Voltage)
Core 2 Duo L7400 – 1.50 GHz (4 MB L2, 667 MHz FSB) (Low Voltage)
Core 2 Duo L7300 – 1.40 GHz (4 MB L2, 800 MHz FSB) (Low Voltage)
Core 2 Duo L7200 – 1.33 GHz (4 MB L2, 667 MHz FSB) (Low Voltage)
Core 2 Duo U7700 – 1.33 GHz (2 MB L2, 533 MHz FSB) (Ultra Low Voltage)
Core 2 Duo U7600 – 1.20 GHz (2 MB L2, 533 MHz FSB) (Ultra Low Voltage)
Core 2 Duo U7500 – 1.06 GHz (2 MB L2, 533 MHz FSB) (Ultra Low Voltage)
Kentsfield – 65 nm process technology
o Two dual-core cpu dies in one package.
o Desktop CPU Quad Core (SMP support restricted to 4 CPUs)
o Introduced December 13, 2006
o same features as Conroe but with 4 CPU Cores
o Number of Transistors 586 Million
o LGA 775
o Family 6, Model 15, Stepping 11
o Variants
Core 2 Extreme QX6850 – 3 GHz (2×4 MB L2 Cache, 1333 MHz FSB)
Core 2 Extreme QX6800 – 2.93 GHz (2×4 MB L2 Cache, 1066 MHz FSB) (April 9, 2007)
Core 2 Extreme QX6700 – 2.66 GHz (2×4 MB L2 Cache, 1066 MHz FSB) (November 14, 2006)
Core 2 Quad Q6700 – 2.66 GHz (2×4 MB L2 Cache, 1066 MHz FSB) (July 22, 2007)
Core 2 Quad Q6600 – 2.40 GHz (2×4 MB L2 Cache, 1066 MHz FSB) (January 7, 2007)
Wolfdale – 45 nm process technology
o Die shrink of Conroe
o Same features as Conroe with the addition of:-
50% more cache, 6 MB as opposed to 4 MB
Intel Trusted Execution Technology
SSE4 SIMD instructions
o Number of Transistors 410 Million
o Variants
Core 2 Duo E8600 – 3.33 GHz (6 MB L2, 1333 MHz FSB)
Core 2 Duo E8500 – 3.16 GHz (6 MB L2, 1333 MHz FSB)
Core 2 Duo E8400 – 3.00 GHz (6 MB L2, 1333 MHz FSB)
Core 2 Duo E8300 – 2.83 GHz (6 MB L2, 1333 MHz FSB)
28
Core 2 Duo E8200 – 2.66 GHz (6 MB L2, 1333 MHz FSB)
Core 2 Duo E8190 – 2.66 GHz (6 MB L2, 1333 MHz FSB, no TXT, no VT)
Wolfdale-3M – 45 nm process technology
o Intel Trusted Execution Technology
o Variants
Core 2 Duo E7600 – 3.06 GHz (3 MB L2, 1066 MHz FSB)
Core 2 Duo E7500 – 2.93 GHz (3 MB L2, 1066 MHz FSB)
Core 2 Duo E7400 – 2.80 GHz (3 MB L2, 1066 MHz FSB)
Core 2 Duo E7300 – 2.66 GHz (3 MB L2, 1066 MHz FSB)
Core 2 Duo E7200 – 2.53 GHz (3 MB L2, 1066 MHz FSB)
Yorkfield – 45 nm process technology
o Quad core CPU
o Die shrink of Kentsfield
o Contains 2x Wolfdale dual core dies in one package
o Same features as Wolfdale
o Number of Transistors 820 Million
o Variants
Core 2 Extreme QX9770 – 3.20 GHz (2×6 MB L2, 1600 MHz FSB)
Core 2 Extreme QX9650 – 3.00 GHz (2×6 MB L2, 1333 MHz FSB)
Core 2 Quad Q9650 – 3 GHz (2×6 MB L2, 1333 MHz FSB)
Core 2 Quad Q9550 – 2.83 GHz (2×6 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q9550s – 2.83 GHz (2×6 MB L2, 1333 MHz FSB, 65W TDP)
Core 2 Quad Q9450 – 2.66 GHz (2×6 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q9505 – 2.83 GHz (2×3 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q9505s – 2.83 GHz (2×3 MB L2, 1333 MHz FSB, 65W TDP)
Core 2 Quad Q9500 – 2.83 GHz (2×3 MB L2, 1333 MHz FSB, 95W TDP, no TXT)
Core 2 Quad Q9400 – 2.66 GHz (2×3 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q9400s – 2.66 GHz (2×3 MB L2, 1333 MHz FSB, 65W TDP)
Core 2 Quad Q9300 – 2.50 GHz (2×3 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q8400 – 2.66 GHz (2×2 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q8400s – 2.66 GHz (2×2 MB L2, 1333 MHz FSB, 65W TDP)
Core 2 Quad Q8300 – 2.50 GHz (2×2 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q8300s – 2.50 GHz (2×2 MB L2, 1333 MHz FSB, 65W TDP)
Core 2 Quad Q8200 – 2.33 GHz (2×2 MB L2, 1333 MHz FSB, 95W TDP)
Core 2 Quad Q8200s – 2.33 GHz (2×2 MB L2, 1333 MHz FSB, 65W TDP)
Core 2 Quad Q7600 – 2.70 GHz (2×1 MB L2, 800 MHz FSB, no SSE4) (no Q7600 at
http://ark.intel.com/ProductCollection.aspx?familyID=28398)
Intel Core2 Quad Mobile Processor Family – 45 nm process technology
o Quad core CPU
o Variants
Core 2 Quad Q9100 – 2.26 GHz (2×6 MB L2, 1066 MHz FSB, 45W TDP)
Core 2 Quad Q9000 – 2.00 GHz (2×3 MB L2, 1066 MHz FSB, 45W TDP)
Pentium Dual Core
Allendale – 65 nm process technology
o Desktop CPU (SMP support restricted to 2 CPUs)
o Two cores on one die
o Introduced January 21, 2007
o SSSE3 SIMD instructions
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o Number of Transistors 167 Million
o TXT, enhanced security hardware extensions
o Execute Disable Bit
o EIST (Enhanced Intel SpeedStep Technology)
o Variants
Intel Pentium E2220 – 2.40 GHz (1 MB L2, 800 MHz FSB)
Intel Pentium E2200 – 2.20 GHz (1 MB L2, 800 MHz FSB)
Intel Pentium E2180 – 2.00 GHz (1 MB L2, 800 MHz FSB)
Intel Pentium E2160 – 1.80 GHz (1 MB L2, 800 MHz FSB)
Intel Pentium E2140 – 1.60 GHz (1 MB L2, 800 MHz FSB)
Wolfdale-3M 45 nm process technology
o Intel Pentium E6800 – 3.33 GHz (2 MB L2,1066 MHz FSB)
o Intel Pentium E6700 – 3.20 GHz (2 MB L2,1066 MHz FSB)
o Intel Pentium E6600 – 3.06 GHz (2 MB L2,1066 MHz FSB)
o Intel Pentium E6500 – 2.93 GHz (2 MB L2,1066 MHz FSB)
o Intel Pentium E6300 – 2.80 GHz (2 MB L2,1066 MHz FSB)
o Intel Pentium E5700 – 3.00 GHz (2 MB L2, 800 MHz FSB)
o Intel Pentium E5500 – 2.80 GHz (2 MB L2, 800 MHz FSB)
o Intel Pentium E5400 – 2.70 GHz (2 MB L2, 800 MHz FSB)
o Intel Pentium E5300 – 2.60 GHz (2 MB L2, 800 MHz FSB)
o Intel Pentium E5200 – 2.50 GHz (2 MB L2, 800 MHz FSB)
o Intel Pentium E2210 – 2.20 GHz (1 MB L2, 800 MHz FSB)
Celeron
Allendale – 65 nm process technology
o Variants
Intel Celeron E1600 – 2.40 GHz (512 KB L2, 800 MHz FSB)
Intel Celeron E1500 – 2.20 GHz (512 KB L2, 800 MHz FSB)
Intel Celeron E1400 – 2.00 GHz (512 KB L2, 800 MHz FSB)
Intel Celeron E1300 – 1.80 GHz (512 KB L2, 800 MHz FSB) (Exist?)
Intel Celeron E1200 – 1.60 GHz (512 KB L2, 800 MHz FSB)
Wolfdale-3M – 45 nm process technology
o Variants
Intel Celeron E3500 – 2.70 GHz (1 MB L2, 800 MHz FSB)
Intel Celeron E3400 – 2.60 GHz (1 MB L2, 800 MHz FSB)
Intel Celeron E3300 – 2.50 GHz (1 MB L2, 800 MHz FSB)
Intel Celeron E3200 – 2.40 GHz (1 MB L2, 800 MHz FSB)
Conroe-L – 65 nm process technology
o Variants
Intel Celeron 450 – 2.20 GHz (512 KB L2, 800 MHz FSB)
Intel Celeron 440 – 2.00 GHz (512 KB L2, 800 MHz FSB)
Intel Celeron 430 – 1.80 GHz (512 KB L2, 800 MHz FSB)
Intel Celeron 420 – 1.60 GHz (512 KB L2, 800 MHz FSB)
Intel Celeron 220 – 1.20 GHz (512 KB L2, 533 MHz FSB)
Conroe-CL – 65 nm process technology
o LGA 771 package
o Variants
Intel Celeron 445 – 1.87 GHz (512 KB L2, 1066 MHz FSB)
Celeron M
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Merom-L 65 nm process technology
o 64 KB L1 cache
o 1 MB L2 cache (integrated)
o SSE3 SIMD instructions, 533 MHz front-side bus, execute-disable bit, 64-bit
o No SpeedStep technology, is not part of the 'Centrino' package
o Variants
520 – 1.60 GHz
530 – 1.73 GHz
540 – 1.86 GHz
550 – 2.00 GHz
560 - 2.13 GHz
32-bit processors: Intel 32 – Intel Atom
TODO: http://ark.intel.com/ProductCollection.aspx?familyId=29035
64-bit processors: Intel 64 – Nehalem microarchitecture
Intel Pentium
Clarkdale – 32 nm process technology
o 2 physical cores/2 threads
o 3 MB L3 cache
o Introduced January 2010
o Socket 1156 LGA
o 2-channels DDR3
o Integrated HD GPU
o Variants
G6950 - 2.8 GHz (No HyperThreading)[5]
G6960 - 2.933 GHz (No HyperThreading)
Core i3
Clarkdale – 32 nm process technology
o 2 physical cores/4 threads
o 64 Kb L1 cache
o 512 Kb L2 cache
o 4 MB L3 cache
o Introduced January, 2010
o Socket 1156 LGA
o 2-channels DDR3
o Integrated HD GPU
o Variants
530 – 2.93 GHz Hyper-Threading
540 – 3.06 GHz Hyper-Threading
550 – 3.2 GHz Hyper-Threading
560 – 3.33 GHz Hyper-Threading
Core i5
Lynnfield – 45 nm process technology
o 4 physical cores
31
o 32+32 Kb (per core) L1 cache
o 256 Kb (per core) L2 cache
o 8 MB common L3 cache
o Introduced September 8, 2009
o Family 6 Model E (Ext. Model 1E)
o Socket 1156 LGA
o 2-channels DDR3
o Variants
750S – 2.40 GHz/3.20 GHz Turbo Boost
750 – 2.66 GHz/3.20 GHz Turbo Boost
760 – 2.80 GHz/3.33 GHz Turbo Boost
Clarkdale – 32 nm process technology
o 2 physical cores/4 threads
o 64 Kb L1 cache
o 512 Kb L2 cache
o 4 MB L3 cache
o Introduced January, 2010
o Socket 1156 LGA
o 2-channels DDR3
o Integrated HD GPU
o AES Support
o Variants
650/655K – 3.2 GHz Hyper-Threading Turbo Boost
660/661 – 3.33 GHz Hyper-Threading Turbo Boost
670 – 3.46 GHz Hyper-Threading Turbo Boost
680 – 3.60 GHz Hyper-Threading Turbo Boost
Core i7
Bloomfield – 45 nm process technology
o 4 physical cores
o 256 KB L2 cache
o 8 MB L3 cache
o Front side bus replaced with QuickPath up to 6.4GT/s
o Hyper-Threading is again included. This had previously been removed at the introduction of Core line
o 781 million transistors
o Intel Turbo Boost Technology
o TDP 130W
o Introduced November 17, 2008
o Socket 1366 LGA
o 3-channels DDR3
o Variants
975 (extreme edition) – 3.33 GHz/3.60 GHz Turbo Boost
965 (extreme edition) – 3.20 GHz/3.46 GHz Turbo Boost
960 - 3.20 GHz/3.46 GHz Turbo Boost
950 – 3.06 GHz/3.33 GHz Turbo Boost
940 – 2.93 GHz/3.20 GHz Turbo Boost
930 – 2.80 GHz/3.06 GHz Turbo Boost
920 – 2.66 GHz/2.93 GHz Turbo Boost
Lynnfield – 45 nm process technology
o 4 physical cores
o 256 KB L2 cache
32
o 8 MB L3 cache
o No QuickPath, instead compatible with slower DMI interface
o Hyper-Threading is included
o Introduced September 8, 2009
o Socket 1156 LGA
o 2-channels DDR3
o Variants
880 – 3.06 GHz/3.73 GHz Turbo Boost (TDP 95W)
870/875K – 2.93 GHz/3.60 GHz Turbo Boost (TDP 95W)
870S – 2.67 GHz/3.60 GHz Turbo Boost (TDP 82W)
860 – 2.80 GHz/3.46 GHz Turbo Boost (TDP 95W)
860S – 2.53 GHz/3.46 GHz Turbo Boost (TDP 82W)
TODO: Westmere
Gulftown – 32 nm process technology
o 6 physical cores
o 256 KB L2 cache
o 12 MB L3 cache
o Front side bus replaced with QuickPath up to 6.4GT/s
o Hyper-Threading is included
o Intel Turbo Boost Technology
o Socket 1366 LGA
o TDP 130W
o Introduced 16 March 2010
o Variants
990X Extreme Edition - 3.46 GHz/3.73 GHz Turbo Boost
980X Extreme Edition - 3.33 GHz/3.60 GHz Turbo Boost
970 - 3.20 GHz/3.46 GHz Turbo Boost
Intel Core i7 Mobile Processor Family – 45 nm process technology
o 4 physical cores
o Hyper-Threading is included
o Intel Turbo Boost Technology
o Variants
940XM Extreme Edition - 2.13 GHz/3.33 GHz Turbo Boost (8 MB L3, TDP 55W)
920XM Extreme Edition - 2.00 GHz/3.20 GHz Turbo Boost (8 MB L3, TDP 55W)
840QM - 1.86 GHz/3.20 GHz Turbo Boost (8 MB L3, TDP 45W)
820QM - 1.73 GHz/3.06 GHz Turbo Boost (8 MB L3, TDP 45W)
740QM - 1.73 GHz/2.93 GHz Turbo Boost (6 MB L3, TDP 45W)
720QM - 1.60 GHz/2.80 GHz Turbo Boost (6 MB L3, TDP 45W)
Xeon
Gainestown – 45 nm process technology
o Same processor dies as Bloomfield
o 256 KB L2 cache
o 8 MB L3 cache, 4MB may be disabled
o QuickPath up to 6.4GT/s
o Hyper-Threading is included in some models
o 781 million transistors
o Introduced March 29, 2009
o Variants
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W5590, W5580, X5570, X5560, X5550, E5540, E5530, L5530, E5520, L5520, L5518 – 4 Cores, 8 MB L3
cache, HT
E5506, L5506, E5504 – 4 cores, 4 MB L3 cache, no HT
L5508, E5502, E5502 – 2 cores, 4 MB L3 cache, no HT
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