Efficient VLSI Architecture for Discrete Wavelet

Transform

AIM:

The main aim of the project is to design and implement “Efficient VLSI

Architecture for Discrete Wavelet Transform”.

ABSTRACT:

This paper proposes an efficient architecture for 2D DWT. The proposed

architecture includes a transform module, a RAM module and a multiplexer. In

transform module, poly phase decomposition and coefficient folding technique is

applied to the decimation filters of stages 1 and 2 respectively. The advantages of

the proposed architecture are the 100% hardware utilization, fast computing time,

regular data flow and low complexity. Because of the regular structure, the

proposed architecture can be easily be scaled with the filter length and 2D DWT

level. VLSI architecture for the 2-D DWT is implemented using FPGA using

Verilog HDL.

BLOCK DIAGRAM:

V.Mallikarjuna (Project manager) Mobile No: +91-8297578555. ISO: 9001- 2008 CERTIFIED COMPANY Branches: Hyderabad & Nagpur

Fig: Block diagram of the proposed work

TOOLS:

Xilinx 9.2ISE, Modelsim 6.4c.

APPLICATION ADVANTAGES:

The advantages of the proposed architecture are 100% hardware utilization,

fast computing time, regular data flow, low control complexity.

These advantages make the design suitable for image compression systems

in JPEG-2000.

The future work includes implementation of efficient architecture for DWT

using Lifting schemes.

REFERENCES:

Chakrabarti, C. and Mumford, C. 1996. “Efficient realizations of analysis

and Synthesis filters based on the 2D- Discrete wavelet transform in Proc.

IEEE ICASSP, pp. 3256-3255.

V.Mallikarjuna (Project manager) Mobile No: +91-8297578555. ISO: 9001- 2008 CERTIFIED COMPANY Branches: Hyderabad & Nagpur

Chakrabarti, C. and Vishwanath, M. 1996. “Architectures for wavelet

transforms:A survey”,VLSI signal processing, Vol. 14, pp.171-192,

Christopoulos, C., Askelof, J. and Larsson, M. 2000. “Efficient Methods for

Encoding Regions of Interest in the upcoming JPEG 2000 still image

Coding standard”, IEEE signal processing letter, pp.247-249.

Gab Cheon Jung, Duk Young Jin, and Seong Mo Park, 2004. “An Efficient

Line based VLSI Architecture for 2D Lifting DWT”.

Parhi, K.K. and Nishitani, T. 1993. “VLSI architectures for discrete wavelet

Transforms”, IEEE trans. VLSI sys, Vol. 1, pp. 191-202.

V.Mallikarjuna (Project manager) Mobile No: +91-8297578555. ISO: 9001- 2008 CERTIFIED COMPANY Branches: Hyderabad & Nagpur