A FAST MULTIPLIER DESIGN USING SIGNED-DIGIT NUMBERS AND 3-VALUED LOGIC

I-Shi E. Chen and T. N. Rajashekhara

Department of Electrical Engineering State University of Nev York at Binghamton

Binghamton, NY 13902-6000

A bs t rdc t

A multiplier design using 3-valued (ternary) logic and redundant binary signed-digit (RBSD) numbers is presented in this paper. The use of 3-valued logic offers the advantage of reduced circuit complexity both i n terms of transistor count and interconnections since each ternary bit can support one digit of the RBSD number system. The choice of RBSD number system enhances the speed of multiplication by allowing carry free addition of partial products. While the internal multiplication uses RBSD numbers, both the input operands and the output product are assumed to be in the standard tvo's complement form. MAGIC and SPICE softvare tools vere used t o produce VLSI design layouts and circuit simulation results.

1. Introduction

In many computer applications such as signal and image processing, computer graphics, and process control, multiplication is one of the most vital functions. The demand placed by these applications on the speed of multiplication is motivating researchers to look for alternative approaches for designing high speed multipliers. Using non-conventional number system such as signed-digit numbers for designing fast arithmetic units is particularly gaining much attention in recent years. Signed-digit number system offers the possibility of carry free addition by taking advantage of the redundancv associated vith this

in the digit set {-l,O,l} of RBSD requires only one ternary bit. Rajashekhara and Chen 161 have presented a scheme for RBSD addition using ternary logic. In this paper, ve present the design of a multiplier unit using the RBSD adder cells presented in 161 . In section 2 , we shall discuss briefly signed-digit numbers and RBSD addition. In section 3, ve shall discuss the multiplier design using 3-valued RBSD adders. In section 4, ve shall summarize the contributions of this paper.

2. RBSD Addition and T e r n a r y L o g i c

Each digit of a signed-digit (SDI number representation in radix r is made up of an element from the digit set {-a, -(a-l),..., -1, 0, , (a-l), a) vhere a is chosen to be Lr/2r to yield mininurs redundancy. An SD number vith radix 2 and digit set (-l,O,l) is called redundant binary signed-digit (RBSD) number. Addition of tvo RBSD numbers can be carried out in parallel in three steps as shown in Figure 1 and described by equations (11, ( 2 1 , and (3). An RBSD adder design using 3-valued logic is described in [61 . Ternary logic is very suitable for designing arithmetic units using RBSD number system since each ternary bit can support one digit of the RBSD number. The truth table of ternary inverter gates used in designing RBSD adder circuit is given in Table 1.

-

=i+2 representation. Several papers have appeared xi+l- in recent years exploring the use of

arithmetic units [l-61. Takagi et a1 [11 have r

redundant binary signed-digit numbers. In this paper, the partial products are added pair-vise vhich reduces the number of - the vord length. Booth recoding technique is yi - also utilized to reduce the number of partial

products are added in constant time, since the partial products are represented in RBSD xi-*

signed-digit numbers for designing fast Yi+l- "i+l = i+2 t' presented a high speed multiplier design using I1

7

_I I %+l

additions in proportion to the logarithm of wi 111 .

products by a factor of tvo. Tvo partial

number system. Rajashekhara and Kal I 4 1 have I presented an implementation of the same idea yi-+ W

I1 d- i W'

- i-1 vith reduced logic complexity making it suitable for VLSI implementation. In both these designs RBSD numbers are represented using binary logic vhich requires two bits per digit of RBSD number. Though these designs are able to achieve

of inter connections can be significantly reduced if a

Figure 1: RESD Adder Structure

higher speeds, the circuit complexity and the number

proper choice of logic implementation compatible vith the number system is made. Ternary or 3-valued logic

xi + Yi = vi t 2*titl vi + ti = VIi t 2*t'i+l VI. t t'i = s

blends itself vith RBSD number system since each digit i

CH28 19- 1/90/0000-088 1$01 .OOO1991 IEEE

Table 1

Truth table of Ternary Inverter Gates

Input (x) output ( i ) STI PTI NTI

0 0 1 -1 1 -1 -1 -1 -1 1 1 1

STI: Simple Ternary Inverter PTI: Positive Ternary Inverter NTI: Negative Ternary Inverter

A ternary T gate vhose function is described by equation (4) is realized using PTI and NTI gates. An appropriate combination of T gates is used to realize the RBSD adder functions described by equations (11, (21, and ( 3 ) .

T(y1,y2,y3: x ) = yi; i = 1 if x = -1 (4) = 2 i f x = O = 3 i f x = 1

vhere yl, y2, y3 are gate inputs, x is control input, and yi is gate output.

3. RBSD Multiplier Design

The RBSD adder discussed above and described in I61 is utilized for adding the partial products in designing the multiplier. Bit pair recoding 171 of the multiplier operand is employed to reduce the number of partial products by a factor of 2. Partial products are added in a pair-vise binary tree fashion 111 vhich reduces the number of partial product pairs to be added in proportion to the logarithm of the word length of the multiplier operand. Since the add time is constant independent of the word length, the multiplication time is of the order O(log2n) for an n-bit multiplier operand. Though the internal addition is performed on RBSD numbers, the input operands are

J A2 J

A3

assumed to be in standard tvo's complement (TC) form and the RBSD product is converted back to TC form thus making the design suitable to be used as a building block in digital systems using binary number system. Figure 2 shovs the block diagram of a 4x4 multiplier unit. The multiplier and multiplicand operands are in TC form. The partial product generator (PPG) generates the partial product bits in RBSD form using bit-pair recoding technique. Figure 3 shovs the circuit diagram of the PPG. This circuit is an implementation of Table 2 which shovs the RBSD product bit as a function of TC multiplicand and multiplier bits. The multiplier and multiplicand bits use binary logic with logic 0 and 1 represented by voltage levels OV and 5V respectively vhile the partial product bits use ternary logic vith logic -1, 0, and 1 represented by voltage levels OV, 2.5V, and 5V respectively. The partial product bits should yield 0, 1, -1, 2 , or -2 times the multiplicand depending on the pattern of multiplier bits Bjt l , Bj, and Bj-l. The partial product bits a (-a) in columns PP. . and PPjtitl represent 1 (-1) and 2 (-2) times the multiplicand respectively. Since the multiplier and multiplicand are in TC form, a 1 in the most significant bit position of the multiplier represents a negative number and this is reflected in the partial product by changing the sign of nonzero elements as seen in the right tvo columns of Table 2. An example of obtaining

3+1

the partial products is shovn belov:

B5B4B3B2B1B0 Multiplier 0 1 1 0 1 1 Multiplicand

Partial product corresponding to BIBOB-l 1 -1 0 0 -1 0 vhich is -1 times the mult

Partial product corresponding to B3B2B1

A SA qA 3A2A lA0 1 1 0 0 1 0

(110) is pl icand . 101) is

1 -1 0 0 -1 0 vhich is also -1 times the multiplicand.

Partial product corresponding to B5B4B3 (011) is -1 1 0 0 1 0 0 vhich is 2 times the multiplicand.

J AO J

PPG

RBSD pp1 Product

to TC +

RBSD ADDER * 4 TC

Product

.? ? .? .?

A 3 A2 A1 AO

PPG = Partial Product Generator B B B B = Multiplier Operand, A A A A = Multiplicand Operand 3 2 1 0 3 2 1 0

Figure 2 Block Diagram of a 4x4 Multiplier

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To ensure proper positional veightages each subsequent partial product is left shifted tvo digit positions vith respect to the previous partial product before the partial products are added.

It may be noted here that the complete circuit of Figure 3 is used only for the PPG corresponding to the HSB of the multiplicand (A3) in Figure 2. The PPG

corresponding to the next lover significant bit of the multiplicand (AZ) consists of only part a of Figure 3

vith OV and 5V lines interchanged. All other PPGs consist of only part b of Figure 3. The choice of only portions of Figure 3 for partial product generation significantly reduces the chip area for operands vith large vord length.

The partial products are properly aligned and added pair-vise using RBSD adder as shovn in Figure 2. For n-bit operands, rn/21 partial products are generated and pair-vise addition of these partial products requires log2rn/21 levels of RBSD adders. Since addition at each level is done in constant time independent of operand length, the multiplication time is of order O(10g2rn/21). Hovever, the product is available in RBSD form. To make the design compatible with other digital systems, it is desirable to convert the RBSD product into TC form. The RBSD to TC converter block shown in Figure 2 is designed using a borrow look back ( B L B ) technique suggested by Rajashekhara and Nale [51.

F i g u r e 3 C i r c u i t Schematic of P a r t i a l P r o d u c t G e n e r a t o r (PPG)

T a b l e 2

B i t - P a i r Recoding to Generate RBSD P a r t i a l P r o d u c t B i t s

Multiplier Multiplicand

Bjtl Bj Bj-l A i

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

partial ppjti ppjtitl

( i f A i is not MSB)

0 a a

- a -a

-a -a 0

- - -

product ppjti (if Ai 0 -a -a - - a a a

Note: B jtl, Bj, Bj-l, Ai are in TC form. The logic levels 0 and 1 corresponds to 08 and SV respectively. x means don't care. a E {O,l). PPjti and PPjtitl are in RBSD form. The logic levels -1, 0, and 1 corresponds to OV, 2.5V, and 5V respectively. 0 and -0 are the same as 0.

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4. Conclusion 4. References

In this paper, we have presented a multiplier design vhich makes use of RBSD adders designed uslng 3-valued logic. Bit pair recoding 1s employed to generate partial products in RBSD for0 using TC multiplier and multiplicand operands. VLSI layouts are produced for RBSD adder and partial product generator circuits using MAGIC software on SUN vork station. Figures 4 lnd 5 show the layouts of portions of RBSD adder and partial product generator circuits respectively. Each functional unit and the complete multiplier circuit are simulated using SPICE circuit simulation software to verify the correctness of design. Currently ve are vorking on the VLSI layout far a prototype of the complete multiplier unit including RBSD to TC converter. Extending bit pair recoding to multi-bit recoding [ 8 1 is an interesting approach to explore and investigate the trade off betveen increased circuit complexity of multi-bit recoding and reduced set of partial products.

Figure 4 VLSI Layout of RBSD Adder C e l l Represen t ing e q u a t i o n ( l ) , F i g . 1

[11 Takagi, N. et al., "High Speed VLSI Multiplication Algorithm with A Redundant Binary Addition Tree," IEEE Trans. Comput., Vol. C-34, No. 9, pp. 789-796, Sept. 1985.

[21 S. Kawahito, M. Kamayerna, T. Higuchi, and H. Yama- da, "A 32x32-bit Multiplier Using Multiple-valued MOS Current-Mode Circuits," IEEE J. Solid State Circuits, Vol. 23, No. 1, pp. 124-132, Febr. 1988.

131 S. Kavahito, M. Kamayema, and T. Higuchi, Multiple -Valued Radix-2 Signed-Digit Arithmetic Circuits for High Performance VLSI Systems," IEEE J. Solid State Circuits, Vol. 25, No. 1, pp. 125- 131, Febr. 1990.

I41 Rajashekhara, T. N. and Kal, O., "Fast Multiplier Design Usincj Redundant Signed-Digit Numbers," to International Journal of Electronics, Vol. 69, 1990.

I51 Rajashekhara, T. N. and Nale, A. S . , "Conversion Representa-

Electronics, Vol. from Signed-Digit to Radix Complement tion," International Journal of 69, 1990.

61 Rajashekhara, T. N. and I-Shi E. Chen, "A Fast Adder Design Using Signed-Digit Numbers and Ternary Logic," Proc. 1990 IEEE Southern Tier Technical Conference, pp. 187-194, Binghamton, New York, April 1990.

McGraw-Hill 1984. 71 J. J. F . Cavanagh, "Digital Computer Arithmetic,"

( 8 1 H. Sam and A. Gupta, "A Generalized Multi-bit Recoding of TWO'S Complement Binary Numbers and Its Proof vith Applications in Multiplier Impleme- ntations," IEEE Tr. Computers, Vol. 39, No. 8, pp. 1006-1015, Aug. 1990.

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F i g u r e 5 VLSI Layout of P a r t i a l Product Genera to r F i g u r e 3.

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