Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 1

Chapter 11 Tree and Array MultipliersFull-Tree MultipliersAlternative Reduction TreesTree Multipliers for Signed NumbersPartial-Tree MultipliersArray MultipliersPipelined Tree and Array Multipliers

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 2

Full-Tree Multipliers

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 3

Full-Tree Multipliers1. All multiples of the multiplicand are produced in

parallel.

2. k-input CSA tree is used to reduce them to two operands.

3. A CPA is used to reduce those two to the product.

No feedback → pipelining is feasible.

Different multiplier arrays are distinguished by the designs of the above three elements.

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 4

General Structure of a Full-tree Multiplier

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 5

Radix Tradeoffs

The higher the radix ….• The more complex the multiple-forming

circuits, and• The less complex the reduction tree.

Where is the optimal cost-effectiveness?• Depends on design• Depends on technology

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 6

Tradeoffs in CSA TreesWallace Tree Multiplier

• Combine partial product bits at the earliest opportunity.

• Leads to fastest possible design.

Dadda Tree Multiplier• Combine as late as possible, while keeping the critical

path length (# levels) of the tree minimal.• Leads to simpler CSA tree structure, but wider CPA

at the end.

Hybrids• Some where in between.

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 7

Two Binary 4 × 4 Tree Multipliers

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 8

Reduction Tree

Results from chapter 8 apply to the design of partial product reduction trees.• General CSA Trees• Generalized Parallel Counters

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 9

CSA for 7 × 7 Tree Multiplier

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 10

Structure of a CSA Tree

A logarithmic depth reduction trees based on CSAs (e.g. Wallace, Dadda. Etc.)

• Have an irregular structure.• Make design and layout difficult.

Connections and signal paths of various lengths• Lead to logic hazards and signal skew.• Implication for both performance and power

consumption.

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 11

Alternative Reduction Trees (n;2) Counters(more suitable to VLSI)

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 12

A Balanced (11;2) Counter1. Balanced: All outputs

are produced after the same number of delays.

2. All carries produced at evel i enter FAs at level i+1.

3. Can be laid out to occupy a narrow vertical slice.

4. Can be easily expanded to a (18;2) counter.

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 13

Tree Multiplier Based on (4,2) Counters

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 14

Layout of Binary Reduction Tree

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 15

Sign Extension

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 16

Signed Addition

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 17

Baugh-Wooley Arrays

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 18

Partial Tree Multipliers

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 19

Basic Array MultiplierUsing a One-Sided CSA Tree

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 20

Unsigned Array Multiplier1

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 21

Unsigned Array Multiplier2

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 22

Baugh-Wooley Signed Multiply

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 23

Signed Multiplier Array

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 24

Mixed Positive and Negative Binary

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 25

Mixed Binary Full Adders

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 26

5 × 5 Signed MultiplierUsing Mixed +/− Numbers

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 27

Include AND Gates in Cells

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 28

Change the Terms of the Problem

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 29

Multiplier Without Final CPA

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 30

Conditional Carry-Save

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 31

Pipelined Partial-Tree Multiplier

Computer Arithmetic Circuit Design

Ch 11. Tree and Array Multipliers 32

Pipelined Array Multiplier