The top documents tagged [subthreshold leakage]

Closing the Power Gap between ASIC and Custom David Chinnery, Kurt Keutzer
Documents Closing the Power Gap between ASIC and Custom David Chinnery, Kurt Keutzer

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LOW-LEAKAGE REPEATERS FOR NETWORK-ON-CHIP INTERCONNECTS Arkadiy Morgenshtein, Israel Cidon, Avinoam Kolodny, Ran Ginosar Technion – Israel Institute of
Documents LOW-LEAKAGE REPEATERS FOR NETWORK-ON-CHIP INTERCONNECTS Arkadiy Morgenshtein, Israel Cidon, Avinoam Kolodny, Ran Ginosar Technion – Israel Institute of

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ECE 7366 Advanced Process Integration Beyond Planar CMOS Dr. Wanda Wosik Text Book: B. El-Karek, “Silicon Devices and Process Integration” 1
Documents ECE 7366 Advanced Process Integration Beyond Planar CMOS Dr. Wanda Wosik Text Book: B. El-Karek, “Silicon Devices and Process Integration” 1

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A Low-Leakage 2.5GHZ Skewed CMOS 32-Bit Adder For Nanometer CMOS Technologies Advanced VLSI Course Seminar December 28, 2006 Peresented by: Rabe’e Majidi
Documents A Low-Leakage 2.5GHZ Skewed CMOS 32-Bit Adder For Nanometer CMOS Technologies Advanced VLSI Course Seminar December 28, 2006 Peresented by: Rabe’e Majidi

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Power Gating Structure for Reversible Programmable Logic Array
Documents Power Gating Structure for Reversible Programmable Logic Array

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Domino Ckts Using Dual Vt
Documents Domino Ckts Using Dual Vt

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Source: Lundstrom/Fossom/Yang/Neudeck, Purdue EE612 lecture notes
Documents Source: Lundstrom/Fossom/Yang/Neudeck, Purdue EE612 lecture notes

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Power Management in High Performance Processors through Dynamic Resource Adaptation and Multiple Sleep Mode Assignments Houman Homayoun National Science
Documents Power Management in High Performance Processors through Dynamic Resource Adaptation and Multiple Sleep Mode Assignments Houman Homayoun National Science

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Background for Leakage Current Sept. 18, 2006. Power Challenge Active power density increasing with device scaling and increased frequency Leakage power
Documents Background for Leakage Current Sept. 18, 2006. Power Challenge Active power density increasing with device scaling and increased frequency Leakage power

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Low Power Design of Integrated Systems
Documents Low Power Design of Integrated Systems

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FinFETs: From Circuit to Architecture
Documents FinFETs: From Circuit to Architecture

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CAE tools and technology challenges in making deep sub-micron IC designs Kostas Kloukinas CERN, PH-ESE dept. CH1211, Geneve 23 Switzerland ESE Group seminar
Documents CAE tools and technology challenges in making deep sub-micron IC designs Kostas Kloukinas CERN, PH-ESE dept. CH1211, Geneve 23 Switzerland ESE Group seminar

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