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The top documents tagged [db sfdr]
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ads7230.pdf
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System Aspects of ADC Design SHANTHI PAVAN Assistant Professor Department of Electrical Engineering Indian Institute of Technology, Madras 05/18/01 V4.3
214 views
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A 600MS/s 30mW 0.13µm CMOS ADC Array Achieving over 60dB SFDR with Adaptive Digital Equalization
57 views
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A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC Byung-Geun Lee, Member, IEEE, Byung-Moo Min, Senior Member, IEEE, Gabriele Manganaro, Senior
217 views
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Integrated receivers for mid-band SKA
42 views
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A Low-Power Low-Voltage 10-bit 100- MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques Kazutaka Honda, Student Member, IEEE, Masanori
219 views
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Clock Generation for a SHA-less 10-bit 100Mhz Pipeline ADC Victor Lu, Pingli Huang, Yun Chiu
71 views
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System Aspects of ADC Design
51 views
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By Patrick Ellis and Scott Jaris Advisors: Dr. Ahn & Dr. Lu
43 views