The top documents tagged [circuit delay]

Lecture15
Business Lecture15

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VLSI Test Technology & Reliabillity - Module 6 combinational_circuit_testing
Education VLSI Test Technology & Reliabillity - Module 6 combinational_circuit_testing

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©2010 Cengage Learning Engineering. All Rights Reserved.8-0 Combinational Circuit Design and Simulation Using Gates PowerPoint Presentation © 2010. Cengage
Documents ©2010 Cengage Learning Engineering. All Rights Reserved.8-0 Combinational Circuit Design and Simulation Using Gates PowerPoint Presentation © 2010. Cengage

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CMOS Circuit and Logic Design* CMOS Logic Gate Design: –Is the design logically functional? Adequate power supply connections Noise margins OK Transistors
Documents CMOS Circuit and Logic Design* CMOS Logic Gate Design: –Is the design logically functional? Adequate power supply connections Noise margins OK Transistors

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Aging-Aware Compiler-Directed VLIW Assignment for GPGPU Architectures
Engineering Aging-Aware Compiler-Directed VLIW Assignment for GPGPU Architectures

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Xing Wei, Wai-Chung Tang, Yu-Liang Wu Department of Computer Science and Engineering The Chinese University of HongKong {xwei,wctang,ylw}@cse.cuhk.edu.hk
Documents Xing Wei, Wai-Chung Tang, Yu-Liang Wu Department of Computer Science and Engineering The Chinese University of HongKong {xwei,wctang,ylw}@cse.cuhk.edu.hk

216 views

Improving Placement under the Constant Delay Model Kolja Sulimma 1, Ingmar Neumann 1, Lukas Van Ginneken 2, Wolfgang Kunz 1 1 EE and IT Department University
Documents Improving Placement under the Constant Delay Model Kolja Sulimma 1, Ingmar Neumann 1, Lukas Van Ginneken 2, Wolfgang Kunz 1 1 EE and IT Department University

213 views

X-Architecture Placement Based on Effective Wire Models Tung-Chieh Chen, Yi-Lin Chuang, and Yao-Wen Chang Graduate Institute of Electronics Engineering
Documents X-Architecture Placement Based on Effective Wire Models Tung-Chieh Chen, Yi-Lin Chuang, and Yao-Wen Chang Graduate Institute of Electronics Engineering

214 views

SimPL: An Effective Placement Algorithm Myung-Chul Kim, Dong-Jin Lee and Igor L. Markov Dept. of EECS, University of Michigan 1ICCAD 2010, Myung-Chul Kim,
Documents SimPL: An Effective Placement Algorithm Myung-Chul Kim, Dong-Jin Lee and Igor L. Markov Dept. of EECS, University of Michigan 1ICCAD 2010, Myung-Chul Kim,

219 views

Congestion Driven Placement for VLSI Standard Cell Design Shawki Areibi and Zhen Yang School of Engineering, University of Guelph, Ontario, Canada December
Documents Congestion Driven Placement for VLSI Standard Cell Design Shawki Areibi and Zhen Yang School of Engineering, University of Guelph, Ontario, Canada December

218 views

PRACTICAL DYNAMIC THERMAL MANAGEMENT ON INTEL DESKTOP COMPUTER Guanglei Liu Department of Electrical and Computer Engineering Florida International University
Documents PRACTICAL DYNAMIC THERMAL MANAGEMENT ON INTEL DESKTOP COMPUTER Guanglei Liu Department of Electrical and Computer Engineering Florida International University

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Interconnect Optimization for Deep-Submicron and Giga-Hertz ICs Lei He helei UCLA Computer Science Department Los Angeles, CA
Documents Interconnect Optimization for Deep-Submicron and Giga-Hertz ICs Lei He helei UCLA Computer Science Department Los Angeles, CA

213 views