The top documents tagged [cache lines]

Reducing Leakage Power in Peripheral Circuits of L2 Caches Houman Homayoun and Alex Veidenbaum Dept. of Computer Science, UC Irvine {hhomayou, alexv}@ics.uci.edu
Documents Reducing Leakage Power in Peripheral Circuits of L2 Caches Houman Homayoun and Alex Veidenbaum Dept. of Computer Science, UC Irvine {hhomayou, alexv}@ics.uci.edu

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1 Garbage Collection Reference Counting Mark-and-Sweep Short-Pause Methods
Documents 1 Garbage Collection Reference Counting Mark-and-Sweep Short-Pause Methods

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BEAR: MITIGATING BANDWIDTH BLOAT IN GIGASCALE DRAM CACHES Chiachen Chou, Georgia Tech Aamer Jaleel, NVIDIA* Moinuddin K. Qureshi, Georgia Tech ISCA 2015
Documents BEAR: MITIGATING BANDWIDTH BLOAT IN GIGASCALE DRAM CACHES Chiachen Chou, Georgia Tech Aamer Jaleel, NVIDIA* Moinuddin K. Qureshi, Georgia Tech ISCA 2015

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SCALABLE PACKET CLASSIFICATION USING INTERPRETING A CROSS-PLATFORM MULTI-CORE SOLUTION Author: Haipeng Cheng, Zheng Chen, Bei Hua and Xinan Tang Publisher/Conf.:
Documents SCALABLE PACKET CLASSIFICATION USING INTERPRETING A CROSS-PLATFORM MULTI-CORE SOLUTION Author: Haipeng Cheng, Zheng Chen, Bei Hua and Xinan Tang Publisher/Conf.:

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1 Architectural Side Channels in Cloud Computing Eran Tromer MIT Includes joint works with Adi Shamir, Dag Arne Osvik Stefan Savage, Hovav Shacham, Thomas
Documents 1 Architectural Side Channels in Cloud Computing Eran Tromer MIT Includes joint works with Adi Shamir, Dag Arne Osvik Stefan Savage, Hovav Shacham, Thomas

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Power, Temperature, Reliability and Performance - Aware Optimizations in On-Chip SRAMs Houman Homayoun PhD Candidate Dept. of Computer Science, UC Irvine
Documents Power, Temperature, Reliability and Performance - Aware Optimizations in On-Chip SRAMs Houman Homayoun PhD Candidate Dept. of Computer Science, UC Irvine

216 views

Adaptive Techniques for Leakage Power Management in L2 Cache Peripheral Circuits Houman Homayoun Alex Veidenbaum and Jean-Luc Gaudiot Dept. of Computer
Documents Adaptive Techniques for Leakage Power Management in L2 Cache Peripheral Circuits Houman Homayoun Alex Veidenbaum and Jean-Luc Gaudiot Dept. of Computer

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Computer Architecture 2011 – Caches 1 Lihu Rappoport and Adi Yoaz Computer Architecture Cache Memory
Documents Computer Architecture 2011 – Caches 1 Lihu Rappoport and Adi Yoaz Computer Architecture Cache Memory

233 views

Hoard: A Scalable Memory Allocator for Multithreaded Applications -- Berger et al. -- ASPLOS 2000 Emery Berger, Kathryn McKinley *, Robert Blumofe, Paul
Documents Hoard: A Scalable Memory Allocator for Multithreaded Applications -- Berger et al. -- ASPLOS 2000 Emery Berger, Kathryn McKinley *, Robert Blumofe, Paul

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Paging Algorithms Vivek Pai / Kai Li Princeton University
Documents Paging Algorithms Vivek Pai / Kai Li Princeton University

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Ray Tracing Performance Zero to Millions in 45 Minutes Gordon Stoll, Intel
Documents Ray Tracing Performance Zero to Millions in 45 Minutes Gordon Stoll, Intel

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Copyright Philipp Slusallek IBR: View Interpolation Philipp Slusallek
Documents Copyright Philipp Slusallek IBR: View Interpolation Philipp Slusallek

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