12
M. S. Ramaiah School of Advanced Studies 1 M. Sc. (Engg.) in Electronics System Design Engineering GREESHMA S CWB0913004 , FT-2013 2 nd Module Presentation Module code : ESE2502 Module name : Advanced Electronic Circuit Design Module leader : Ms. Lasitha.M Presentation on : 26/11/2013

JHDL BITS: THE INTEGRATION OF TWO PROMINENT FPGA DESIGN TOOLS

Embed Size (px)

Citation preview

Page 1: JHDL BITS: THE INTEGRATION OF TWO PROMINENT FPGA DESIGN TOOLS

M. S. Ramaiah School of Advanced Studies 1

M. Sc. (Engg.) in Electronics System Design

Engineering

GREESHMA SCWB0913004 , FT-2013

2nd Module Presentation

Module code : ESE2502

Module name : Advanced Electronic Circuit

Design

Module leader : Ms. Lasitha.M

Presentation on : 26/11/2013

Page 2: JHDL BITS: THE INTEGRATION OF TWO PROMINENT FPGA DESIGN TOOLS

M. S. Ramaiah School of Advanced Studies 2

JHDL BITS: THE INTEGRATION

OF TWO PROMINENT FPGA

DESIGN TOOLS

Page 3: JHDL BITS: THE INTEGRATION OF TWO PROMINENT FPGA DESIGN TOOLS

M. S. Ramaiah School of Advanced Studies 3

• ABSTRACT

• INTRODUCTION

• JHDL

• RELATIONSHIPS OF OPEN SOURCE CONSTITUENTS OF

JHDLBITS

• JHDLBITS DESIGN FLOW

• JHDLBITS IMPLEMENTATION

• ADVANTAGES & DISADVANTAGES

• CONCLUSION

Page 4: JHDL BITS: THE INTEGRATION OF TWO PROMINENT FPGA DESIGN TOOLS

M. S. Ramaiah School of Advanced Studies 4

• JHDL Bits: the integration of two prominent FPGA design tools: JHDL and JBits.

• JHDL Bits offers high-level structural circuit design, control provided by JBits with

high level circuit design of JHDL.

• JHDL Bits flow provides greater control of resource manipulation, placement and

routing and gives researchers a “sand box” to explore advanced interactions with

FPGA Bistreams.

• The overall architecture of the open source JHDL Bits.

• Detailed explanation on how the core components- JHDL, JBits3 for vertex-II, and

ADB connectivity database- are linked together to provide a cohesive design

environment.

Page 5: JHDL BITS: THE INTEGRATION OF TWO PROMINENT FPGA DESIGN TOOLS

M. S. Ramaiah School of Advanced Studies 5

• FPGA –related research require a testbed for exploring and evaluating new tools

algorithms, and new ways to interact with FPGA Bitstream.

• For example, placement enhancements on wire length.

• Many languages , IDEs, and compilers have emerged in recent years that offer

interesting environments for creating FPGA bit streams, but more rely on the

FPGA vendors’ implementation flows to map, place, and route the final design.

• JHDL Bits is an open source endeavor striving to merge the salient features of

these two prominent FPGA research environments.

• The relevance of such exploration diminished since the results from the

experimental could not be definitely confirmed on a real FPGA since FPGA

vendors are secretive on the low-level architecture details of their products.

Page 6: JHDL BITS: THE INTEGRATION OF TWO PROMINENT FPGA DESIGN TOOLS

M. S. Ramaiah School of Advanced Studies 6

• JHDL is a java based design language, it’s object oriented language.

• The Primary distinction of JHDL is the creation of a single integrated API.

• JHDL is a structural HDL.

• Java classes form the basis for all circuits:

• Logic

•Wire

• The JHDL libraries were created in a layered fashion.

• The Features include I/O, recursion, control flow constructs, functions, user-defined

types and reflection.

• The key feature of JHDL is it’s ability to operate in either simulation or hardware

mode.

Page 7: JHDL BITS: THE INTEGRATION OF TWO PROMINENT FPGA DESIGN TOOLS

M. S. Ramaiah School of Advanced Studies 7

Page 8: JHDL BITS: THE INTEGRATION OF TWO PROMINENT FPGA DESIGN TOOLS

M. S. Ramaiah School of Advanced Studies 8

Page 9: JHDL BITS: THE INTEGRATION OF TWO PROMINENT FPGA DESIGN TOOLS

M. S. Ramaiah School of Advanced Studies 9

Page 10: JHDL BITS: THE INTEGRATION OF TWO PROMINENT FPGA DESIGN TOOLS

M. S. Ramaiah School of Advanced Studies 10

• Easy to use.

• Has built in documentation capabilities.

• Is portable.

• Has rich set of GUI API that are integral to the language.

• The net interaction with router must be improved to decrease memory usage and

reduce routing time.

• Improve execution time.

• Improve robustness.

• Provide more flexible interface between JHDL and the router.

Page 11: JHDL BITS: THE INTEGRATION OF TWO PROMINENT FPGA DESIGN TOOLS

M. S. Ramaiah School of Advanced Studies 11

• A major goal has been to retain the properties and philosophies of Jbits.

• It was essential to provide the ability to reconfigure the device through

JHDLBits design flow.

• It allows partitioning of design.

• The developers would investigate using JHDLBits in an embedded system,

using small subset of JHDL rewritten in language other than Java to reduce

memory usage.

• In current version of JHDLBits, placement is performed in a greedy sub-

optimal manner.

REFERENCE Alexander Poetter (2005). JHDLBits. Blacksburg: Virginia

Tech. 1-10.

Page 12: JHDL BITS: THE INTEGRATION OF TWO PROMINENT FPGA DESIGN TOOLS

M. S. Ramaiah School of Advanced Studies 12