VLSI Design Final Project - 32 bit ALU

1

EECT-6325 VLSI DESIGN

PROJECT- 6

DESIGN OF 32-bit ALU

Submitted by:

Arun Nagar Nadarajan

Balachandran Jayachandran

Sachin Kumar Asokan

2

INDEX

S.No Contents Page No. 1. Project Overview 3

2. Behavioral Verilog code and Testbench 4

3. Cell Library - Layouts 8

4. Simulated waveforms 15

5. D-Flip Flop design 22

6. Tradeoffs 30

7. Function 31

8. Scope 32

9. Final Layout and Schematic 33

9. ALU Output Waveform 34

10. Final layout DRC and LVS reports 36

11. Primetime report 37

3

Project Overview

An Arithmetic Logic Unit (ALU) is a functional block of any

processor. It is used to perform arithmetical and logical

operations. ALU’s are designed to perform integer based

operations. In this module, we have designed an ALU which

performs certain specific operations on 32 bit numbers.

The arithmetic operations performed are: Addition, subtraction

and multiplication. The logical operations performed are: AND,

OR, XNOR, left shift and right shift.

The behavioral Verilog code and testbench were simulated using

MODELSIM to verify the functionality.

The individual gates (INVERTER, NAND2, NOR2, XOR2, OAI3222,

AOI22, MUX2:1) which constituted to the cell library were laid out

in CADENCE. The DRC and LVS run were successfully completed

to ensure usage. These individual layouts were combined and the

combined DRC was run without any errors.

The D flip flop (DFF) was laid out and the static timing analysis

were done using Waveform viewer and it’s functionality was

verified and the D flip flop times were calculated.

By putting together these cells which were designed, the ALU was

developed and the outputs were obtained.

4

Behavioral Verilog Code

module alumod(a,b,out,s,clk);

input [31:0]a,b;

input [3:0]s;

input clk;

output [31:0]out;

reg [31:0]out;

always @(posedge clk)

begin

case(s)

4'b0000: out=add(a,b);

4'b0001: out=sub(a,b);

4'b0010: out=mul(a,b);

4'b0011: out=and1(a,b);

4'b0100: out=or1(a,b);

4'b0101: out=xnor1(a,b);

4'b0110: out=rshift(a,b);

4'b0111: out=lshift(a,b);

endcase

end

function [31:0]add; //addition operation

input [31:0]a,b;

add=a+b;

endfunction

function [31:0]sub; //subtraction operation

input [31:0]a,b;

sub=a-b;

endfunction

5

function [31:0]mul; //multiplication operation

input [31:0]a,b;

mul=a*b;

endfunction

function [31:0]and1; //and operation

input [31:0]a,b;

and1=a&b;

endfunction

function [31:0]or1; // or operation

input [31:0]a,b;

or1=a|b;

endfunction

function [31:0]xnor1; //xor operation

input [31:0]a,b;

xnor1=a~^b;

endfunction

function [31:0]lshift; //shift operation

input [31:0]a,b;

lshift=a<<b;

endfunction

function [31:0]rshift; // right shift operation

input [31:0]a,b;

rshift=a>>b;

endfunction

endmodule

6

Testbench

module main;

reg clk;

reg [31:0] a,b;

reg [3:0] s;

wire [31:0] out;

initial begin

a = 32'b00000000000000000000000000001001; //a and b are the operand values

b = 32'b00000000000000000000000000000010;

s = 4'b0000;

clk = 0;

end

always begin

#100 s = 4'b0001; //s for switching

#100 s = 4'b0010;

#100 s = 4'b0011;

#100 s = 4'b0100;

#100 s = 4'b0101;

#100 s = 4'b0110;

#100 s = 4'b0111;

#100 s = 4'b0000;

end

always begin

#5 clk=~clk;

end

alumod as1 (a,b,out,s,clk);

endmodule

7

Behavioral code output waveform

8

CELL LAYOUTS

INVERTER

9

NAND

10

NOR

11

XOR

12

AOI22

13

MUX

14

OAI3222

15

Simulated Waveform –Inverter

16

Simulated Waveform –NAND2

17

Simulated Waveform –MUX 2:1

18

Simulated Waveform –NOR2

19

Simulated Waveform –AOI22

20

Simulated Waveform –OAI3222

21

Simulated Waveform –XOR2

22

D flip flop schematic

23

D flip flop Layout

24

D flip flop Simulation Results

Transient Analysis

HSPICE code:

$Transient Analysis:

.include "/home/cad/kits/IBM_CMRF8SF-LM013/IBM_PDK/cmrf8sf/relLM/HSPICE/models/model013.lib_inc"

.include "DFFLVS.sp"

.GLOBAL vdd! gnd!

.option post runlvl=5

xi clk d reset q DFF

.param VDD=1.2

vdd vdd! gnd! 1.2V $ VDD voltage

Vin1 clk gnd! pulse (0V 1.2V 0ps 93.75ps 93.75ps 1406ps 3000ps)

Vin2 d gnd! pulse (0V 1.2V 0ns 93.75ps 93.75ps 5906ps 12000ps)

Vin3 reset gnd! pulse (1.2V 0V 0ns 93.75ps 93.75ps 15500ps 24000ps)

cout q gnd! 25f $ output load capacitor

.tr 0.01ns 24ns

.end

Simulated Waveforms:

Wave1: falling edge triggered

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Wave2: showing Asynchronous reset

Calculating D flip flop times

The Tsu and Tclk->Q were calculating by sweeping the input ‘D’ value and

running the HSPICE simulations. The delay time is the summation of the Tsu

and Tclk->Q.

The drop dead time (Tsu_dd) and the hold time (Thold) were computed by

plotting a graph between the setup time and delay time.

The used HSPICE codes and the waveforms obtained are attached in the

report below.

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Passing 0:

HSPICE code

$Passing 0



.GLOBAL vdd! gnd!



.param VDD=1.2V

.param const=4499ps



Vin2 d gnd! PWL (0ns VDD 'const' VDD 'const+93.75ps' 0)

Vin3 reset gnd! pulse (0V 0V 0ps 93.75ps 93.75ps 1406ps 3000ps)


.meas tsetup trig v(d) val=0.6 fall=1

+targ v(clk) val=0.6 fall=2

.meas tclktoq trig v(clk) val=0.6 fall=2

+targ v(q) val=0.6 fall=1

.tran 0.001ns 10ns sweep const 4400ps 4500ps 1ps

.end

Passing “0”

Waveforms showing different setup time for ‘D’

27

Setup vs Delay time (passing “0”)

Passing 1:

HSPICE code

$Passing 1



.GLOBAL vdd! gnd!



.param VDD=1.2V

.param const=4499ps



Vin2 d gnd! PWL (0ns 0 'const' 0 'const+93.75ps' VDD)

Vin3 reset gnd! pulse (0V 0V 0ps 93.75ps 93.75ps 1406ps 3000ps)


.meas tsetup trig v(d) val=0.6 rise=1

+targ v(clk) val=0.6 fall=2

.meas tclktoq trig v(clk) val=0.6 fall=2

+targ v(q) val=0.6 rise=1

.tran 0.001ns 10ns sweep const 4400ps 4500ps 1ps

.end

0.00E+00

5.00E-11

1.00E-10

1.50E-10

2.00E-10

2.50E-10

3.00E-10

0.00E+00 2.00E-11 4.00E-11 6.00E-11 8.00E-11 1.00E-10 1.20E-10

de

lay

tim

e (

s)

setup time (s)

passing 0

28

Passing “1”

waveforms showing different setup time for ‘D’

Setup vs Delay time (passing “1”)

2.20E-10

2.30E-10

2.40E-10

2.50E-10

2.60E-10

2.70E-10

2.80E-10

0.00E+00 2.00E-11 4.00E-11 6.00E-11 8.00E-11 1.00E-10 1.20E-10

de

lay

tim

e (

s)

setup time (s)

passing 1

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D flip flop Times

Passing ‘0’ Passing ‘1’

Tsu_dd = 9.75E-12 s 1.78E-11 s

Tsu_opt = 2.58E-11 s 2.32E-11 s

Thold = 2.32E-11 s 2.58E-11s

Tclk->q = 1.98E-10 s 1.95E-10 s

tD = 2.23E-10 s 2.31E-10 s

Sizing information

Height = 8.790 um

Width = 11.84 um

30

Tradeoffs

The sizes of the cells are not the minimum possible values so as

to assert the symmetry in the overall design.

The functionality of the ALU has been limited so as to reduce the

complexity of the entire system and make it easily decipherable

in case of any error.

31

Function

The function of the ALU is to perform the arithmetic and logical

operations (arithmetic operations: addition, subtraction and

multiplication; logical operations : AND, OR, XNOR, left shift and

right shift) when it’s fed with the necessary inputs.

All these functions are developed from the cell library which was

developed using CADENCE. The functionality of each individual

block was verified before it was placed together in the ALU.

32

Scope

The area of the entire unit can be reduced which will also impact

the power performance and transient time dependent

characteristics.

Complex operations can be added and new cells can be developed

so as to help performing those operations.

33

ALU Output Waveforms

34

FINAL LAYOUT

FINAL SCHEMATIC

35

Final layout, LVS & DRC Reports

36

37

PRIMETIME REPORT

set search_path "* ~/EECT6325/cad/primetime" * ~/EECT6325/cad/primetime source variables1 R ############################################################### # link library ############################################################### set link_library $library_file finalproj.db set target_library $library_file finalproj.db #set link_library [list $library_file "ff.db"] #set target_library [list $library_file "ff.db"] ############################################################### # link design ############################################################### remove_design -all Error: Nothing matched for designs: there are none loaded (SEL-005) 0 read_verilog $verilog_file Loading verilog file '/home/eng/a/axn131030/EECT6325/cad/primetime/newALUfinal_syn.v' 1 ############################################################### # Define IO parameters ############################################################### set_driving_cell -lib_cell $driving_cell -input_transition_rise $input_transition -input_transition_fall $input_transition [all_inputs] Loading db file '/home/eng/a/axn131030/EECT6325/cad/primetime/finalproj.db' Linking design alumod_1... Information: 1 (12.50%) library cells are unused in library lib_all..... Information: total 1 library cells are unused. Information: Issuing set_operating_conditions for setting analysis mode on_chip_variation. (PTE-037) set_operating_conditions -analysis_type on_chip_variation -library [get_libs {finalproj.db:lib_all}] 1 set_load $load [all_outputs] 1

############################################################### ############################################################### #define the clock - for comb circuit we may not need to use any clock ############################################################### create_clock -name clk -period $clock_period [get_ports $clock_pin_name] 1 set_clock_transition -rise -max $input_transition [get_clocks clk] 1 set_clock_transition -fall -max $input_transition [get_clocks clk] 1 #set_ideal_transition –max 50 clk #set_false_path –from R ############################################################### # set condition ############################################################### set timing_slew_propagation_mode worst_slew worst_slew set timing_report_unconstrained_paths true true set power_enable_analysis true true set_disable_timing [get_ports $reset_pin_name] Warning: No port objects matched 'R' (SEL-004) Error: Nothing matched for ports (SEL-005) Error: Nothing matched for object_list (SEL-005) 0

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############################################################### # analyze delay and power ############################################################### check_timing Warning: Some timing arcs have been disabled for breaking timing loops or because of constant propagation. Use the 'report_disable_timing' command to get the list of these disabled timing arcs. (PTE-003) Information: Checking 'no_input_delay'. Warning: There are 68 ports with no clock-relative input delay specified. Since the variable 'timing_input_port_default_clock' is 'true', a default input port clock will be assumed for these ports. Information: Checking 'no_driving_cell'. Information: Checking 'unconstrained_endpoints'. Warning: There are 32 endpoints which are not constrained for maximum delay. Information: Checking 'unexpandable_clocks'. Information: Checking 'latch_fanout'. Information: Checking 'no_clock'. Information: Checking 'partial_input_delay'. Information: Checking 'generic'. Information: Checking 'loops'. Information: Checking 'generated_clocks'.

Information: Checking 'pulse_clock_non_pulse_clock_merge'. Information: Checking 'pll_configuration'. 0 update_timing 1 report_timing -transition_time -delay min_max -capacitance -input_pins **************************************** Report : timing -path_type full -delay_type min_max -input_pins -max_paths 1 -transition_time -capacitance Design : alumod_1 Version: D-2010.06-SP1 Date : Mon Dec 16 19:57:33 2013 **************************************** Startpoint: x[31] (input port) Endpoint: outp_reg[31] (falling edge-triggered flip-flop clocked by clk') Path Group: clk Path Type: min Point Cap Trans Incr Path ----------------------------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 r x[31] (in) 44.75 81.88 63.10 63.10 r U748/d (AOI22) 81.88 0.00 63.10 r U748/out (AOI22) 5.27 23.91 46.50 109.59 f U743/a (NAND) 23.91 0.00 109.59 f U743/out (NAND) 5.48 20.98 32.32 141.91 r U742/b (NOR) 20.98 0.00 141.91 r U742/out (NOR) 5.37 12.32 23.71 165.62 f U741/a (INVERTER) 12.32 0.00 165.62 f U741/out (INVERTER) 5.60 17.11 23.95 189.57 r outp_reg[31]/D (DFF) 17.11 0.00 189.57 r data arrival time 189.57

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clock clk' (fall edge) 20.00 0.00 0.00 clock network delay (ideal) 0.00 0.00 outp_reg[31]/Clk (DFF) 0.00 f library hold time -10.64 -10.64 data required time -10.64 ----------------------------------------------------------------------------- data required time -10.64 data arrival time -189.57 ----------------------------------------------------------------------------- slack (MET) 200.22 Startpoint: x[1] (input port) Endpoint: outp_reg[31] (falling edge-triggered flip-flop clocked by clk') Path Group: clk Path Type: max Point Cap Trans Incr Path ----------------------------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 input external delay 0.00 0.00 r

x[1] (in) 185.10 315.57 259.75 259.75 r U4948/a (NAND) 315.57 0.00 259.75 r U4948/out (NAND) 10.07 73.83 74.37 334.12 f U4946/a (NOR) 73.83 0.00 334.12 f U4946/out (NOR) 21.30 92.92 115.07 449.19 r U4945/a (INVERTER) 92.92 0.00 449.19 r U4945/out (INVERTER) 10.32 30.88 39.26 488.45 f U4943/a (NAND) 30.88 0.00 488.45 f U4943/out (NAND) 11.54 33.08 44.36 532.81 r U4942/a (INVERTER) 33.08 0.00 532.81 r U4942/out (INVERTER) 14.97 21.57 33.01 565.82 f U4941/b (XOR) 21.57 0.00 565.82 f U4941/out (XOR) 10.45 35.95 93.09 658.91 f U4940/a (INVERTER) 35.95 0.00 658.91 f U4940/out (INVERTER) 15.53 36.06 50.27 709.18 r U4911/b (NAND) 36.06 0.00 709.18 r U4911/out (NAND) 5.24 31.32 33.67 742.84 f U4909/a (AOI22) 31.32 0.00 742.84 f U4909/out (AOI22) 20.98 86.17 102.93 845.77 r U4908/b (XOR) 86.17 0.00 845.77 r U4908/out (XOR) 9.07 65.47 109.71 955.48 r U4893/a (XOR) 65.47 0.00 955.48 r U4893/out (XOR) 21.30 102.24 139.40 1094.88 r U4853/b (NAND) 102.24 0.00 1094.88 r U4853/out (NAND) 5.24 31.33 44.06 1138.94 f U4850/a (AOI22) 31.33 0.00 1138.94 f U4850/out (AOI22) 20.98 85.90 102.93 1241.87 r U4849/b (XOR) 85.90 0.00 1241.87 r U4849/out (XOR) 9.07 65.17 109.66 1351.53 r U4818/a (XOR) 65.17 0.00 1351.53 r U4818/out (XOR) 21.02 101.25 138.60 1490.13 r U4817/b (NOR) 101.25 0.00 1490.13 r U4817/out (NOR) 5.37 30.87 39.69 1529.81 f U4816/a (INVERTER) 30.87 0.00 1529.81 f U4816/out (INVERTER) 5.26 20.71 32.07 1561.89 r U4814/a (AOI22) 20.71 0.00 1561.89 r U4814/out (AOI22) 20.33 56.07 64.96 1626.84 f U4813/b (XOR) 56.07 0.00 1626.84 f U4813/out (XOR) 8.80 33.91 102.79 1729.63 f U4769/a (XOR) 33.91 0.00 1729.63 f U4769/out (XOR) 19.21 49.88 98.26 1827.90 f U4644/b (NOR) 49.88 0.00 1827.90 f U4644/out (NOR) 5.77 41.65 65.55 1893.45 r

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U4643/a (INVERTER) 41.65 0.00 1893.45 r U4643/out (INVERTER) 5.24 16.45 23.86 1917.31 f U4642/a (AOI22) 16.45 0.00 1917.31 f U4642/out (AOI22) 20.98 85.64 95.90 2013.21 r U4641/b (XOR) 85.64 0.00 2013.21 r U4641/out (XOR) 9.07 66.24 109.60 2122.82 r U4581/a (XOR) 66.24 0.00 2122.82 r U4581/out (XOR) 20.33 99.07 136.81 2259.63 r U4580/b (NOR) 99.07 0.00 2259.63 r U4580/out (NOR) 5.37 30.52 39.47 2299.09 f U4579/a (INVERTER) 30.52 0.00 2299.09 f U4579/out (INVERTER) 5.26 20.61 31.94 2331.03 r U4577/a (AOI22) 20.61 0.00 2331.03 r U4577/out (AOI22) 20.33 55.56 64.91 2395.94 f U4576/b (XOR) 55.56 0.00 2395.94 f U4576/out (XOR) 8.80 33.85 102.65 2498.60 f U4502/a (XOR) 33.85 0.00 2498.60 f U4502/out (XOR) 19.21 49.88 98.24 2596.83 f U4321/b (NOR) 49.88 0.00 2596.83 f U4321/out (NOR) 5.77 41.65 65.55 2662.39 r U4320/a (INVERTER) 41.65 0.00 2662.39 r U4320/out (INVERTER) 5.24 16.45 23.86 2686.25 f U4319/a (AOI22) 16.45 0.00 2686.25 f

U4319/out (AOI22) 20.98 85.29 95.90 2782.15 r U4318/b (XOR) 85.29 0.00 2782.15 r U4318/out (XOR) 9.07 64.16 109.54 2891.68 r U4230/a (XOR) 64.16 0.00 2891.68 r U4230/out (XOR) 20.33 99.07 136.53 3028.22 r U4229/b (NOR) 99.07 0.00 3028.22 r U4229/out (NOR) 5.37 30.52 39.47 3067.69 f U4228/a (INVERTER) 30.52 0.00 3067.69 f U4228/out (INVERTER) 5.26 20.61 31.94 3099.62 r U4226/a (AOI22) 20.61 0.00 3099.62 r U4226/out (AOI22) 20.33 55.56 64.91 3164.54 f U4225/b (XOR) 55.56 0.00 3164.54 f U4225/out (XOR) 8.80 33.78 102.66 3267.19 f U4123/a (XOR) 33.78 0.00 3267.19 f U4123/out (XOR) 19.21 49.88 98.20 3365.39 f U3885/b (NOR) 49.88 0.00 3365.39 f U3885/out (NOR) 5.77 41.65 65.55 3430.95 r U3884/a (INVERTER) 41.65 0.00 3430.95 r U3884/out (INVERTER) 5.24 16.45 23.86 3454.81 f U3883/a (AOI22) 16.45 0.00 3454.81 f U3883/out (AOI22) 20.98 84.85 95.90 3550.71 r U3882/b (XOR) 84.85 0.00 3550.71 r U3882/out (XOR) 9.07 64.18 109.45 3660.16 r U3766/a (XOR) 64.18 0.00 3660.16 r U3766/out (XOR) 20.33 99.07 136.54 3796.70 r U3765/b (NOR) 99.07 0.00 3796.70 r U3765/out (NOR) 5.37 30.52 39.47 3836.16 f U3764/a (INVERTER) 30.52 0.00 3836.16 f U3764/out (INVERTER) 5.26 20.61 31.94 3868.10 r U3762/a (AOI22) 20.61 0.00 3868.10 r U3762/out (AOI22) 20.33 55.83 64.91 3933.01 f U3761/b (XOR) 55.83 0.00 3933.01 f U3761/out (XOR) 8.80 33.76 102.73 4035.74 f U3631/a (XOR) 33.76 0.00 4035.74 f U3631/out (XOR) 19.21 49.88 98.19 4133.94 f U3337/b (NOR) 49.88 0.00 4133.94 f U3337/out (NOR) 5.77 41.65 65.55 4199.49 r U3336/a (INVERTER) 41.65 0.00 4199.49 r U3336/out (INVERTER) 5.24 16.45 23.86 4223.35 f U3335/a (AOI22) 16.45 0.00 4223.35 f U3335/out (AOI22) 20.98 85.04 95.90 4319.25 r U3334/b (XOR) 85.04 0.00 4319.25 r U3334/out (XOR) 9.07 64.29 109.49 4428.74 r

41

U3190/a (XOR) 64.29 0.00 4428.74 r U3190/out (XOR) 20.33 99.07 136.55 4565.29 r U3189/b (NOR) 99.07 0.00 4565.29 r U3189/out (NOR) 5.37 30.52 39.47 4604.76 f U3188/a (INVERTER) 30.52 0.00 4604.76 f U3188/out (INVERTER) 5.26 20.61 31.94 4636.70 r U3186/a (AOI22) 20.61 0.00 4636.70 r U3186/out (AOI22) 20.33 56.60 64.91 4701.61 f U3185/b (XOR) 56.60 0.00 4701.61 f U3185/out (XOR) 8.80 34.52 102.93 4804.54 f U3027/a (XOR) 34.52 0.00 4804.54 f U3027/out (XOR) 19.21 49.88 98.53 4903.07 f U2675/b (NOR) 49.88 0.00 4903.07 f U2675/out (NOR) 5.77 41.65 65.55 4968.63 r U2674/a (INVERTER) 41.65 0.00 4968.63 r U2674/out (INVERTER) 5.24 16.45 23.86 4992.49 f U2673/a (AOI22) 16.45 0.00 4992.49 f U2673/out (AOI22) 15.54 72.71 84.04 5076.53 r U2672/b (XOR) 72.71 0.00 5076.53 r U2672/out (XOR) 9.07 63.25 107.07 5183.60 r U2499/a (XOR) 63.25 0.00 5183.60 r U2499/out (XOR) 20.60 99.87 137.18 5320.77 r U2498/b (NAND) 99.87 0.00 5320.77 r

U2498/out (NAND) 5.24 29.51 43.89 5364.66 f U2494/a (AOI22) 29.51 0.00 5364.66 f U2494/out (AOI22) 15.54 72.52 90.14 5454.80 r U1519/a (INVERTER) 72.52 0.00 5454.80 r U1519/out (INVERTER) 9.84 26.52 35.48 5490.28 f U1518/a (NOR) 26.52 0.00 5490.28 f U1518/out (NOR) 5.77 41.83 49.62 5539.89 r U1517/a (INVERTER) 41.83 0.00 5539.89 r U1517/out (INVERTER) 5.24 16.49 23.90 5563.79 f U1516/a (AOI22) 16.49 0.00 5563.79 f U1516/out (AOI22) 20.98 85.20 95.92 5659.71 r U1515/b (XOR) 85.20 0.00 5659.71 r U1515/out (XOR) 9.07 64.34 109.52 5769.23 r U1321/a (XOR) 64.34 0.00 5769.23 r U1321/out (XOR) 14.33 79.66 119.89 5889.12 r U930/a (AOI22) 79.66 0.00 5889.12 r U930/out (AOI22) 9.70 47.26 72.68 5961.80 f U929/b (XOR) 47.26 0.00 5961.80 f U929/out (XOR) 8.80 32.70 100.23 6062.03 f U924/a (XOR) 32.70 0.00 6062.03 f U924/out (XOR) 8.80 33.17 87.35 6149.37 f U751/a (XOR) 33.17 0.00 6149.37 f U751/out (XOR) 5.05 28.51 83.51 6232.88 f U750/d (AOI22) 28.51 0.00 6232.88 f U750/out (AOI22) 5.76 46.16 47.34 6280.23 r U749/b (NAND) 46.16 0.00 6280.23 r U749/out (NAND) 4.79 23.44 35.35 6315.57 f U742/a (NOR) 23.44 0.00 6315.57 f U742/out (NOR) 5.77 39.71 48.26 6363.83 r U741/a (INVERTER) 39.71 0.00 6363.83 r U741/out (INVERTER) 5.28 16.07 23.55 6387.38 f outp_reg[31]/D (DFF) 16.07 0.00 6387.38 f data arrival time 6387.38 clock clk' (fall edge) 0.00 6700.00 6700.00 clock network delay (ideal) 0.00 6700.00 outp_reg[31]/Clk (DFF) 6700.00 f library setup time -35.12 6664.88 data required time 6664.88 ----------------------------------------------------------------------------- data required time 6664.88 data arrival time -6387.38 -----------------------------------------------------------------------------

42

slack (MET) 277.50 1 update_power Information: Checked out license 'PrimeTime-PX' (PT-019) Warning: Neither event file or switching activity data present for power estimation. The command will propagate switching activity values for power calculation. (PWR-246) Information: Running averaged power analysis... (PWR-601) 1 report_power **************************************** Report : Averaged Power Design : alumod_1 Version: D-2010.06-SP1 Date : Mon Dec 16 19:57:34 2013 **************************************** Attributes ---------- i - Including register clock pin internal power

u - User defined power group Internal Switching Leakage Total Power Group Power Power Power Power ( %) Attrs -------------------------------------------------------------------------------- io_pad 0.0000 0.0000 0.0000 0.0000 ( 0.00%) memory 0.0000 0.0000 0.0000 0.0000 ( 0.00%) black_box 0.0000 0.0000 0.0000 0.0000 ( 0.00%) clock_network 3.425e-04 4.095e-05 8.268e-10 3.834e-04 (12.15%) i register 1.720e-05 2.776e-06 3.034e-07 2.028e-05 ( 0.64%) combinational 1.318e-03 1.428e-03 5.748e-06 2.752e-03 (87.21%) sequential 0.0000 0.0000 0.0000 0.0000 ( 0.00%) Net Switching Power = 1.472e-03 (46.65%) Cell Internal Power = 1.678e-03 (53.16%) Cell Leakage Power = 6.052e-06 ( 0.19%) --------- Total Power = 3.156e-03 (100.00%)

Engineering

VLSI Design Final Project - 32 bit ALU