Design and implementation of 32 bit alu using verilog

DESIGN AND IMPLEMENTATION OF 32-BIT ALU USING

VERILOG

A.Athihrii -12UEC001

M Stephen -12UEC016

Sanjay Kumar -12UEC020

(i)

DESIGN AND IMPLEMENTATION OF 32-BIT ALU USING

VERILOG

Report submitted to

National Institute of Technology Manipur

for the award of the degree

of

Bachelor of Technology in Electronics and communication Engineering

by

A.Athihrii (12UEC001)

M. Stephen (12UEC016)

Sanjay kumar(12UEC020)

Under the guidance of Shri MANOJ KUMAR

Assistant Professor, NIT Manipur

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

NATIONAL INSTITUTE OF TECHNOLOGY MANIPUR

MAY 2016

© 2016, Athihrii, Stephen, Sanjay. All rights reserved

(ii)

DECLARATION

We certify that

a. the work contained in this report is original and has been done by me under the

guidance of my supervisor(s).

b. the work has not been submitted to any other Institute for any degree or diploma.

c. I have followed the guidelines provided by the Institute in preparing the report.

d. I have conformed to the norms and guidelines given in the Ethical Code of Conduct

of the Institute.

e. whenever I have used materials (data, theoretical analysis, figures, and text) from

other sources, I have given due credit to them by citing them in the text of the report

and giving their details in the references. Further, I have taken permission from the

copyright owners of the sources, whenever necessary. Signature of the Student

Signature of the Student

……………………………….

……………………………….

……………………………….

(v)

ACKNOWLEDGEMENT

It gives us immense pleasure to express our heartfelt gratitude and sincere thanks to our

project mentor Shri. Manoj Kumar (Assistant Professor, Electronics And Communication

Engineering) for his timeless and valuable contribution, suggestion and encouragement for

the completion of this project. His continuous guidance had led us to execute our project

titled “DESIGN AND IMPLEMENTATION OF 32-BIT ALU USING VERILOG”.

We are deeply indebted to you Sir.

A. ATHIHRII(12UEC001)

M. STEPHEN (12UEC016)

SANJAY KUMAR(12UEC020)

(vi)

ABSTRACT

In this fast growing booming technology, the need for high-tech and superfast technology is

on high demand. Hence through the use of FPGA (Field Programmable Gate Array) we can

design superfast technology especially in the field of embedded system.

Verilog standardized as IEEE 1364 is a hardware description language(HDL), a textual

format for describing electronics design and circuits. Applied to electronic design, verilog is

intended to used for verification through simulation, for timing analysis, for test analysis

(testability analysis and fault grading) and for logic synthesis.

An Arithmetic Logic Unit (ALU) is a digital electronic circuits that performs arithmetic and

bitwise logical operations on integer binary numbers. This is in contrast to FPU(Floating

point unit )which operates on floating point numbers. ALU is a fundamental building block of

many type of computing circuits including the central processing unit (CPU), FPU and GPU

(Graphics Processing Unit).A single CP, FPU and GPU may contain multiple ALUs.

(vii)

CONTENTS

TITLE Page NO.

Title page i

Certificate iii

Certificate iv

Declaration v

Acknowledgement vi

Abstract vii

Contents viii

List of Figures xi

List of table xii

CHAPTER-1 INTRODUCTION AND LITERATURE REVIEW 1 - 5

1.1 HDL (Hardware Description language) 1

1.2 Typical Design Flow 3

1.3 Literature review 4

CHAPTER-2 INTRODUCTION TO VERILOG AND XILINX 6 - 10

2.1 Verilog 6

2.2 Xilinx 8

2.2.1 Procedure to Operate Xilinx (ISE 14.7) 9

2.3 Tools and Enviroment Used 10

2.3.1 Minimum Hardware Requirement 10

2.3.2 Minimum Software Requirement 10

(viii)

CHAPTER-3 DESIGN OF ALU 11-19

3.1 Arithmetic Unit 11

3.2 Logic Unit 14

3.3 Shift unit 15

3.3.1 Left Shift 15

3.3.2 Right Shift 16

3.4 Arithmetic Logic Unit 17

CHAPTER-4 VERILOG CODING AND WAVEFORM 20 – 47

4.1 Selection MUX 4 to 1 (1 bit I/O) 20

4.2 Selection MUX 4 to 1 (32-bit I/O) 21

4.3 Selection MUX 2 to 1 (32-bit I/O) 21

4.4 Full adder 22

4.5 4-bit Adder 22

4.6 32-bit Adder 23

4.7 32-bit AND 23

4.8 32-bit OR 23

4.9 32-bit XOR 24

4.10 32-bit NOT 24

4.11 Right shift 24

4.12 Left shift 25

4.13 Shift unit 25

(ix)

4.14 Arithmetic unit 26

4.15 Logic unit 30

4.16 32-bit ALU 32

4.17 Test Bench for 32-bit ALU 40

CHAPTER-5 ADVANTAGE AND CONCLUSION 48 - 52

5.1 Importance of HDL 48

5.2 Advantage of Verilog HDL 48

5.3 Conclusion 49

5.4 Future scope of Verilog 50

5.4.1 Design process 50

5.4.2 System Level 51

5.4.3 Digital 51

5.4.4 Analog 51

5.4.5 Debugging 52

REFERENCES 53

(x)

LIST OF FIGURES

1.1 TYPICAL DESIGN FLOW 3

2.2 Xilinx ISE Interface 9

3.1 32-bit Arithmetic unit 13

3.2 32-bit Logic unit 14

3.3.1 (a) 32-bit before Left Shift 15

(b) 32-bit after Left Shift 16

3.3.2 (a) 32-bit before Right Shift 16

(b) 32-bit after Right 16

3.3.3 32-bit Shift unit 17

3.4 Arithmetic Logic Unit 19

4.1 RTL of 32-bit ALU 44

4.2 4 to 1 32-bit Waveform 45

4.3 32-bit Arithmetic Unit Waveform 45

4.4 32-bit Logic Unit waveform 46

4.5 32-bit Shift unit Waveform 46

4.6 32-bit Arithmetic Logic unit Waveform 47

5.4.1 Design process 50

(xi)

LIST OF TABLE

Table 1. Table of 32-bit Arithmetic unit 12

Table 2. Table of 32-bit Logic uni 15

Table 3. Table of 32-bit Shift unit 17

Table 4. Table of 32-bit Arithmetic Logic unit 19

(xii)

This is to certify that the dissertation entitled

“Design and Implementation of 32-bit ALU using Verilog”

to the National Institute of Technology Manipur, India, is a record of

bonafied project work carried out under my supervision and guidance and is

worthy of consideration for the award of the degree of Bachelor of

Technology in Electronics and Communication Engineering of the Institute.

Signature of Guide

(Shri.Manoj Kumar)

(iii)

Department of Electronics and Communication Engineering

Takyelpat, Imphal- 795001, Ph.:0385-2445812, email:

Ref no.: NITMN/ECE:4/B.TECH/ ...... Dated.........

This is to certify that the Dissertation Report entitled,

submitted by Mr.“A.Athihrii,

M. Stephen, Sanjay Kumar” to National Institute of Technology Manpur,

India, is a record of bonafide Project work carried out by them under the

supervision and guidance of Shri. Manoj Kumar (Assistant Professor, NIT

Manipur) and is worthy of consideration for the award of the degree of Bachelor

of Technology in Electronics and Communication Engineering of the Institute.

HOD, ECE Department

NIT MANIPUR

(iv)

Department of Electronics and Communication Engineering ©Athihrii, Stephen, Sanjay 2016 Page 1

Design and implementation of 32-bit ALU using Verilog 2016

Chapter 1

INTRODUCTION AND LITERATURE REVIEW

Digital circuit design has evolved rapidly, the earliest digital circuits were designed with

vacuum tubes and transistors. With the advent of VLSI (Very Large Scale Integration)

technology, designers could design single chip with more than 100,000 transistors.

Because of the complexity of these circuits, it was not possible to verify these circuits on

a breadboard. Computer aided techniques became critical for verification and design of

VLSI digital circuits. Computer programs to do automatic placement and routing of

circuit layout also became popular. The designers were now building gate level digital

circuits manually on graphic terminals. They would build small building blocks and then

derive higher level blocks from them. This process would continue until they had built

the top-level block. Logic simulator came into existence to verify the functionality of

these circuits before they were fabricated on chip.

1.1 HDL (Hardware Description Language)

Hardware Description Language [1] came into existence to replace programming

language such as FORTAN, Pascal and C as a standard language to describe digital

circuit. HDL is a specialized computer language used to describe the structure and

behaviour of electronic circuit, and most commonly digital logic circuit.

There are two types of HDL:

1. Verilog HDL

2. VHDL (VHSIC Hardware Description Language)



The advent of logic synthesis in the late 1980s changed the design methodology radically.

Digital circuit could be described at RTL (Register Transfer Level) by use of an HDL.

Thus, the designer had to specify how the data flow between register and how the design

processes the data. The detail of gates and their interconnections to implement the circuits

were automatically extracted by logic synthesis tools from RTL descriptions

HDL also began to use for system-level design. HDLs were used for simulation of system

boards; interconnect buses, FPGA (Field Programmable Gate Array) and PALs

(Programmable Array Logic). A common approach is to design each IC chip, using an

HDL, and then verify system functionality via simulation.

Verilog HDL originates in 1983 at Gateway Design Automation. Later, VHDL was

developed under contract from DARPA. Both Verilog and VHDL simulators to simulate

large digital circuit quickly gain acceptance from designers. Verilog is a Hardware

Description Language, a textual format for describing electronic circuits and systems.

Applied to electronic design, Verilog is intended to be used for verification through

simulation, for timing analysis, for test analysis (testability analysis and fault grading)

and for logic synthesis.



1.2 TYPICAL DESIGN FLOW

A typical design flow for designing VLSI IC circuits is shown in figure 1.1.Unshaded

blocks show the level of design representation [1] ;shaded blocks show processes in the

design flow;

Fig. 1.1 Typical Design Flow

Behavioural Description

RTL Description (HDL)

Functional Verification and

Testing

Logic synthesis

Gate-Level Netlist

Logical Verification and

Testing

Floor planning, Automatic

Place and Route

Physical Layout

Layout Verification

Implementation

Design specification



1.3 LITERATURE REVIEW

The general idea of this particular project is to compile 32–bits logic gates, shift gates and

arithmetic operation into one single MUX to carry out the desire operation successfully.

1. In ‗Verilog HDL, A guide to digital Design and Synthesis’ [1], the book

imparts the working knowledge of a broad variety of Verilog-based topics, thus

giving the reader a global understanding of Verilog HDL-based design. The book

leaves the in-depth coverage of each topic to the Verilog HDL language reference

manual and the reference manuals of the individual Verilog-based products.

2. In ‗The Verilog Hardware Description language‘ [2], it focus on tutorial

approach to presenting the language. It continues with a more complete discussion

of the language constructs. Numerous example are also provided to allow the

reader to make it more easy to learn through examples. The rest of the book could

be used in upper level logic design and architecture courses

3. In ‗A Verilog HDL Primer‘ [3][4], It is a practical and useful guide to Verilog

HDL register-transfer level synthesis. A large number of synthesizable Verilog

HDL examples are provided. Verilog HDL constructs that are supported for

synthesis are described in detail. Common causes of functional mismatches

between the design model and the synthesized netlist are described in detail and

recommendations are make on how to avoid this.

4. In ‗Verifiable RTL Design: A Functional Coding Style Supporting

Verification Processes in Verilog‘ [5] and ‗IEEE Std 1364-2001 : IEEE Standard

Hardware Description Language based on the Verilog Hardware Description

Language Published by the IEEE, Inc., http://www.ieee.org 345 East 47th Street,

New York, NY 10017, USA‘ [6], mostly introduce a verifiable subset of Verilog

and a simple RTL coding style. It enabled us to effectively incorporate these new

verification technologies into our design flow. To provide a framework for

discussion, it place emphasis on describing verification processes throughout the



text-as opposed to an in-depth discussion of the Verilog language. This book tells

how you can write Verilog to describe chip designs at the RT-level in a manner

that cooperates with verification processes. This cooperation can return an order

of magnitude improvement in performance and capacity from tools such as

simulation and equivalence checkers.

5. In the project ‗Design and Implementation of 32-Bit ALU on XILINX FPGA

using VHDL‘ [7] they are designing an 32-bit ALU using VHDL and

implementing on Xilinx FPGA.

6. In the project ‗Implementation of 32-bit Arithmetic Logic Unit on Xilinx using

VHDL‘ [8] the are implemeting the 32-bit ALU code on Xilinx.



Chapter 2

INTRODUCTION TO VERILOG AND XILINX

2.1 Verilog

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to

model electronic systems. It is most commonly used in the design and verification of

digital circuits at the register-transfer level of abstraction. Verilog HDL has become an

industry standard as a result of extensive used in the design of IC chips and digital

systems. Verilog came into being as a proprietary language supported by a simulation

environment that was the first to support by a simulation environment that was the first to

support mixed-level design representations comprising switches, gates, RTL and higher

levels of abstractions of digital circuits. The simulation environment provided a powerful

and uniform method to express digital designs as well as tests that were meant to verify

such designs.

There were three key factors that drove the acceptance and dominance of Verilog in the

marketplace. First, introduction of Programming Language Interface (PLI) permitted

users of Verilog to literally extend and customized the simulation environment. Since

then users have exploited the introduction of Verilog-based synthesis technology by

Synopsys. The combination of the simulation and synthesis technologies serve to make

Verilog the language of choice for PLI and their success at adapting Verilog to their

environments has been a real winner for Verilog. The Second key factor which drove

Verilog‘s dominance came from Gateways paying close attention to the needs of the

ASIC foundries and enhancing Verilog in close partnership with Motorola, National and

UTMC.The realisation that the vast majority of logic simulation was being done by



designers of ASIC chips drove this effort. The third key factor behind the success was the

the hardware designers.

Verilog also provide the concept of a module. A module is the basic building block in

verilog. A module can be an element or a collection of lower-level design block. A

module provides the necessary functionality to the higher level block through its port

interface (inputs and outputs), but hides the internal implementation. This allows the

designer to modify module internals without affecting the rest of the design.

Verilog is both a behavioural and structural language[1]. Internals of each module can be

defined at four level of abstraction. The levels are defined below.

i. Behavioural or algorithmic level

This is the highest level of abstraction provided by verilog HDL. A module can be

implemented in terms of the desired design algorithm without concern for the hardware

implementation details.

ii. Data flow

At this level the module is designed by specifying the data flow. The designer is aware

of how data flows between hardware registers and how the data is processed in the

design.

iii. Gate level

The module is implemented in terms of logic gates and interconnection between these

gates. Design at this level is similar to describing a design in terms of a gate level logic

diagram.



iv. Switch level

This is the lowest level of abstraction provided by verilog. A module can be implemneted

in terms of switches, storage nodes and the interconnection between them.

Verilog allows a designer to mix and match all four levels of abstraction in a design. In

the digital design community, the term Register Transfer Level (RTL) is frequently used

for a verilog description that uses a combination of behavioural and data flow constructs

and is acceptable to logic synthesis tools.

2.2 Xilinx

Xilinx is an American technology company, primarily a supplier of programmable logic

devices and the first semi-conductor company with a fabulous manufacturing model.

Founded in Silicon valley in 1984 and head quartered in San Jose, California, USA, the

company has cooperate offices throughout North America and Europe

Xilinx ISE (Integrated Software environment) is a software tool produced by xilinx for

synthesis and analysis of HDL designs, enabling the developer to synthesize their

designs, perform timing analysis, examine RTL diagrams, simulate a design‘s reaction to

different stimuli and configure the target device with a programmer.



2.2.1 Procedure to operate Xilinx. (ISE 14.7)

1. Open the Xilinx project Navigator

2. Following are the main areas of the Project Navigator, which are shown in the

following figure:

Toolbar - provides convenient access to frequently used menu commands.

Design panel - provides access to the following areas:

o Design View - allows you to select a design phase from the ―Sources for‖

area, which controls the sources files displayed in the Hierarchy pane.

o Hierarchy pane - allows you to view and manage design source files.

o Processes pane - allows you to run processes, which move the design

from design creation through programming the device. In addition, you

can run processes that allow you to analyze and improve your design.

Workspace - allows you to view and edit your design using various tools, and

provides access to reports in the Design Summary.

Transcript window - allows you to view output log, messages, errors, and

warning information as it is generated.

Fig2.2 Xilinx ISE Interface



2.3 Tools and Environment Used

2.3.1 Minimum Hardware Requirement:

1. Computer : IBM or Compatible

2. Hard disk : 20 GB or higher

3. Processor : PENTIUM– IV 2 GHz or above

4. Ram : 512 Mb and above

5. VDU : VGA

2.3.2 Minimum Software Requirement:

1. Operating System : Windows XP

2. Development Software : Xilinx ISE 8.2i



Chapter 3

DESIGN OF ALU

Designing of the ALU will follow the principle "Divide and Conquer" in order to use a

modular design that consists of smaller, more manageable blocks, some of which can be

re-used.

An ALU consists of 3 units:

1. Arithmetic unit: Consists of addition, subtraction, addition with carry

subtraction with borrow, increment, decrement and transfer.

2. Logic Unit: Consists of AND gate, OR gate, NOT gate and XOR gate.

3. Shift Unit: Consists of left shift, right shift.

3.1 Arithmetic unit

An Arithmetic unit does the following task: Addition, Addition with carry, Subtraction,

Subtraction with borrow, Decrement, Increment and Transfer function. As the input is

given in 32-bit, we get 32-bit output. The arithmetic will show only one output at a time ,

so a selector is necessary to select one of the operator.

In this case, we use 8:1 multiplexer where s2, s1,s0 are selector lines, A and B is the

input to be given and Y is the output. Function Table for Arithmetic is shown in table 1.

When s2s1s0= 000:

then Y = A+B i.e. Addition.



When s2s1s0= 001:

then RESULT= A-B i.e. Subtraction.

When s2s1s0= 010:

then RESULT= A+B+1 i.e. Addition with carry

When s2s1s0= 011:

then RESULT= A+(~B) i.e. Subtraction with borrow.

When s2s1s0= 100:

then RESULT= A+1 i.e. Increment.

When s2s1s0= 101:

then RESULT= A-1 i.e. decrement.

When s2s1s0= 110:

then RESULT= A i.e. Transfer.

Table 1. Table of 32-bit Arithmetic Unit



Fig 3.1. 32-bit Arithmetic unit

Subtraction with borrow

Increment

Decrement

Transfer

Addition with carry

Subtraction

Addition

8:1 MUX

Y

S2 S1 S0



3.2 Logic Unit

A Logic unit does the following task: Logical AND, Logical OR, Logical XOR and

Logical NOT operation. We will design a logic unit that can perform the four basic logic

Micro operations: OR, AND, XOR and Complement, because from these four micro-

operations, all other logic micro-operations can be derived. A one-stage logic unit for

these four basic micro-operations is shown in the Fig.3.2

Fig. 3.2 32-bit Logic Unit

The logic unit consists of four gates and a 4:1 multiplexer. The outputs of the gates are

applied to the data inputs of the multiplexer. Using to selection lines S0 and S1 one of the

data inputs of the multiplexer is selected as the output. For a logic unit of 32bit, the

output will be of 33-bit with 33th bit to be High-impedance.

The common selection lines are applied to all the stages.

When S1 S0= 00: RESULT= A∙B i.e. AND.

When S1 S0= 01: RESULT= A+B i.e. OR.



When S1 S0= 10: RESULT= A⨁B i.e. XOR.

When S1 S0= 10: RESULT= A i.e. NOT

Table 2 .Table of 32-bit Logic Unit

3.3 Shift Unit

A Shift register is a storage device that used for storage or the transfer of data in the form

of binary numbers. Considering two types of register:

i. Left shift

ii. Right shift

3.3.1 Left Shift

Data is shifted in the left hand direction one bit at a time with each transition of the

clock signal. The data enters the shift register serially from the right hand side and after

32 clock transition the 32-bit register has 32-bit of data . The data is shifted out serially

one bit at a time from the left hand side of the register if clock signal are continuously

applied. The operation of left shit is shown on the figure 3.3.1 (a) and (b)..

(a)

D31 D30 D0 . . . . . . . . . . . . . . . D1 C_in



(b)

Fig. 3.3.1 (a)32-bit before left shift. (b)32-bit after left shift.

3.3.2 Right Shift

The data is shifted in the right hand direction one bit at a time with each transition of the

clock signal. The data enter the shift register serially from the left hand side and after 32

clock transition the 32- bit register has 32-bit of data. The data is shifted out serially one

bit at a time from the right hand side of the register if clock signal are commonly applied

.The operation of right shift is shown on the figure 3.3.2 (a) and (b).

(a)

The contents of a register that has to be shifted first placed onto common bus. The

D30 D29 . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . . D0 C_in D31

. . . . . . . C_in D31 D30 D0 D1 . .. . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . . .. . C_in

-in D0 C_in

D31

D30

D1

D2

. . . . .. . . . . . . . . . . . . . . . . . .

(b)

Fig 3.3.2 (a) 32-bit before right shift .(b) 32- bit after right shift



circuit uses no clock pulse. When the shifting unit is activated, the register is shifted left

or right according to the selection unit. It used only one selector line i,e s1.

For a shift unit of 32- bit, the output will be of 33-bit with 33th bit to be the outgoing bit.

The circuit of shift unit is shown in figure 3.3

Fig 3.3. 32-bit Shift Unit

Table 3. Table of 32-bit Shift Unit

3.4 Arithmetic Logic Unit

The technique used in these is to split ALU into three modules, Arithmetic, Logic and

shift module. Here the arithmetic, logic and shift that define earlier are combined into

ALU with common selection line. The shift micro-operation are often perform in seperate

unit, but sometime the shifter unit made part of overall ALU.

For 32-bit ALU a 33 bit 4:1 MUX is needed. A particular arithmetic or logic or shift

operation is selected according to the selection inputs S4 ,S5,S6 and S7. The final output



of the ALU is determined by the set of multiplexers with selection lines S2 and S3 for

logic and S1 for shift.. The function table for the ALU is shown in the Table. 4. The table

lists 13 micro-operations: 7 for arithmetic, 4 for logic and 2 for shifter unit. For shifter

unit, the selection line S1 is used to select either left or right shift micro-operation.

Table 4. Table of 32-bit Arithmetic Logic Unit



Fig.3.4 Arithmetic Logic Unit



Chapter 4

VERILOG CODING AND WAVEFORM

4.1 Selection MUX 4 to1(1-bit I/O)

module mux4(i0,i1,i2,i3,s0,s1,clk,y);

input i0,i1,i2,i3,s0,s1,clk;

output reg y;

always @(posedge clk)

case({i0,i1,i2,i3,s0,s1})

2'b00:y=i0;

2'b01:y=i1;

2'b10:y=i2;

2'b11:y=i3;

default y=1'bz;

endcase

endmodule




module mux4l (out, i0, i1, i2, i3, s1, S0);

input[31:0] i0, i1, i2, i3;

input s1, S0;

output[31:0] out;

reg[31:0] out;

always @(s1 or S0 or i0 or i1 or i2 or i3)

case ({s1, S0})

2'b00 : out = i0;

2'b01 : out = i1;

2'b10 : out = i2;

2'b11 : out = i3;

default: $display("Invalid control signals");

endcase

endmodule


module mux2l (out, i0, i1, S0);

input[31:0] i0, i1;

input S0;



output[31:0] out;

reg[31:0] out;

always @( S0 or i0 or i1 )

case ({ S0})

1‘b0 : out = i0;

1‘b1 : out = i1;

default: $display("Invalid control signals");

endcase

endmodule

4.4 Full Adder

module fadd1(a,b,s,c,carry);

input a,b,c;

output s,carry;

assign s=a^b^c;

assign carry=a&b+b&c+c&a;

endmodule

4.5 4-Bit Adder

module add(a,b,y);

input [3:0]a,b;



output[3:0] y;

assign y=a+b;

endmodule

4.6 32-Bit Adder

module ader32bit(a,b,y);

input[31:0]a,b;

output [31:0]y;

assign y=a+b;

endmodule

4.7 32-Bit AND

module and32(a,b,y);

input [31:0]a;

input [31:0]b;

output [31:0]y;

assign y=a&b;

endmodule

4.8 32-Bit OR

module or1(a,b,y);

input[31:0]a,b;



output[31:0]y;

assign y=a|b;

endmodule

4.9 32-Bit XOR

module xor32(a,b,y);

input [31:0]a;

input [31:0]b;

output [31:0]y;

assign y=a^b;

endmodule

4.10 32-Bit NOT

module not32(a,y);

input [31:0]a;

output [31:0]y;

assign y=~a;

endmodule

4.11 Right Shift

module rshift(a,b);

input[31:0]a;



output[31:0]b;

assign b=a>>1;

endmodule

4.12 Left Shift

module shift32a(a,b);

input[31:0]a;

output[31:0]b;

assign b=a<<1;

endmodule

4.13 Shift Unit

module shift1(s1,a,cin,result);

input [31:0]a;

input s1,cin;

output reg[31:0]result ;

wire[31:0] w1,w2;

rshift r1(a,w1);

lshift r2(a,w2);

always @(a,s1,cin,w1,w2)

case({s1})



1'b0:result<=w1;

1'b1:result<=w2;

default:result<=1'b0;

endcase

endmodule

module rshift(a,b);

input[31:0] a;

output[31:0] b;

assign b=a>>1;

endmodule

module lshift(a,b);

input [31:0]a;

output [31:0] b;

assign b=a<<1;

endmodule

4.14 Arithmetic Unit

module arith1(a,b,cin,s0,s1,s2, result);

input[31:0] a,b;

input cin;



input s0,s1,s2;

output[31:0] result;

reg[31:0] result;

wire[31:0]w0,w1,w2,w3,w4,w5,w6;

add r1(a,b,w0);

sub r2(a,b,w1);

addwc r3(a,b,cin,w2);

subwb r4(a,b,cin,w3);

inc r5(a,w4);

dec r6(a,w5);

tra r7(a,w6);

always@(a,b,cin,s0,s1,s2,w0,w1,w2,w3,w4,w5,w6)

case ({s2,s1,s0})

3'b000: result<=w0; //addition//

3'b001: result<=w1; //subtraction//

3'b010: result<=w2; //addition with carry//

3'b011: result<=w3; //subtraction with borrow//

3'b100: result<=w4; // increment//

3'b101: result<=w5; //decrement//



3'b110: result<=w6; //transfer//

3'b111: result<=1'bx; //no need //

endcase

endmodule

//add//

module add(a,b,y);

input [31:0]a,b;

output[31:0] y;

assign y=a+b;

endmodule

//sub//

module sub(a,b,y);

input [31:0]a,b;

output[31:0] y;

assign y=a-b;

endmodule

//additiion with carry//

module addwc(a,b,cin,y);

input [31:0]a,b;



input cin;

output [31:0]y;

assign y=a+b+cin;

endmodule

//sub with borrow//

module subwb(a,b,cin,y);

input [31:0]a,b;

input cin;

output [31:0]y;

//output br;

assign y=a+(~b)+cin;

endmodule

//increment//

module inc(a,y);

input[31:0] a;

output[31:0] y;

assign y=a+1;

endmodule

//deredment//



module dec(a,y);

input [31:0]a;

output [31:0]y;

assign y=a-1;

endmodule

//transfer//

module tra(a,y);

input[31:0]a;

output[31:0]y;

assign y=a;

endmodule

4.15 Logic Unit

module logicunit32bit(a,b,s1,s0,result );

input[31:0] a,b;

input s1,s0;

output reg [31:0]result;

wire [31:0]w1,w2,w3,w4;

and1 a1 (a,b,w1);

or1 a2 (a,b,w2);



not1 a3(a,w3);

exor1 a4(a,b,w4);

always @(a,b,s1,s0,w1,w2,w3,w4)

begin

case({s1,s0})

2'b00:result<= w1;

2'b01:result<=w2;

2'b10:result<=w3;

2'b11:result<=w4;

default:result<=1'b0;

endcase

end

endmodule

module and1(c,d,j);

input[31:0] c,d;

output [31:0]j;

assign j=c&d;

endmodule

module or1(c,d,j);



input[31:0] c,d;

output[31:0] j;

assign j=c|d;

endmodule

module not1(c,d);

input[31:0] c;

output [31:0]d;

assign d= ~c;

endmodule

module exor1(c,d,j);

input [31:0]c,d;

output [31:0]j;

assign j=c^d;

endmodule

4.16 32- bit ALU

module alu2(a,b,s2,s3,s1,s0,s4,s5,s6,s7,cin,result );

input[31:0] a,b;

input s2,s3,s1,s0,s4,s5,s6,s7,cin;

output reg[31:0] result;



wire [31:0]w1,w2;

wire[31:0] w3;

wire [31:0]w4,w5,w6,w7,w8,w9,w10;

shift a1(s1,a,cin,w1);

logicunit32bit a2 (a,b,s2,s3,w3);

addcarry a3(a,b,cin,w4,s4,s5,s6,s7);

add a4 (a,b,cin,w5,s4,s5,s6,s7);

sub a5 (a,b,cin,w6,s4,s5,s6,s7 );

subcarry a6 (a,b,cin,w7,s4,s5,s6,s7 );

incremen22 a7 (a,cin,w8,s4,s5,s6,s7);

decremen22 a8 (a,cin,w9,s4,s5,s6,s7);

trd a9 (w10,a,cin,s4,s5,s6,s7);

always @(a,b,w3,s1,s0,cin,s4,w1,w4,w5,w6,w7,w8,w9,w10,s5,s2,s6,s7,s3)

begin

case({s4,s5,s6,s7})

4'b0000:result<= w3;

4'b0001:result<=w1;

4'b0010:result<=w4;

4'b0011:result<=w5;



4'b0100:result<=w6;

4'b0101:result<=w7;

4'b0110:result<=w8;

4'b0111:result<=w9;

4'b1000:result<=w10;

4'b1001:result<=1'bx;







default:result<=1‘b0;

endcase

end

endmodule

module shift(s1,a,cin,res);

input[31:0] a;

input s1,cin;



output reg [31:0]res ;

wire [31:0]w1,w2;

rshift r1(a,w1);

lshift r2(a,w2);

always @(a,s1,w1,w2)

case({s1})

1'b0:res<=w1;

1'b1:res<=w2;

endcase

endmodule

module rshift(a,b);

input[31:0] a;

output[31:0] b;

assign b=a>>1;

endmodule

module lshift(a,b);

input[31:0] a;

output [31:0] b;

assign b=a<<1;



endmodule

module logicunit32bit(a11,b11,s11,s00,res );

input[31:0] a11,b11;

input s11,s00;

output reg[31:0] res;

wire[31:0] w31,w41,w51,w61;

and1 a1 (a11,b11,w31);

or1 a2 (a11,b11,w41);

not11 a3(a11,w51);

exor1 a4(a11,b11,w61);

always @(a11,b11,s11,s00,w31,w41,w51,w61)

begin

case({s11,s00})

2'b00:res<= w31;

2'b01:res<=w41;

2'b10:res<=w51;

2'b11:res<=w61;

default:res<=1‘b0;

endcase



end

endmodule

module and1(c,d,j);

input[31:0] c,d;

output[31:0] j;

assign j=c&d;

endmodule

module or1(c1,d1,j1);

input [31:0]c1,d1;

output [31:0] j1;

assign j1=c1|d1;

endmodule

module not11(c2,d2);

input [31:0]c2;

output [31:0]d2;

assign d2= ~c2;

endmodule

module exor1(c3,d3,j3);

input [31:0]c3,d3;



output[31:0] j3;

assign j3=c3^d3;

endmodule

module add(a,b,cin,y,s4,s5,s6,s7);

input [31:0]a,b;

input cin;

input s4,s5,s6,s7;

output[31:0] y;

assign y=a+b;

endmodule

module addcarry(a,b,cin,y,s4,s5,s6,s7 );

input [31:0]a,b;

input cin;

input s4,s5,s6,s7;

output [31:0]y;

assign y=a+b+cin;

endmodule

module sub(a,b,cin,y,s4,s5,s6,s7 );

input [31:0]a,b;



input s4,s5,s6,s7;

output [31:0]y;

//output br;

input cin;

assign y=a+(~b)+cin;

//assign br=(~a)&b;

endmodule

module subcarry(a,b,cin,y,s4,s5,s6,s7 );

input [31:0]a,b;

input cin;

input s4,s5,s6,s7;

output [31:0]y;

assign y=a+~b+cin;

endmodule

module incremen22(a,cin,y,s4,s5,s6,s7);

input[31:0] a;

input cin;

input s4,s5,s6,s7;

output[31:0] y;



assign y=a+1+cin;

endmodule

module decremen22(a,cin,y,s4,s5,s6,s7);

input [31:0]a;

input cin;

input s4,s5,s6,s7;

output [31:0]y;

assign y=a-1+cin;

endmodule

module trd(y,a ,cin,s4,s5,s6,s7);

input [31:0]a;

input s4,s5,s6,s7;

output [31:0]y;

input cin;

assign y=a+cin;

endmodule

4.17 Test Bench for 32-bit ALU

module test1;

// Inputs



reg [31:0] a;

reg [31:0] b;

reg s2;

reg s3;

reg s1;

reg s0;

reg s4;

reg s5;

reg s6;

reg s7;

reg cin;

// Outputs

wire [31:0] result;

// Instantiate the Unit Under Test (UUT)

alu2 uut (

.a(a),

.b(b),

.s2(s2),

.s3(s3),



.s1(s1),

.s0(s0),

.s4(s4),

.s5(s5),

.s6(s6),

.s7(s7),

.cin(cin),

.result(result)

);

initial begin

// Initialize Inputs

a = 0;

b = 0;

s2 = 0;

s3 = 0;

s1 = 0;

s0 = 0;

s4 = 0;

s5 = 0;



s6 = 0;

s7 = 0;

cin = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

#10 s2=0;s3=0;s1=1'bx;s4=0;s5=0;s6=0;s7=0;cin=1'bx;a=7;b=5;

#10 s4=0;s5=0;s6=0;s7=1;s1=1;s2=1'bx;s3=1'bx;cin=1'bx;a=9;b=1'bx;

#10 s1=1'bx;s4=0;s5=0;s6=0;s7=0;cin=1'bx;a=15;b=1'bx;s2=1;s3=0;

#10 s4=0;s5=1;s6=1;s7=0;a=13;cin=1;b=1'bx;s1=1;s0=1;s3=0;

#10 s4=0;s5=1;s6=1;s7=1;a=14;b=1'bx;cin=0;s1=1;s0=0;s2=0;s3=0;

#10 s4=1;s5=0;s6=0;s7=0;a=10;b=1'bx;cin=0;s1=1;s0=0;s2=0;s3=0;

#10 s4=0;s5=0;s6=0;s7=0;s2=1;s3=1;s1=1;s0=0;a=12;b=6;cin=1'bx;

#10 s4=0;s5=0;s6=0;s7=0;s3=0;s2=1;s1=1;s0=1;cin=1'bx;a=99;b=1'bx;

#10 s2=0;s3=1;s1=1'bx;s4=0;s5=0;s6=0;s7=0;cin=1'bx;a=7;b=5;

#10 s4=0;s5=0;s6=1;s7=1;cin=0;s0=0;s1=0;s2=0;s3=0;a=9;b=6;

#10 s4=0;s5=0;s6=1;s7=0;cin=1;s0=0;s1=0;s2=0;s3=0;a=3;b=5;

#10 s4=0;s5=1;s6=0;s7=0;cin=1;s0=1;s1=0;s2=0;s3=0;a=9;b=5;

#10 s4=0;s5=1;s6=0;s7=1;cin=0;s0=1;s1=0;s2=0;s3=0;a=9;b=5;



#10 s4=0;s5=0;s6=0;s7=1;s3=1;s2=0;s1=0;s0=1'bx;cin=1'bx;a=8;b=1'bx;

end

endmodule

Fig.4.1 RTL of 32-bit ALU



Waveform

Fig 4.2. 4:1 MUX 32-bit Waveform

Fig 4.3. 32-bit Arithmetic unit



Fig 4.4. 32-bit Logic unit

Fig 4.5. 32-bit Shift Unit



Fig 4.6. 32-bit Arithmetic Logic Unit



Chapter 5

ADVANTAGE AND CONCLUSION

5.1 Importance of HDL

HDLs have many advantages compare to traditional schematic-based design.[1]

Designs can be described at a very abstract level by use of HDLs. Designers can

write their RTL description without choosing a specific fabrication technology.

By describing designs in HDLs, functional verification of the design can be done

early in the design cycle. Since designers work at RTL level, they can optimize

and modify the RTL description until it meet the desired functionality. Most

design bugs are eliminated at this point.

Designing with HDLs is analogous to computer programming. A textual

description with comments is an easier way to develop and debug circuits. This

also provides a concise representation of the design, compare to gate level

schematics. Gate level schematics are almost incomprehensible for very complex

designs.

5.2 Advantages of Verilog HDL

Verilog HDL is a general-purpose hardware description language that is easy to

learn and easy to use. It is similar in syntax to the C programing language.

Designers with C programing experience will find it easy to learn Verilog HDL.

Verilog HDL allow different level of abstraction to mixed in the same model.

Thus , a designer can define a hardware model in terms of switches, gates, RTL,



or behavioural codes. Also, a designer needs to learn only one language for

stimulus and hierarchical design.

Most popular logic synthesis tools support Verilog HDL. This makes it the

language of choice for designers .

All fabrication vendors provide Verilog HDL libraries for post logic synthesis

simulation. Thus, designing a chip in Verilog HDL allows the widest choice of

vendors.

The programming language interface (PLI) is a powerful feature that allow s the

user to write custom C code to interact with the internal data structures of Verilog.

Designers can customized a Verilog HDL simulator to their needs with the PLI.

5.3 Conclusion

In our project ―Design and Implementation of a 32-bit ALU using Verilog‖ we have

designed and implemented a 32 bit ALU. Arithmetic Logic Unit is the part of a computer

that performs all arithmetic computations such as addition, subtraction, addition with

carry, subtraction with borrow, increment and decrement ,shifting such as right shift and

left shift and all basic logical operations like AND, OR,NOT and XOR. ALU represents

the fundamental building block of the central processing unit (CPU) of a computer

We have compare the number of MUX with [7],[8] which result in less number of MUX

that we used.



5.4 Future scope of Verilog

Verilog can be used at different levels of abstraction as we have already seen [9]. But

how useful are these different levels of abstraction when it comes to using Verilog?

5.4.1 Design process

The diagram below shows a very simplified view of the electronic system design process

incorporating Verilog. The central portion of the diagram shows the parts of the design

process which will be impacted by Verilog.

System analysis and partitioning

Physical spec H/W spec S/W spec

Analog spec Digital function spec

Verilog

Algorithm

RTL

Gates

Timing analysis

fault simulation

Mixed signal simulation

Layout

Fig.5.4.1 Design Process

Sign off simulation



5.4.2 System Level

Verilog is not ideally suited for abstract system-level simulation, prior to the hardware-

software split. This is to some extent add ressed by SystemVerilog. Unlike VHDL, which

has support for user-defined types and overloaded operators which allow the designer to

abstract his work into the domain of the problem, Verilog restricts the designer to

working with pre-defined system functions and tasks for stochastic simulation and can be

used for modelling performance, throughput and queueing but only in so far as those

built-in language features allow. Designers occasionally use the stochastic level of

abstraction for this phase of the design process.

5.4.3 Digital

Verilog is suitable for use today in the digital hardware design process, from functional

simulation, manual design and logic synthesis down to gate-level simulation. Verilog

tools provide an integrated design environment in this area.

Verilog is also suited for specialized implementation-level design verification tools such

as fault simulation, switch level simulation and worst case timing simulation. Verilog can

be used to simulate gate level fanout loading effects and routing delays through the

import of SDF files.

The RTL level of abstraction is used for functional simulation prior to synthesis. The gate

level of abstraction exists post-synthesis but this level of abstraction is not often created

by the designer, it is a level of abstraction adopted by the EDA tools (synthesis and

timing analysis, for example).

5.4.4 Analog

Because of Verilog's flexibility as a programming language, it has been stretched to

handle analog simulation in limited cases. There is a draft standard – Verilog-AMS – that

addresses analog and mixed signal simulation.



5.4.5 Debugging

Accuracy and time is essential—especially when it comes to your development

simulation and debugging. Our Verilog simulator and compiler will change the way you

can simulate, debug, and manage your development process.

VeriLogger Extreme is a high-performance compiled-code Verilog 2001 simulator with

automatic test bench generation that significantly reduces simulation debug time.

VeriLogger Extreme offers fast simulation of both RTL and gate-level simulations with

SDF timing information. VeriLogger Extreme supports design libraries and design flows

for all major ASIC and FPGA vendors, including Actel/MicroSemi, Altera, Atmel, LSI

Logic, Quick Logic, and Xilinx.



References

[1]. Samir Palnitkar, Verilog HDL, A Guide to digital design and Synthesis.

Published by Prentice Hall PTR, 1996 ISBN 10: 0134516753 / ISBN 13:

9780134516752.

[2]. Donald E. Thomas and Philip R. Moorby, The Verilog Hardware Description

language . Published by Springer; 5th ed. 2002 edition (27 October 2008).

ISBN-10: 0387849300,ISBN-13: 978-0387849300

[3]. J Bhasker, A Verilog HDL Primer . Published by Bs Publications/bsp

Books(2008).

ISBN-10: 817800142X, ISBN-13: 978-8178001425

[4]. Lionel Benning and Harry Foster, Verifiable RTL Design: A Functional Coding Style

Supporting Verification Processes in Verilog. Published by Springer; 2nd ed. 2001

edition (31 May 2001). ISBN-10: 0792373685, ISBN-13: 978-0792373681.

[5]. IEEE Std 1364-2001 : IEEE Standard Hardware Description Language based on the

Verilog Hardware Description Language Published by the IEEE, Inc.,

http://www.ieee.org 345 East 47th Street, New York, NY 10017, USA.

[6]. Douglas J Smith, FPGAs using VHDL or Verilog . Published by Doone Publications.

[7]. Anushka Pakrashi, Arindam Bose, Kausik Bhattacharya, Monigingir Pal, Tanaya

Bose. Design and Implementation of 32-Bit ALU on XILINX FPGA using

VHDL.Institute: FUTURE INSTITUTE OF ENGINEERING AND

MANAGEMENT (2008-2012).



[8]. Anadi Anant Jain, Ankush Bhushan, Bhavyai Gupta, Faizan Ayubi. Implementation

of 32-Bit arithmetic Logic Unit on Xilinx using VHDL. Institute : DELHI

TECHNOLOGICAL UNIVERSITY.

[9]. https://www.doulos.com/knowhow/verilog_designers_guide/scope_of_verilog/