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Analysis and Characterization of Different High Density On-Chip Switched Capacitor
Power Converters in 130nm Technology
Prepared By
Aalay Kapadia (adk130330)
Nishtha Sharma (nxs135730)
05/01/2015
2
Team member contributions
Aalay Kapadia
Auto-Reconfigurable Switched-Capacitor DC-DC Power Converter
Nishtha Sharma
Switched-Capacitor Power Converter with Closed-Loop Interleaving Regulation
05/01/2015
3
Introduction
05/01/2015
•Switched capacitor is one of the DC-DC type converters.
•Similar to the SMPS, a SC converter also consists of two major components.
•Two stages are Power stage (also known as the charge pump) and a closed loop feedback controller (and/or a
feed-forward controller).
•The major benefit of SC power converters ,capability for monolithic integration at low power levels,
•Employs capacitors as energy storage devices, instead of bulky, off-chip inductors.
•One major drawback of traditional SC DC–DC converters is their ability to provide only a single Conversion
Gain (CG).
•To accommodate a large output voltage range and to be capable of powering Dynamic Voltage Frequency
Scaling (DVFS).
• Reconfigurable SC power converters using: Series-Parallel switched capacitor (SPSC) or Sequential
switched capacitor (SQSC).
• SPSC is a reconfigurable SC power converter combined with interleaving technique, which is popular
among the most of the designs.
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Switched Capacitor Power Converters
Block and timing diagrams of the DPWM SPSCResonant Switched Capacitor (ReSC) Converter
Interleaving Regulation and Cross coupled Power Stage Architecture
Structure of the auto-reconfigurable dual-output SC regulator
SCPC With OpportunisticCurrent Borrowing and Fast DVFS Capabilities
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Design focus & innovation
• Main focus -to maximize the power delivered keeping the area as low as possible for the converter.
• Innovation in the converter is that since the capacitor sizes for the five capacitors were decreased by a factor of almost 100 each from the original values proposed in the paper we referred.
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Auto-Reconfigurable Charge Pump Design
• Block level Diagram of schematic of Auto-Reconfigurable SCPC
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Design Components
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Design Components
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Result For Vin=1.2V and RL=1K
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Result For Vin=1.2V and RL=100K
EECT 6379 11
Result For Vin=1.8V and RL=100K
05/01/2015
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Results for 350nm & 130nm
R Iout Vout vexp eff1 100 0.018 1.8 2 0.92 1000 0.00195 2 2 0.9753 10000 0.00018 1.8 2 0.94 100000 0.000019 1.9 2 0.955 1000000 0.0000018 1.8 2 0.9
At 500KHz Frequency and 1.2 V as Vin
Vin Iin Vout Iout pout Vout expected eff1 1.2 0.0025 1.8 0.0042 0.00756 2 0.92 1.32 0.0055 2 0.006 0.012 2.2 0.9090913 1.44 0.0093 2.2 0.0065 0.0143 2.4 0.9166674 1.56 0.014 1.9 0.0076 0.01444 2.6 0.7307695 1.68 0.02275 1.8 0.01 0.018 2.8 0.6428576 1.8 0.02 2 0.0115 0.023 3 0.666667
At 10Kohm resistance and 1MHz switching frequency
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Specifications Auto ReconfigurableTechnology 130nm
Vin 1.2 to 1.8VVout 2-2.5V
Power Effi ciency 65% to 92%Switching Frequency 0.5MHz-1MHz
Load Current < 50mA
Area(mm2) 0.01725
Power Density(Watt/mm2) 0.43826087-1.33333
Results for 350nm & 130nm
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SCPC with closed loop regulation
Somasundaram, MN & Ma, D 2006, 'Low-ripple CMOS switched-capacitor power converter with closed-loop interleaving regulation'. in Proceedings of the Custom Integrated Circuits Conference.
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Gate control signals for each PMOS and NMOS power transistors are generated internally. This avoids the need for additional clock generators and voltage boosting circuits.
SCPC with closed loop regulation
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Cross coupled power stage
Somasundaram, MN & Ma, D 2006, 'Low-ripple CMOS switched-capacitor power converter with closed-loop interleaving regulation'. in Proceedings of the Custom Integrated Circuits Conference.
• Nodes voltages swing between Vin and 2Vin.• Each clock has a phase difference of 90 degrees between each other.
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Output voltage & Output current
Output Voltage=2 V & Output current=3.081 mA
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Simulations for efficiency
Efficiency vs Vin Vout vs Vin vs Iout
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Performance summary
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Performance summary
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Layouts Using Cadence Virtuoso
Design A
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Layouts Using Cadence Virtuoso
Design B
Q/A