POWER EFFICIENT ALU DESIGN WITH CLOCK AND CONTROL-SIGNAL GATING TECHNIQUE

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Int. J. Elec&Electr.Eng&Telecoms. 2015 Anil Kumar Yadav and Mohammed Aneesh Y, 2015

POWER EFFICIENT ALU DESIGN WITH CLOCKAND CONTROL-SIGNAL GATING TECHNIQUE

Anil Kumar Yadav1* and Mohammed Aneesh Y1

*Corresponding Author: Anil Kumar Yadav,[email protected]

To design a low power processor, low power Arithmetic and Logic Unit (ALU) is required, sinceALU is one of the core components and most power hungry sections in a microprocessor thatcarries out the arithmetic and logic operations. Clock gating is the power saving technique usedfor low power design, it switches off the module which is not active as decided by selection line.This techniques is applied in ALU to reduce clock power and dynamic power consumption ofALU. Control signal gating technique provides power saving by reducing unnecessary switchingactivity on datapath buses, when a bus is not going to be used and it will be held in a quiescentstate by stopping the propagation of switching activity through the module(s) driving the bus. Fordesigning a proposed Power Efficient ALU, both the clock gating and the control-signal gatingtechniques are introduced for minimizing the clock power and to reduce the unnecessaryswitching activity of data path. Functionality of proposed ALU is verified by using Xilinx tool andpower analysis is carried out by using Xilinx X’Power analysis tool.

Keywords: Clock gating, Control-signal gating, Data buses, Low power, Switching activity,Dynamic power

INTRODUCTIONPower dissipation is becoming a limitingfactor for high performance microprocessordesign due to ever increasing device countsand clock rates and it continues to grow as animportant challenge in deep submicron chipdesign since, it is becoming a bottleneck forfuture technologies, lowering powerconsumption becomes major issue not only forincreasing battery life in portable devices, but

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Int. J. Elec&Electr.Eng&Telecoms. 2015

1 Department of Electronics Engineering, Pondicherry University, Pondicherry, India.

also for improving reliability and reducing heatremoval cost in high performance devices.With the scaling of technology powerdissipation becomes a major concern formicroprocessor systems design. A largefraction of the total power dissipation in CPUtoday is typically due to clocks (40%), memory(20%), datapaths (15%), and control unit(15%), I/O Pads (10%) as shown in Figure 1.Hence, 55% of total power of CPU is

Research Paper

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dissipated only in datapaths and clocks. So,to reduce the power of clock and data path,clock and control signal gating techniques areintroduces.

loaded into registers infrequently but the clocksignal continues to switch at every clock cycleoften driven a large capacitive load. So, asignificant amount of power can be saved byidentifying when the registers are inactive anddisabling the clock during these periods. Thistechnique has been extensively used fordynamic power reduction in low powerapplications. However, at any particular instantonly a single module may be functional, butunnecessary clocking of the other moduleslead to a lot of power dissipation. Hence,Clock gating technique is a power downmethodology, which involves selectivelyclocking modules as and when required whilekeeping other inactive modules in quiescentmode. Thus the power consumption due tocharging and discharging of the clock atunused gates, is avoided in this strategy. Thereare three types of clock gating:

a) Latch based clock gating

b) Flip flop based clock gating

c) AND/OR gate based clock gating

Latch Based Clock GatingLatch based clock gating techniques employsa level-sensitive latch to the design as shownin Figure 2, for holding the enable signal fromthe active edge of the clock until the inactiveedge of the clock (Frank Emnett and MarkBiegel, 2000). Since the latch captures thestate of the enable signal and holds it until thegeneration of complete clock pulse cycle andit is necessary for enable signal to be stableup to the rising edge of the clock pulse.

Flip-Flop Based Clock GatingThe Flip-Flop based clock gating techniqueconsists of a level sensitive latch in design as

Figure 1: Power Distributionin High-Performance CPU

A Simple Microprocessor contain registerfiles, an ALU and Control Circuit. ALU is thecore of microprocessors where allcomputations are being performed it is one ofthe most power hungry sections of its data pathand clock power. For designing a power efficientALU becomes a major issue to reduce the clockpower and switching activity of data paths.According to reference (Kapadia et al., 1999;and Kamaraju et al., 2010). Power optimization,traditionally relegated to the synthesis andcircuits level, now it shifted to the System Leveland Register-Transfer-Level (RTL). This ispossible due to clock gating and control signalgating. Clock gating techniques turn off theinactive units of the design and control signalgating stop the propagation of switching activityof data path by detecting the bus which is notactive by the help of selection line.

Clock Gating TechniquesClock power constitutes a significant portionof dynamic power. In many designs, data are

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OR gate at the signal path to stop thepropagation of signal, when it needs to bemasked. Another techniques is to use a latchor flip-flop to block the propagation of thesignal. Sometimes, a transmission gate or atristate buffer can be used in place of a latch ifcharge leakage is not concern. All signal-gating method requires control signals to stopthe propagation of switching activities, that'swhy it'sname given control-signal gating, asshown in Figure 4.

Figure 2: Latch Based Clock Gating

Figure 3: Flip-Flop Based Clock Gating

Figure 4: Control-Signal Gating

shown in Figure 3, to hold the enable signalfrom the active edge to the inactive edge ofthe clock.

AND/OR Gate Based Clock GatingIn AND/OR gate based clock gating techniqueuses the AND/OR gate for controlling of theclock signal. In AND gate clock gating clock isactive on the rising edge of the input clock,whereas in OR gate clock gating signal isactive on the falling edge of the clock.

Control-Signal Gating TechniquesThe control-signal technique employs theadvantage of a fine granularity analysis toreduce the switching activity in the datapathsbuses. The method is based on theObservability Don’t Care concept (ODC) todetect when a bus is not used and to stop thepropagation of the switching activity throughthe module(s) driving the bus. There are manydifferent ways to implement control-signalgating. The simplest method is to put an AND/

CONVENTIONAL16-BIT ALUWITHOUT GATINGFunctional of Conventional 16-Bit ALUThe basic blocks of a computer are CentralProcessing Unit (CPU), memory unit, andinput/output unit. CPU of the computer isbasically the same as the brain of a humanbeing. It contains all the registers, control unitand the Arithmetic Logic Unit (ALU). Arithmeticand Logic Unit (ALU) is considered as one ofthe common and the most crucial componentsof microprocessor. Usually ALU’s consists ofa number of functional blocks/units for differentarithmetical, logical and shifting operationwhich are realized using combinational circuits.Each of the functional blocks/unit performs a

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specific arithmetical, logical or shiftingoperation. Therefore, the ALU is one of thehottest spots in the datapaths. ALU takes 16-bit operands as inputs, process the operanddata and gives 16-bit output data. Followingoperation is performed by conventional ALU,described in Table 1.

0000 Add 1000 AND

0001 Subtract 1001 OR

0010 Increment 1010 NOT

0011 Decrement 1011 EXOR

0100 Multiply 1100 Shift left

0101 Division 1101 Shift right

0110 Clear 1110 Rotate left

0111 Set 1111 Rotate right

Table 1: Function of ALU

SelectOperation

ArithmeticOperation

SelectOperation

LogicOperation

PROPOSED ALU MODELWITH CLOCK ANDCONTROL-SIGNAL GATINGArchitecture of Proposed ALUInstead of designing ALU as a singlemodule, it is divided into sixteen functionalblocks, which is select by Clock gatingtechnique, but there is problem that when onemodule is functioning, all other 15 input bitlines will be always in active mode, causesmore switching power dissipation. Toremove this problem, we introduces controlsignal gating techniques, which will activateonly that line which is required for operationand deactivate other functional line similarto clock gating techniques. ProposedArchitecture of is shown in Figure 8, whichconsist of clock gating and control-signalgating circuit feeded to ALU module.

Clock Gating Circuit: It is combination of 4 x16 decoder and 16 AND logic gate, in whichclock signal is ANDed with output of decoder,which will select one of sixteen AND gate asdecided by opcode. Hence, clock gating circuitacts as a clock selector, which can select oneof the sixteen block of any architecture whichrequires clock.

Control Signal Gating Circuit: It is acombination of two 1 x 16 Demux, which iscontrolled by a control-signal, (as shown inFigure 8). We are applying input signal to thisblock and it will give a pair of sixteencombination of output line, which will be usedto feed the ALU block as a input pair line.Controlled line will select only one pair of outputline, i.e., one time only one output line willactivate and other fifteen will be off. Hence, inthis way, it saving the switching powerconsumption on datapath buses.

The Top level schematic view and Timingwaveform of Conventional ALU is shown inFigures 5 and 6 respectively.

Figure 5: Top Level Schematic Viewof Conventional ALU

Figure 6: Timing Waveformof Conventional ALU

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Clock distribution of proposed ALU isshown in Figure 7.

Function of Proposed ALUFunction of proposed ALU can be explainedas follows: There is two inputs line inproposed ALU architecture: one is clocksignal (Clock) and another is selection line(SEL). SEL line has feeded to Control signalgating circuit, clock-gating circuit and alsoto out DEMUX. It acts as a opcode signalfor Decoder in Clock gating circuit, whichwill selects one of the sixteen AND gatesof clock-feeded AND logic in clock-gatingcircuit. SEL is also feeded to control-signalgating circuit as a controlling signal. Hence,in this way, SEL line is act as a controlsignal for ALU operation.

For example, when selection line is “0000”,then opcode will be “0000”, then it will selects

Figure 8: Proposed Architecrue of ALU with Clock and Control-Signal Gating

Figure 7: Clock Distribution in ProposedALU Model

AND 1 gate, which in turn sends clock signalto the first functional block of ALU, while for

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remaining fifteen units clock signals are notallowed, at a time.

Control-signal gating circuit activate onlyfirst input lines of first block and deactivateother fifteen inputs line and then, out mux willselect output of first functional block becauseof selection line input as feeded. Hence, it'ssaving about 93.7 (15/16)% switching activitypower of its input data path and about 93.7(15/16)% clock power.

The timing waveform and top levelschematic of proposed ALU is shown inFigure 9 and Figure 10 respectively.

Figure 9: Timing Waveform of ProposedModel

Figure 10: Top Level RTL Viewof Proposed Model

RESULTSPower ComparisonThe dynamic and total Power of conventionaland proposed Model is calculated by XilinxX’Power Analyzer tool considering targetFPGA Device Virtex-6 Low power with speedgrade –1 L. Power of both model is given inTable 2. and dynamic power comparison isshown in Figure 11.

Total power 1176 mW 1171 mW

Dynamic power 77 mW 72 mW

Quiescent power 1099 mW 1099 mW

Table 2: Power Comparison of Both Model

Parameter ConventionalModel

ProposedModel

Figure 11: Dynamic Power Comparison

From the above synthesis result and table,it is observed that the Dynamic power ofproposed model is reduced in comparisonto conventional model. Hence, clock andcontrol-signal gating can be implemented asa power efficient techniques to reduce thedynamic power of device.

Device Utilization SummaryDevice utilization summary of both the model(conventional as well as Proposed) is shownFigure 12 and Figure 13 respectively.

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is power efficient technique to optimize thepower of clock and datapath buses.

In this project work, there are still someimprovements could be done in the future forimproving the performance of ALU byintroducing Low power adder and multiplierunit. We can also improve in Clock and Controlsignal gating techniques by replacing it withappropriate circuit model. This techniques canalso be implemented at architecture level, byintroducing clock gating and other low powerdesign techniques, we can improve thedynamic power performance ofMicroprocessor and other power hungrydevices.

REFERENCES1. Bishwajeet Pandey and Manisha

Pattanaik (2013), “Clock Gating AwareLow Power ALU Design andImplementation on FPGA”, InternationalJournal of Future Computer andCommunication, Vol. 2, No. 5.

2. Christian Piguet (2005), “Low-PowerCMOS Circuits: Technology, LogicDesign and CAD Tools”, CRC Press.

3. Frank Emnett and Mark Biegel (2000),“Power Reduction Through RTL ClockGating”, SNUG, San Jose.

4. Hamid Mahmoodi, Tirumalashetty V,Matthew Cooke and Kaushik Roy (2009),“Ultra Low-Power Clocking SchemeUsing Energy Recovery and ClockGating”, IEEE Transactions on VeryLarge Scale Integration (VLSI) Systems,Vol. 17, No. 1.

5. Ireneusz Brzozowski and Andrzej Kos(1999), “Minimization of Power

Figure 12: Device Utilization Summaryof Conventional Model

Figure 13: Device Utilization Summaryof Proposed Model

CONCLUSIONThere are several approaches to reduce thedynamic power. In this project work, ALUmodel with clock gating and control signalgating technique is designed using VerilogHDL, simulated and synthesized using XilinxISE 13.2 considering Virtex Low power with aspeed grade–1 L, to optimize the power andit is found that ALU with both clock gating andcontrol-signal techniques consumes lesspower than conventional ALU. Hence, it isconcluded that clock and control-signal gating

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8. Kamaraju M, Lal Kishore K and Tilak AV N (2010), “Power Optimized ALU forEff icient Datapath”, InternationalJournal of Computer Applications ,Vol. 11, No. 11.

9. Kapadia H, Benini L and De Micheli G(1999), “Reducing Switching Activity onDatapath Buses with Control-SignalGating”, IEEE J. Solid-State Circuits,Vol. 34, March, pp. 405-414.

10. Pietro Babighian, Luca Benini and EnricoMacii (2005), “A Scalable Algorithm forRTL Insertion of Gated Clocks Based onODCs Computation”, IEEE Trans.Computer-Aided Design, Vol. 24, No. 1,pp. 29-42.

Consumption in Digital IntegratedCircuits by Reduction of SwitchingActivity”, EUROMICRO Conference,pp. 1376, doi:10.1109/EURMIC1999.794494.

6. Jagrit Kathuria, Ayoub Khan M and ArtiNoor (2011), “A Review of Clock GatingTechniques”, MIT International Journal ofElectronics and CommunicationEngineering, Vol. 1, No. 2, pp. 106-114.

7. Javier Castro, Pilar Parra and Antonio JAcosta (2010), “Optimization of Clock-Gating Structures for Low Leakage High-Performance Applications”, IEEEInternational Symposium on Circuit andSystem, May 10, pp. 3320-3223.