COMPUTER ORGANIZATION

AND ASSEMBLY LANGUAGE

Lecture 12

Computer Organization

We have learned the ISA of the processor till now

Given an algorithm, express it in terms of the processor ISA

Instruction Set Architecture

software

hardware

Working of Computer

Processor

Control

Datapath

Memory

Devices

Input

Output

Input Device Inputs Object Code

Processor

Control

Datapath

Memory

Devices

Input

Output

000000 00000 00101 0001000010000000

000000 00100 00010 0001000000100000

100011 00010 01111 0000000000000000

100011 00010 10000 0000000000000100

101011 00010 10000 0000000000000000

101011 00010 01111 0000000000000100

000000 11111 00000 0000000000001000

Object Code Stored in Memory

Processor

Control

Datapath

MemoryDevices

Input

Output

000000 00000 00101 0001000010000000

000000 00100 00010 0001000000100000

100011 00010 01111 0000000000000000

100011 00010 10000 0000000000000100

101011 00010 10000 0000000000000000

101011 00010 01111 0000000000000100

000000 11111 00000 0000000000001000

Processor Fetches an Instruction

Processor

Control

Datapath

MemoryDevices

Input

Output

000000 00000 00101 0001000010000000

000000 00100 00010 0001000000100000

100011 00010 01111 0000000000000000

100011 00010 10000 0000000000000100

101011 00010 10000 0000000000000000

101011 00010 01111 0000000000000100

000000 11111 00000 0000000000001000

Processor fetches an instruction from memory

Control000000 00100 00010 0001000000100000

Control Decodes the Instruction

Processor

Datapath

Memory

Devices

Input

Output

Control decodes the instruction to determine what to execute

Datapath Executes the Instruction

Processor

Control

Datapath

Memory

Devices

Input

Outputcontents Reg #4 ADD contents Reg #2

results put in Reg #2

Datapath executes the instruction as directed by control

000000 00100 00010 0001000000100000

Update the PC, and continue

Processor

Control

Datapath

MemoryDevices

Input

Output

000000 00000 00101 0001000010000000

000000 00100 00010 0001000000100000

100011 00010 01111 0000000000000000

100011 00010 10000 0000000000000100

101011 00010 10000 0000000000000000

101011 00010 01111 0000000000000100

000000 11111 00000 0000000000001000

Fetch

DecodeExecute

Output Data Stored in Memory

Processor

Control

Datapath

MemoryDevices

Input

Output00000100010100000000000000000000

00000000010011110000000000000100

00000011111000000000000000001000

At program completion the data to be output resides in memory

Output Device Outputs Data

Processor

Control

Datapath

Memory

Devices

Input

Output

00000100010100000000000000000000

00000000010011110000000000000100

00000011111000000000000000001000

MIPS ISA to Implement

Arithmetic Instructions

Add, sub, AND, OR, and slt (R-

type)

Memory access instructions

LW, and SW (I-type)

Branch instructions

Beq (I-type)

Jump instructions

J (J-type)

MIPS Machine

Read

AddressInstr[31-0]

Instruction

Memory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read

Data 1

Read

Data 2

ALU

ovf

zero

RegWrite

Data

Memory

Address

Write Data

Read Data

MemWrite

MemRead

Sign

Extend16 32

MemtoReg

ALUSrc

Shift

left 2

Add

PCSrc

RegDst

ALU

control

1

1

1

0

00

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15

-11]

Control

UnitInstr[31-26]

Branch

Shift

left 2

0

1

Jump

32

Instr[25-0]

26PC+4[31-28]

28

Build a MIPS Processor

Today – Build the ALU

Support all the Arithmetic/Logic operations

32

32

32

ALU control lines

result

a

b

ALU

ALU Control

Lines

Function

0000 AND

0001 OR

0010 add

0110 subtract

0111 Set on less than

1100 NOR

ALUOp and ALU control bits

Instruction

Opcode

ALUOp Instruction

operation

Funct

field

Desired ALU

action

ALU

control

input

LW 00 Load word XXXXX

X

add 0010

SW 00 Store word XXXXX

X

Add 0010

Beq 01 Branch equal XXXXX

X

Subtract 0110

R-type 10 Add 100000 Add 0010

R-type 10 Subtract 100010 Subtract 0110

R-type 10 AND 100100 AND 0000

R-type 10 OR 100101 OR 0001

R-type 10 Set on less

than

101010 Set on less

than

0111

Implementation

Truth table for 4 ALU control bits

OP rs rt rd sa funct

6 bits 6 bits

Building a 1-bit Binary Adder

S = A xor B xor carry_incarry_out = (A and B) or (A and carry_in) or (B and carry_in)

1 bit

Full

Adder

A

BS

carry_in

carry_out

• How can we use it to build a 32-bit adder?

• How can we modify it easily to build an adder/subtractor?

A B carry_in carry_out S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

Building 32-bit Adder

Just connect the carry-out of

the least significant bit FA to

the carry-in of the next least

significant bit and connect . . .

Ripple Carry Adder (RCA)

advantage: simple logic, so small

(low cost)

disadvantage: slow and lots of

glitching (so lots of energy

consumption)

1-bit

FA

A0

B0

S0

c0=carry_in

c1

1-bit

FA

A1

B1

S1

c2

1-bit

FA

A2

B2

S2

c3

c32=carry_out

1-bit

FA

A31

B31

S31

c31

. . .

Building 32-bit Adder/Subtractor

Remember 2’s

complement is just

complement all the bits

add a 1 in the least

significant bit

A 0111 0111

B - 0110 + 1010

1-bit

FA S0

c0=carry_in

c1

1-bit

FA S1

c2

1-bit

FA S2

c3

c32=carry_out

1-bit

FA S31

c31

. . .

A0

A1

A2

A31

B0

B1

B2

B31

add/subt

B0

control

(0=add,1=subt) B0 if control = 0,

!B0 if control = 1

Logic Operations

Logic operations operate on individual bits of the

operand.

$t2 = 0…0 0000 1101 0000

$t1 = 0…0 0011 1100 0000

and $t0, $t1, $t2 $t0 =

or $t0, $t1, $t2 $t0 =

xor $t0, $t1, $t2 $t0 =

nor $t0, $t1, $t2 $t0 =

How do we expand our FA design to handle the logic

operations - and, or, xor, nor ?

0…0 0000 1100 0000

0…0 0011 1101 0000

0…0 0011 0001 0000

1…1 1100 0010 1111

A Simple ALU Cell

1-bit

FA

carry_in

carry_out

A

B

add/subt

add/subt

result

op

Tailoring the ALU to the MIPS

ISA

Need to support the set-on-less-than instruction (slt)

remember: slt is an arithmetic instruction

produces a 1 if rs < rt and 0 otherwise

use subtraction: (a - b) < 0 implies a < b

Need to support test for equality (beq)

use subtraction: (a - b) = 0 implies a = b

Need to add the overflow detection hardware

Modifying the ALU Cell for slt

1-bit

FA

A

B

result

carry_in

carry_out

add/subt op

add/subt

less

ALU for slt

0

0

set

First perform a subtraction

Make the result 1 if the subtraction yields a negative result

Make the result 0 if the subtraction yields a positive result

A1

B1

A0

B0

A31

B31

+

result1

less

+

result0

less

+

result31

less

. . .

tie the most significant sum bit (sign bit) to the low order less input

ALU for Zero

+

A1

B1

result1

less

+

A0

B0

result0

less

+

A31

B31

result31

less

. . .

0

0

set

First perform

subtraction

Insert additional logic

to detect when all result

bits are zero

zero

. . .

add/subtop

Note zero is a 1 when result is all zeros

Overflow Detection

Overflow: the result is too large to represent in the number of bits allocated

On your own: Prove you can detect overflow by:

Carry into MSB xor Carry out of MSB

1

1

1 10

1

0

1

1

0

0 1 1 1

0 0 1 1+

7

3

0

1

– 6

1 1 0 0

1 0 1 1+

–4

– 5

71

0

Modifying the ALU for Overflow

+

A1

B1

result1

less

+

A0

B0

result0

less

+

A31

B31

result31

less

. . .

0

0

set

Modify the most

significant cell to

determine overflow

output setting

Disable overflow bit

setting for unsigned

arithmetic

zero

. . .

add/subt

op

overflow

Shift Operations

Also need operations to pack and unpack 8-bit characters into

32-bit words

Shifts move all the bits in a word left or right

sll $t2, $s0, 8 #$t2 = $s0 << 8 bits

srl $t2, $s0, 8 #$t2 = $s0 >> 8 bits

Such shifts are logical because they fill with zeros

op rs rt rd shamt funct

000000 00000 10000 01010 01000 000000

000000 00000 10000 01010 01000 000010

Shift Operations

An arithmetic shift (sra) maintain the arithmetic correctness

of the shifted value (i.e., a number shifted right one bit should

be ½ of its original value; a number shifted left should be 2

times its original value)

so sra uses the most significant bit (sign bit) as the bit shifted in

note that there is no need for a sla when using two’s

complement number representation

sra $t2, $s0, 8 #$t2 = $s0 >> 8 bits

The shift operation is implemented by hardware (usually a

barrel shifter) outside the ALU

000000 00000 10000 01010 01000 000011

MIPS Machine

Read

AddressInstr[31-0]

Instruction

Memory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read

Data 1

Read

Data 2

ALU

ovf

zero

RegWrite

Data

Memory

Address

Write Data

Read Data

MemWrite

MemRead

Sign

Extend16 32

MemtoReg

ALUSrc

Shift

left 2

Add

PCSrc

RegDst

ALU

control

1

1

1

0

00

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15

-11]

Control

UnitInstr[31-26]

Branch

Shift

left 2

0

1

Jump

32

Instr[25-0]

26PC+4[31-28]

28