8085 CPU- Architecture 1

Intel 8085-Architecture

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8085 CPU- Architecture 27/8/2015

8085 CPU- Architecture 3

Functional blocks

• Registers• ALU• Instruction decoder and machine cycle encoder• Address buffer• Address / Data buffer• Incrementer / Decrementer Address Latch• Interrupt control• Serial I/O control• Timing and control circuitry7/8/2015

8085 CPU- Architecture 4

1.Registers

• General purpose registers

• Temporary registers

• Special purpose registers

• Sixteen bit registers7/8/2015

8085 CPU- Architecture 5

General purpose registers

• B,C,D,E,H,L are 8 bit registers.

• Combination of BC,DE,HL registers are form a 16 bit

registers

• HL pair also function as a data pointer or memory pointer

• To store intermediate results in their memory

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8085 CPU- Architecture 6

Temporary registers

• Temporary storage registers to store one input for arithmetic and logical operations

• Programmer cannot access this registers externally

• W and Z registers are used as temp. registers.

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8085 CPU- Architecture 7

Special purpose registers

• Accumulator – tri-state 8 bit register, used in arithmetic logical operations and mostly the performed results are stored in it.

• Flag Register-8 bit registers.Sign Flag- D7-1 the num is negative

D7-0 the num is positive

Zero Flag- set if ALU result is zeroReset if ALU result is non-zero

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8085 CPU- Architecture 8

• Auxiliary carry flagflag is set if the bit is overflow out of bit

3.

Parity flag-the number of 1’s present in accumulator,-Even parity means flag set-Odd Parity means flag reset

Carry Flag-flag is set if there is an overflow of bit 7.

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8085 CPU- Architecture 9

16-bit registers

• Program counter (PC)-stores the address of next instruction to be fetched.-PC acts as a pointer to the next instruction.

• Stack pointer (SP)- to hold the address of the most recent stack entry.

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8085 CPU- Architecture 10

ALU

• Addition , Subtraction

• Logical operations

- AND,OR,EX-OR.

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8085 CPU- Architecture 11

Instruction decoder

• Fetch and store the opcode in instruction

register.

• Decodes the opcode and gives timing and

control signals which control reg.,data

buffers,ALU,external peripherals.

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8085 CPU- Architecture 12

Address buffer

• 8-bit unidirectional buffer

• Tri-state high order address bus under such

conditions like halt,hold , reset.

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8085 CPU- Architecture 13

Address /data buffer

• 8-bit unidirectional buffer

• Low order address bus and data bus

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8085 CPU- Architecture 14

Incrementer /Decrementer latch

• 16-bit register

• Used to INC / DEC. the contents of program

counter and stack pointer

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8085 CPU- Architecture 15

Interrupt control

• Sometimes there will be need to make a

interrupt to allow or block the signals for

some time.

• RST5.5,RST 6.5,RST7.5 ,TRAP,INTR AND INTA.

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8085 CPU- Architecture 16

Serial I/O control

• SID-Serial input data for receive data.

• SOD-Serial output data for sending data.

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8085 CPU- Architecture 17

Timing and control

• For fetching and decoding operations and

generating appropriate signals for instruction

execution ,control circuitry.

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