8085 Architecture Introduction

11

8085 8085 Microprocessor Microprocessor

ArchitectureArchitecture

8085 8085 Microprocessor Microprocessor

ArchitectureArchitecture

DR E M MOHAMMED

22

Intel 8085 CPU Block DiagramIntel 8085 CPU Block Diagram

33

Registers – hold temporary data.Registers – hold temporary data. Instruction register (IR)– holds the Instruction register (IR)– holds the

currently executing instruction. currently executing instruction. Instruction Decoder (ID)- decodes the Instruction Decoder (ID)- decodes the

instruction. Once decoded, the instruction instruction. Once decoded, the instruction controls the remainder of the MPU, controls the remainder of the MPU, memory and IO through the timing and memory and IO through the timing and control block.control block.

The 8085 Block DiagramThe 8085 Block Diagram

44

Temporary register- holds information Temporary register- holds information from the memory or register array. An from the memory or register array. An input of the ALU.input of the ALU.

Increment/Decrement address latch – It Increment/Decrement address latch – It adds or subtracts one from any of other adds or subtracts one from any of other registers in register array. registers in register array.

The 8085 Block DiagramThe 8085 Block Diagram

Why are the PC and SP registers are 16-bit ?

55

Signals and I/O Pins

66

Intel 8085 Intel 8085 Pin Pin

ConfigurationConfiguration

77

8085 MPU has 3 8085 MPU has 3 pins that control or pins that control or present the clock present the clock signal.signal. X1 and X2 pins X1 and X2 pins

determine the determine the clock frequency.clock frequency.

CLK OUT is a TTL CLK OUT is a TTL square-wave square-wave output clock.output clock.

The CLOCK OUT The CLOCK OUT is one-half the is one-half the crystal crystal frequency. frequency.

Clock PinsClock Pins

8085A

X1 CLK OUT

X2

6 MHz

88

8085 8085 μμp consists of 16 signal pins use as p consists of 16 signal pins use as address bus.address bus.

Divide into 2 part: A15 – A8 (upper) and Divide into 2 part: A15 – A8 (upper) and AD7 – AD0 (lower).AD7 – AD0 (lower). A15 – A8 : Unidirectional, known as ‘high A15 – A8 : Unidirectional, known as ‘high

order address’.order address’. AD7 – AD0 : bidirectional and dual AD7 – AD0 : bidirectional and dual

purpose (address and data placed once at purpose (address and data placed once at a time).a time).

AD7 – AD0 also known as ‘low order AD7 – AD0 also known as ‘low order address’.address’.

To execute an instruction, at early stage To execute an instruction, at early stage AD7 – AD0 uses as address bus and AD7 – AD0 uses as address bus and alternately as data bus for the next cycle.alternately as data bus for the next cycle.

The method to change from address bus The method to change from address bus to data bus known as ‘to data bus known as ‘bus multiplexingbus multiplexing’. ’.

8085 Pinout8085 Pinout

99

Group of signals consists of :Group of signals consists of : Two control signals (‘RD’ – read; and ‘WR’ Two control signals (‘RD’ – read; and ‘WR’

- write).- write). Three status signals (IO/M, S1, and S0) to Three status signals (IO/M, S1, and S0) to

recognize nature of operation.recognize nature of operation. ALE (Address Latch Enable) signal :ALE (Address Latch Enable) signal :

active high signal - generated to show active high signal - generated to show the start of the start of 8085 operation. 8085 operation.

When transition 1-to-0: indicate that When transition 1-to-0: indicate that lines AD7-AD0 (AD7-AD0 = A7-A0) act lines AD7-AD0 (AD7-AD0 = A7-A0) act as address lines.as address lines.

8085 Pinout8085 Pinout

1010

ALE used to demultiplex address/data busALE used to demultiplex address/data bus

1111

Control and Status SignalsControl and Status SignalsControl and Status SignalsControl and Status Signals

Signals:Signals: RD – Read (active low). To indicate that the I/O or RD – Read (active low). To indicate that the I/O or

memory selected is to be read and data are memory selected is to be read and data are available on the bus.available on the bus.

WR – Write: Active low. This is to indicate that the WR – Write: Active low. This is to indicate that the data available on the bus are to be written to data available on the bus are to be written to memory or I/O ports.memory or I/O ports.

IO/M – To differentiate I/O operation of memory IO/M – To differentiate I/O operation of memory operations. operations.

‘‘0’ - indicates a memory operation.0’ - indicates a memory operation. ‘‘1’-indicates an I/O operation. 1’-indicates an I/O operation.

IO/M combined with RD and WR to generate I/O IO/M combined with RD and WR to generate I/O and memory control signals.and memory control signals.

S1 dan S0: Status signals, similar to IO/M, can S1 dan S0: Status signals, similar to IO/M, can identify various operations as shown on the identify various operations as shown on the following table :following table :

1212

Control and Status Signals.Control and Status Signals.Control and Status Signals.Control and Status Signals.

1313

Interrupt SignalsInterrupt SignalsInterrupt SignalsInterrupt Signals 8085 8085 μμp has several interrupt signals as shown in the p has several interrupt signals as shown in the

following table.following table.

1414

Interrupt signalsInterrupt signalsInterrupt signalsInterrupt signals

An interrupt is a hardware-initiated subroutine CALL.An interrupt is a hardware-initiated subroutine CALL. When interrupt pin is activated, an ISR will be called, When interrupt pin is activated, an ISR will be called,

interrupting the program that is currently executing.interrupting the program that is currently executing.

PinPin Subroutine LocationSubroutine Location

TRAPTRAP 00240024

RST 5.5RST 5.5 002C002C

RST 6.5RST 6.5 00340034

RST 7.5RST 7.5 003C003C

INTRINTR **

Note: * the address of the ISR is determined by the external Note: * the address of the ISR is determined by the external hardware.hardware.

1515

Interrupt signalsInterrupt signalsInterrupt signalsInterrupt signals

INTR input is enabled when EI INTR input is enabled when EI instruction is executed.instruction is executed.

The status of the RST 7.5, RST 6.5 and The status of the RST 7.5, RST 6.5 and RST 5.5 pins are determined by both EI RST 5.5 pins are determined by both EI instruction and the condition of the instruction and the condition of the mask bits in the interrupt mask mask bits in the interrupt mask register. register.

1616

Interrupt Interrupt VectorsVectors

Interrupt Interrupt VectorsVectors

1717

A circuit that causes an RST4 instruction (E7) A circuit that causes an RST4 instruction (E7) to be executed in response to INTR.to be executed in response to INTR.A circuit that causes an RST4 instruction (E7) A circuit that causes an RST4 instruction (E7) to be executed in response to INTR.to be executed in response to INTR.

When INTR is When INTR is asserted, asserted, 8085 8085 response with response with INTA pulse. INTA pulse.

During INTA During INTA pulse, 8085 pulse, 8085 expect to see expect to see an instruction an instruction applied to its applied to its data bus.data bus.

1818

RESET signalRESET signalRESET signalRESET signal

Following are the two kind of RESET Following are the two kind of RESET signals:signals: RESET INRESET IN: an active low input signal, Program : an active low input signal, Program

Counter (PC) will be set to 0 and thus MPU Counter (PC) will be set to 0 and thus MPU will reset.will reset.

RESET OUTRESET OUT: an output reset signal to indicate : an output reset signal to indicate that the that the μμp was reset (i.e. p was reset (i.e. RESET IN=0)RESET IN=0). It . It also used to reset external devices.also used to reset external devices.

1919

RESET signalRESET signalRESET signalRESET signal

2020

Direct Memory Access (DMA)Direct Memory Access (DMA)Direct Memory Access (DMA)Direct Memory Access (DMA)

DMA is an IO technique where external IO DMA is an IO technique where external IO device requests the use of the MPU buses.device requests the use of the MPU buses.

Allows external IO devices to gain high Allows external IO devices to gain high speed access to the memory.speed access to the memory. Example of IO devices that use DMA: disk Example of IO devices that use DMA: disk

memory system. memory system. HOLD and HLDA are used for DMA. HOLD and HLDA are used for DMA. If HOLD=1, 8085 will place it address, data If HOLD=1, 8085 will place it address, data

and control pins at their high-impedance.and control pins at their high-impedance. A DMA acknowledgement is signaled by A DMA acknowledgement is signaled by

HLDA=1. HLDA=1.

2121

MPU Communication and Bus TimingMPU Communication and Bus TimingMPU Communication and Bus TimingMPU Communication and Bus Timing

Figure 3: Moving data form memory to MPU using instruction MOV C, A (code machine 4FH = 0100 1111)

2222

The Fetch Execute Sequence :The Fetch Execute Sequence :1.1. The The μμp placed a 16 bit memory address p placed a 16 bit memory address

from PC (program counter) to address bus. from PC (program counter) to address bus. – Figure 4: at T1Figure 4: at T1

– The high order address, 20H, is placed at A15 – The high order address, 20H, is placed at A15 – A8. A8.

– the low order address, 05H, is placed at AD7 - the low order address, 05H, is placed at AD7 - AD0 and ALE is active high. AD0 and ALE is active high.

– Synchronously the IO/M is in active low Synchronously the IO/M is in active low condition to show it is a memory operation.condition to show it is a memory operation.

2.2. At T2 the active low control signal, RD, is At T2 the active low control signal, RD, is activated so as to activate read operation; activated so as to activate read operation; it is to indicate that the MPU is in fetch it is to indicate that the MPU is in fetch mode operation. mode operation.


2323Figure 4: 8085 timing diagram for Opcode fetch cycle for MOV C, A .


2424

3.3. T3: The active low RD signal enabled the T3: The active low RD signal enabled the byte instruction, 4FH, to be placed on byte instruction, 4FH, to be placed on AD7 – AD0 and transferred to the MPU. AD7 – AD0 and transferred to the MPU. While RD high, the data bus will be in While RD high, the data bus will be in high impedance mode.high impedance mode.

4.4. T4: The machine code, 4FH, will then be T4: The machine code, 4FH, will then be decoded in instruction decoder. The decoded in instruction decoder. The content of accumulator (A) will then content of accumulator (A) will then copied into C register at time state, T4. copied into C register at time state, T4.


2525

Thank youThank youM D SM D S

Documents

8085 Architecture Introduction