WELCOME

DESIGN AND IMPLEMENTATION OF CMOS RAIL-TO-RAIL

OPERATIONAL AMPLIFIERS

Grace AbrahamRoll No: 01VLSI & ES

3CONTENTS

Dept. of ECE09/08/2015

• INTRODUCTION

• RAIL-TO-RAIL INPUT STAGE

• RAIL-RAIL OUTPUT STAGE

• SCHEMATIC DESIGN

• LAYOUT IMPLEMENTATION

• SIMULATION RESULTS

• CONCLUSION

INTRODUCTION

• Rail-to-rail operational amplifiers allow signals to swing from the negative supply rail to positive supply rail• Input common-mode voltage specifies the range of input for normal operation• Output voltage swing is defined as the range of max. negative to positive peak output voltage• Rail-to-rail high swing op-amps have highly linear response when used as a voltage follower• Rail-to-rail operation is based on op-amp topology

4

Dept. of ECE09/08/2015

5

Dept. of ECE

• Rail-to-rail input stage allows the op-amp to operate with input voltages near the voltage supply rails • The output stage minimizes the voltage drops at the output to achieve high swing

09/08/2015

6

Dept. of ECE

RAIL-TO-RAIL INPUT STAGE

• Input stages

• PMOS transistors in input terminal allows i/p voltage to operate near the negative supply rail• NMOS differential i/p pairs operate near the positive rail • Parallel-connected PMOS and NMOS differential stage achieves operating mode at both rails• At least one of the differential i/ps is still active at either rail

PMOS differential input pairs or NMOS differential input pairs

09/08/2015

7

Dept. of ECE

1. Complementary Differential Pair With Active Load

• Effect of active load is to realize a single-ended output for both NMOS & PMOS pairs• Each output is then connected as inputs to a push-pull inverter stage• Output of NMOS pair biases the PMOS in push-pull inverter and PMOS pair biases the NMOS • Push pull inverter stage integrates the o/ps of previous stage into single output• This circuit uses less transistors and less biasing network• With an addition of an o/p stage after push pull inverter lead to an issue of op-amp stability and compensation

09/08/2015

8

Dept. of ECE09/08/2015

9

Dept. of ECE

2. Complementary Differential Pair With Cascode Load

• Folded cascode op-amp with a PMOS differential pair and NMOS cascode load• Folded cascode op-amp with a NMOS differential pair and NMOS cascode load• More transistors compared to input stage at active load • Topology is more complex but offer more flexibility in design• Topology has fewer stages making op-amp compensation for stability manageable

09/08/2015

10

Dept. of ECE09/08/2015

11

Dept. of ECE

RAIL-TO-RAIL OUTPUT STAGE

• Output stage minimizes voltage drops at the output branch • Allows the output to reach the rails• Output stage increases the op-amp’s voltage gain

09/08/2015

Dept. of ECE

1. Push – pull Inverter Output Stage 12

• Also known as complementary common-source output stage• Uses a common-source NMOS & PMOS connected at the drain• Push-pull inverter output stage due to behavior of topology with each device conducting for alternate half-cycles at the input• Uses 2 transistors which are at saturation• Bias is the o/p voltage from previous stage• No current bias network• Current in o/p branch depend on size of transistor• Limitation in the design of transistor sizes

09/08/2015

Dept. of ECE

13

09/08/2015

Dept. of ECE

1. Common Source Output Stage 14

• Composed of a common source amplifier with a current driver• A common source PMOS with an NMOS current mirror load or a common source NMOS with a PMOS current mirror load• Current source is mirrored to provide current bias• Supply current consumption of output is more controllable compared to push-pull inverter

09/08/2015

Dept. of ECE

15

09/08/2015

Dept. of ECE

SCHEMATIC DESIGN

• Initial sizes and bias are set and using MOS current equation in saturation• Corresponding W/L ratio’s are calculated depending on current flow in different branches• Design requires a maximum supply current of 250μA, input offset voltage less than 1mV and unity gain bandwidth greater than 100KHz

16

09/08/2015

1. Complimentary differential pair with active load with common source o/p stage

Dept. of ECE

17

• Transistors are grouped into pairs and implemented with equal ratios to reduce mismatches• To minimize current consumption, currents are generated using only 1 current bias network• To minimize area of amplifier, resistor for biasing is realized using a properly-sized diode-connected transistor• Two main considerations in design

• Compensation is necessary because multiple stages of op-amp make circuit unstable

Operating point Two identical diode-connected transistors are used to generate the required current

09/08/2015

18

Dept. of ECE

• Lead compensation to compensate instability of opamp• Mirror-pole compensation to stabilize circuit

09/08/2015

Dept. of ECE

192. Complimentary differential pair with cascode load with push pull o/p stage

• A folded cascode op-amp with PMOS differential pair & NMOS cascode load is used• Widths of differential pairs are increased to increase the transconductance of i/p transistors and improve the gain• Widths of voltage bias & upper current mirror PMOS are decreased• Widths of cascode load & lower current mirror PMOS are increased• Bias voltages are adjusted to put the transistors at edge of saturation• Two main considerations in design

Operating point Supply current of o/p stage - without using current bias network

09/08/2015

• Lead compensation to compensate instability of opamp• This circuit has fewer stages compared to other one

20

Dept. of ECE09/08/2015

LAYOUT IMPLEMENTATION

Dept. of ECE

21

• Comdiff-Act topologies have larger areas since larger compensating capacitors are used

09/08/2015

SIMULATION RESULTS

• Op-amps are implemented in 0.25μm CMOS process

• Simulated USING cadence design system software

• Op-amps with push-pull inverter output stage have higher gain

• OVSR and ICMR of op-amps with CS o/p stage is far from

supply rails

22

• Input offset voltage of op-amp with CS o/p stage is larger than those with push pull inverter o/p stage• Complementary differential pair with active loads results in lower phase margin

Dept. of ECE

23

09/08/2015

24

Dept. of ECE09/08/2015

CONCLUSION

Dept. of ECE

25

• Rail-to-rail input and output stages are necessary for rail-to-rail input and output operation• A standard design methodology is formulated for different topologies• Main design consideration is stability issue since passive components for compensation n/w consumes a large amount of chip space• Input stage : Complementary differential pair with cascode load

• Output stage : Push-pull inverter

Less stability issues

Maximum gain Does not limit the output voltage swing range of op-amp

09/08/2015

REFERENCE

• Design and Implementation of CMOS rail-to-rail operational amplifiers – Michal Angelo G Lorenzo, Maria Theresa A Gusad, John Richard E. Hizon

26

Dept. of ECE09/08/2015

THANK YOU