Chapter:10Calculator Design with LCD Using FPGA

By:Hossam Hassan

PhD Student, MSIS Lab,Chungbuk National University

MSIS

Objectives• In this lab we will deal with the LCD (Liquid Crystal Display) display which as dot-matrix used

to display information on many devices. • We will write Verilog code to implement a basic calculator and show the results on the LCD

display then simulate how to drive LCD display and synthesis the code to run on FPGA board.• We will consider the following code for the calculator operation:

Binary Code Operation

000 Nothing to do

001 +

010 -

011 *

100 /

101 =

110 ~ 111 Nothing to do

Objectives• Our design for simple calculator will be as following:

• Enter your First digit (Only One Digit)• Select Arithmetic Operation (+,-,/,*)• Enter your Second digit (Only One Digit)• The result is ………….

Introduction• Text LCD modules are cheap and easy to interface using a microcontroller or FPGA.• LCDs are used in a wide range of applications including computer monitors,

televisions, instrument panels, aircraft cockpit displays, and signage. • They are common in consumer devices such as DVD players, gaming devices,

clocks, watches, calculators, and telephones, and have replaced cathode ray tube (CRT) displays in most applications.

• An LCD is made with either a passive matrix or an active matrix display grid. • The passive matrix LCD has a grid of conductors with pixels located at each intersection in the grid.

• A current is sent across two conductors on the grid to control the light for any pixel. • The active matrix LCD is also known as a thin film transistor (TFT) display.

• An active matrix has a transistor located at each pixel intersection, requiring less current to control the luminance of a pixel. For this reason, the current in an active matrix display can be switched on and off more frequently, improving the screen refresh time.

Introduction• A simplified scheme of time multiplexing with passive matrix

displays is shown in Figure. • A short pulse is applied periodically to the rows as a strobe

signal, whereas the columns carry the information signals. • A pixel is only selected if a difference in potential (and,

therefore, an electrical field) is present, that is, only if the row and column are not on a low or high level at the same time.

Text LCD module• Let's drive the LCD module from an FPGA board.• Text-LCD module is in the form of a one controller and the LCD Panel.• You have to transmit the data via the data bus, the controller can obtain desired display. • The figure below shows the internal structure of a LCD module.

Text LCD module• LCD controlled via a control lines:

• E (module selection signal Enable): command to enable the LCD, this should be the first pin to the action, such as reading or writing data.

• RS (internal register selection): a command input and the output of the inner pin is used to select one of the mem-ory. RS is 0 (read mode), RS is 1 (write mode).

• R/W (input / output selection): is used to select the data read and write data. If the R / W is 0 and the data write, R / W is 1, the data read state.

• DB0 ~ DB7 sending and receiving data through the 8-bit data bus of LCD controller• Vdd and Vss are the module voltage that operates on + 5V power supply.

Text LCD module• Table provides a summary of the features and a control signal for

use with an LCD. (For More information refer to the manual)1. Clears the screen. 2. Move the cursor to the position (Home) on the upper-left.3. The character output decide whether to go forward to go back one

character. I/D = 1: increases, I/D = 0 decreases, S = 1: Accompanies display shift

4. The display ON/OFF, the cursor of the ON/OFF, a cursor blink ON/OFF determination D = 1: Screen ON, C = 1: cursor ON, B = 1: flashing ON

5. determining a direction in case of transmitting the character to dis-play on the LCD continues. S/C = 1: display shift, S/C = 0: No shift, R/L = 1: right, R/L = 0: left

6. The control settings of the LCD. 4-bit/8-bit data and determines the settings such as font size. IF = 1: 8 bits, IF = 0: 4 bits, N = 1: 2 line, N = 0: 1 line, F = 1: 5 × 10 font, F = 0: 5 × 7 font

7. specifies an address corresponding to the position to be displayed on the LCD.

Verilog implementation• To run our code we have 4 Inputs and 5 Outputs. • First, there are RESET and Clock can be entered by default in the FPGA, the KEY

and Mode_Switch as an input to select Mode are needed to control the Dot-Matrix (same as previous labs).

• Then, the Dot-Matrix is used for the output. (LEDs and 7-Segments used same as the previous labs).

Verilog implementationTop Module of the LCD example indicated the Input/Output Ports

- top.v

Verilog implementationTop Module of the LCD example indicated the Input/Output Ports

textlcd.v (top) Registers Declaration

State machine for control• Simple Calculator Registers for getting the values IDLE

Insert_1stNumber

First_Number

Insert_OpCode

OpCode_Is

Insert_2ndNumber

Second_Number

Result_Is

Function to convert hexadecimal or decimal to ASCII for LCD

Simple Calculator STATE MACHINE

Simple Calculator STATE MACHINE

Simple Calculator STATE MACHINE

Simple Calculator STATE MACHINE

Text LCD control related to Counter and Enable

Text LCD Mode control order

Text LCD control, according to the Mode

Verilog Behavioral Simulation • To test the operation of the LCD Display and the functionality of our code we have to run

behavioral simulation as following steps:• Define the IOs for the Design Under Test (DUT) to provide inputs and see the expected output on the

ISim waveform. • We define the input in the testbench as register type, so we can provide our inputs for test. • The output will be wire type, we cannot modify.

Homework • Do the following exercise and explain your Verilog code with

simulation, and test on the FPGA.• Run the LCD Project and display your name. (Hint: you have to convert ASCII

to Hexadecimal)• Add more features to the simple calculator example.

Thank You