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FPGA Calculator Core
Mid Presentation
Chen ZukermanLiran Moskovitch
Advisor : Moshe Porian
Duration: semesterialNovember 2011
Contents
• Project Overview (+ Intro)• Top Architecture• Transition to postfix notation• Micro Architecture• Testability• Next steps• Schedule
Project Overview
GUI FPGA
Feedback
Result
Hardware implementation of calculator core :
• Positive integers
• Operands: ‘+’ , ’-’ , ’x’, ‘^’ , ‘ { ‘ , ‘ } ‘
• Precedence rules compatible
• Manually acquisition Input via Matlab GUI
• Result display - LCD + debugging feedback
Top Architecture
Implemented integrated Next Step
Inte
rcon
Wis
hbon
e
TX PATH
WN
B2
WBS2
RX PATH
WBM
1
WBS1
CALC_CORE
WBS3
WBM3
LCD_CORE
WBS4
Altera Cyclone II FPGA
LCD Display
HD 44780
GUI - MATLAB
Uart Out115200 bits/sec
Uart In 115200 bits/sec
Inte
rcon
Wis
hbon
e
TX PATH
WN
B2
WBS2
RX PATH
WBM
1
WBS1
CALC_CORE
WBS3
WBM3
LCD_CORE
WBS4
Altera Cyclone II FPGA
GUI - MATLAB
Uart In 115200 bits/sec
Uart Out115200 bits/sec
LCD Display
HD 44780
Implemented integrated Next Step
SOP
Type
Address
Data Length
Postfix Data..
FF
CRC
EOP
Infix - Data..
FF
Postfix Data..
FF
Infix - Data ..
FF
Infix - Data..
FF
Result
Result
Type
Address
Data Length
Result
Type
Address
Data Length
Result
SOP
Type
Address
Data Length
CRC
EOP
Type
Address
Data Length
Infix - Data..
FF
Result
Data Flow
Previous calculator algorithm
5 x ( 6 + 2 ^ 2 ) (5 x ( 6 + 2 ^ 2 )) (5 x ( 6 + 4 )) ( 5 x 10 )50(
5
x
(
6
+
2
^
2
EOC
)
)
4
(
5
x
(
6
+
)
EOC
)
4
10
(
5
x
10
EOC
)
50
Problems with the algorithm• Multiple read transitions in the RAM :
Seeking for a specific operator each time and start the search again for every partial result calculated
• Multiple write transitions in the RAM:
After each partial calculation the partial result is been written to the upper operand involved and shift all cells beneath the upper operand is required.
By using the Postfix notation RAM actions can be reduced, calculation is simplified and system performance improved
The postfix notation benefits
• The postfix notation is a mathematical notation wherein every operator follows all of its operands.
• The postfix notation features are:
• parenthesis-free
• precedence rules are taken into account, in advance, therefore simplifies the calculation
for example : 3 4 + (infix: 3 + 4)
Infix to postfix conversion
Stack
Infix:
Postfix:
5 * ( 6 + 2 ^ 2 )
5 *
(
6
+
2
^ > +
precedence
^
2 ^ + *
Micro Architecture
Ram Charger• Ram Charger receives the string data from WS
and runs the data writing process in Ram1
• Ram Charger operation is according to the following FSM diagram:
Ram Charger in action
Detailed View
ACU - Algebraic Calculation Unit
02
03
010
1
02
03
06
1
06
1
2 3 6
Multiplier example (2x3=6) – wave view
Operation Table
Select value Hex code Binary code Operation
- 85 10010101 (
- 86 10010110 )
011 83 10000011 ^
010 82 10000010 x
000 80 10000000 +
001 81 10000001 -
- FF 11111111 End of Postfix\infix
• Runs and manages the core operation
• Produces necessary control signals in the right timing
• Operand Path
• Operator Path
• Final Result Path
Calculator Core State Machine
Calc Core State Machine
RAM2(32 bits)
ACU
do
ut_
valid
addr_
ou
t
aout_
valid
addr_in
din_validdata_in
data
_ou
t
data
_se
l
Wishbone Slave
TGA_I
ADR_I
TGD_I
DAT_I
CYC_I
STB_I
WE_I
DAT_O
ACK_O`
RAM Charger
valid
_i
dat_
i
len_i
cyc_
i
do
ut_
valid
data
_ou
t
load_
finish
data
1
data
2
sel_
op
acu_
data
_valid
result
Calc_Core Registers
reg_sel
reg_en
result_valid
Result_Ready
Result
RAM1(8 bits)
addr_in
din_valid
data_in
addr_
ou
t_1
a_ou
t_valid
_1
02
02FF
03820580
82038005
02
00
0B
02
1
1
0B
02
03
03
82
82
02
0203
0382
03
03
02
02
06
06
05
05
80
05
05
06
06
0B
0B
FF
FF
0B
0B
1
Calculator Core in action
detailed view
Testability• Testing and simulating
environment :
Goals : 1. functionality verification 2. verification that hardware and software calculation results are equal
GUI
Method select
Enter the exercise
Exhibit the data to transmit
Exercise display
Software result
Hardware result
Gui messages
GUI-Video demonstration 1
http://www.youtube.com/watch?v=RB9x5or1EsU
GUI-Video demonstration 2
http://www.youtube.com/watch?v=UoZdFcK59V0
Text FileString txt file format :
• General comment – desired test literally, explanation, Clarifications etc.
• Different notations comment: infix , postfix , postfix in hex + operator conversion
• Data line + expected result comment
Postfix data Infix data End of postfix End of infix
Expected resultWishbone signals
TGA – Client TypeTGD – data lengthADR – Client inner address
Text File• Txt file example (3
strings):
String generator + checker
• Allows simple & fast testing and simulation
• Automatic feedback – message in the transcript window
• Working with multiple strings one after the other
String generator + checker example
Beginning of transmissionEnd of transmissionData transmission process
2 3 5 11
Operators blocks basic testing
32 bits
31 bits
32 bits
32 bits
32 bits
16 bits
Power basic tests:Adder basic tests: Multiplier basic
tests:Subtractor basic tests:
16 bits
16 bits
General testing
Next steps
• System integration with former project integrated blocks: RX, TX, wishbone etc.
• Implementation of result transmission from the Calc_core to the TX .
• Testing and Simulating in the top level after full system Integration.
• Synthesis + FPGA burning.
• Updating GUI to support the Uart protocol
• LCD Core implementation .
ScheduleTasks Date #
Finishing PLL implementation 12.11.12 1
cc_mdwm implementation + connecting Cores + TX adaptation 18.11.12 2
Connecting gui to uart protocol to RX and from TX. 25.11.12 3
Top simulations 2.12.12 4
Hardware burning to FPGA 9.12.12 5
Upgrading cc_mdwm to support LCD. 23.12.12 6
LCD Core implementation 30.12.12 7
Connecting all Cores + top simulations 6.1.13 8
Hardware burning to FPGA 13.1.13 9
Lab validation tests 20.1.13 10
Project Book 27.1.13 11
Final Presentation 3.2.13 12
