Logic gates

Logic Gates

Digital Logic and Software Principles

© University of Wales Newport 2009 This work is licensed under a Creative Commons Attribution 2.0 License.

The following presentation is a part of the level 4 module -- Digital Logic and Signal Principles. This resources is a part of the 2009/2010 Engineering (foundation degree, BEng and HN) courses from University of Wales Newport (course codes H101, H691, H620, HH37 and 001H). This resource is a part of the core modules for the full time 1st year undergraduate programme.

The BEng & Foundation Degrees and HNC/D in Engineering are designed to meet the needs of employers by placing the emphasis on the theoretical, practical and vocational aspects of engineering within the workplace and beyond. Engineering is becoming more high profile, and therefore more in demand as a skill set, in today’s high-tech world. This course has been designed to provide you with knowledge, skills and practical experience encountered in everyday engineering environments.

ContentsAND gate Truth Table Symbol OR gate NOT gate Exclusive OR EXOR gate Not AND NAND gate Not OR NOR gate Universal Gates NOT using NANDs only AND using NANDs only OR using NANDs only Logic Families Transistor Transistor Logic TTL TTL Gate Packages Complementary Metal Oxide Semiconductor Logic CMOS TTL and CMOS developments Logic Problem. Convert the circuit to NAND only. Logic Circuits TTL and CMOS Credits

In addition to the resource below, there are supporting documents which should be used in combination with this resource. Please see: Holdsworth B, Digital Logic Design, Newnes 2002 Crisp J, Introduction to Digital Systems, Newnes 2001

Logic Gates

AND gatee.g. I get up if it is 8-00 a.m. AND it is a weekday

he said if A = 8-00 a.m. B = weekday and Y = get up

then he said you can write:

where the dot represents logical AND.

He went on to say that if 1 represents TRUE and 0 represents FALSE

then the function can be defined in a truth table.

BAY

Logic Gates

Truth TableThe truth table has an entry for each possible

combination of inputs. For n inputs there will be 2n entries … 2

inputs = 4 entries.

A B Y

0 0

0 1

1 0

1 1

A B Y

0 0 0

0 1 0

1 0 0

1 1 1

We can have more than two inputs in which case the only time we would have a 1 out is when all the inputs are true.

Logic Gates

SymbolThe symbol adopted for the AND

function (gate) is shown belowAmerican (MIL-STD-806) British (IEC 617:12)

AA

BB

YY &

Logic Gates

OR gate

e.g. I turn on my headlights if it is dark OR it is raining

if A = dark B = raining and Y = headlights on then:

where the + sign represents logical OR.

BAY

Logic Gates

A B Y

0 0

0 1

1 0

1 1

A B Y

0 0 0

0 1 1

1 0 1

1 1 1

We can have more than two inputs in which case the only time we would have a 0 out is when all the inputs are false.

American (MIL-STD-806) British (IEC 617:12)

AA

BB

YY1

Logic Gates

NOT gate

e.g. I turn on the heating if it is NOT hot if A = hot and Y = Heating on then:

where the bar represents logical NOT.

AY

Logic Gates

We can only have one input and the output is always the opposite sign.


A Y

0

1

1

0

AA

YY 1

Logic Gates

Using these three gates we can design any logic circuit.

We will define three additional gates which aid circuit design.

Logic Gates

Exclusive OR EXOR gate

A B Y

0 0

0 1

1 0

1 1

where the sign represents logical EXOR.

BAY

A B Y

0 0 0

0 1 1

1 0 1

1 1 0

Note that the normal OR includes the case where we have both inputs true. The EXOR does not include this case. For more than two inputs the gate is defined as: The output is TRUE if we have an odd number of inputs TRUE

Logic Gates

The symbol adopted for the EXOR function (gate) is shown below


A

B

Y=1

A

BY

Logic Gates

Not AND NAND gate

A B Y

0 0

0 1

1 0

1 1

where the dot and bar represents logical NAND.

BAY 1

1

1

0

We can have more than two inputs in which case the only time we would have a 0 out is when all the inputs are true.


A

B

Y&A

BY

Logic Gates

Not OR NOR gate

A B Y

0 0

0 1

1 0

1 1

where the + sign and bar represents logical NAND.

1

0

0

0

We can have more than two inputs in which case the only time we would have a 1 out is when all the inputs are false.


BAY

A A

BB

YY1

Logic Gates

Universal Gates

NAND and NOR gates are referred to as universal gates as the three basic gates can be constructed using either one of the two.

This therefore implies that all logic circuits can be constructed using either of the gates.

The notes show this process for NAND only but it can be shown for NOR also.

Logic Gates

NOT using NANDs onlyA B Y

0 0 1

0 1 1

1 0 1

1 1 0

The Truth Table is for a NAND gateIf we tie the inputs of a NAND together then we limit the possible input combinations to two, 1 1 and 0 0. These are shown on the table now if the input is 0 the output is 1 and vice versa – a NOT gate

AY

Logic Gates

AND using NANDs only

As a NAND is simply an AND followed by a NOT gate (inverter) we can simply use a NAND followed by NOT.

A

B

Y

Note – more than one NAND gate to produce the desired AND gate.

Logic Gates

OR using NANDs only

0 0 0

0 1 1

1 0 1

1 1 1

A B BA

This is our desired OR gate

Logic Gates

OR using NANDs only

0 0 0 1 1

0 1 1 1 0

1 0 1 0 1

1 1 1 0 0

A B BA A B

If we now add NOT A and NOT B into our table

Logic Gates

OR using NANDs only

0 0 0 1 1 1

0 1 1 1 0 0

1 0 1 0 1 0

1 1 1 0 0 0

A B BA A B BA

If these are now ANDed together

Logic Gates

OR using NANDs only

0 0 0 1 1 1 0

0 1 1 1 0 0 1

1 0 1 0 1 0 1

1 1 1 0 0 0 1

A B BA A B BA BA

Finally if we invert our result we see that the 3rd and 7th column are identical. This means that if we invert the inputs then NAND then we will end up with the OR function.

Logic Gates

OR using NANDs only

A

B

Y

Let us examine the way in which logic gates can be used to realise logic circuits:

Logic Gates

ExampleA drill (D) is to operate if we are in automatic (A) and

the system (S) is running or if we are in manual (M) and a button (B) is pressed or if an override (O) input is not operated.

The boolean (logic) expression for this can be written

in the following way: OBMSAD A

S

M

B

O

D

This can be constructed in the

following way:

At this point let us examine different logic integrated circuits (I.C.s) families which can be used to construct logic circuits.

Logic Gates

Logic FamiliesTransistor-Transistor Logic (TTL) is a class of

digital circuits built from bipolar junction transistors (BJT), and resistors. It is called transistor-transistor logic because both the logic gating function (e.g. AND) and the amplifying function are performed by transistors (contrast this with RTL and DTL).

Logic Gates

Transistor Transistor Logic TTLprefix 74 e.g. 7400Quad 2-input NAND

More Specifically MM74XXX00P

MM Manufacturers codese.g. SN Texas Instruments

CD Harris SemiconductorsDM Fairchild SemiconductorsM SGS-Thomson MicroelectronicsMC Motorola

Logic Gates

Transistor Transistor Logic TTLXXX variantse.g. L Low power

S Schottky high speedLS Low power SchottkyALS Advanced low power Schottky

Voltage range Speed Power

LS +5V 5% 10nS 2mW

ALS +5V 5% 7nS 1mW

Logic Gates

Transistor Transistor Logic TTLPrefix 54 not 74 is used for higher

specifications (normally military)

Temperature range

Voltage supply tolerance

Commercial 74 families

0 - 70ºC ±5%

Military 54 families -55 - +125ºC ±10%

Logic Gates

Transistor Transistor Logic TTLMost TTL families

An input is recognised as 1 if the input is >2VAn input is recognised as 0 if the input is <

0.8V

Noise immunity is the difference = 1.2V

A low output has a maximum output of 0.2VA high output has a minimum output of 3.3V

Logic Gates

Available TTL Gate Packages

Quad 2-input gates7400 quad 2-input NAND 7403 quad 2-input NAND with open collector outputs 7408 quad 2-input AND 7409 quad 2-input AND with open collector outputs 7432 quad 2-input OR 7486 quad 2-input EX-OR 74132 quad 2-input NAND with Schmitt trigger inputs7402 quad 2-input NOR

Logic Gates

Triple 3-input gates7410 triple 3-input NAND 7411 triple 3-input AND 7412 triple 3-input NAND with open collector outputs 7427 triple 3-input NOR Dual 4-input gates7420 dual 4-input NAND 7421 dual 4-input AND Others7430 8-input NAND gateHex NOT gates7404 hex NOT 7405 hex NOT with open collector outputs 7414 hex NOT with Schmitt trigger inputs

Logic Gates

Complementary Metal Oxide Semiconductor Logic CMOS

Number sequence originally from 4000 upwards but not the same as TTL

CharacteristicsDelay 50nS Power 1W Voltage 3-18VInput

Logic 1 is recognised above 2/3 SupplyLogic 0 is recognised below 1/3 Supply

OutputThe minimum for logic 1 is Supply – 0.01VThe maximum for logic 0 0.01V

Logic Gates

Available CMOS Gate Packages

Quad 2-input gates4001 quad 2-input NOR 4011 quad 2-input NAND 4070 quad 2-input EX-OR 4071 quad 2-input OR 4077 quad 2-input EX-NOR 4081 quad 2-input AND 4093 quad 2-input NAND with Schmitt trigger

inputs

Logic Gates

CMOS Gate Packages

Triple 3-input gates4023 triple 3-input NAND 4025 triple 3-input NOR 4073 triple 3-input AND 4075 triple 3-input OR Dual 4-input gates4002 dual 4-input NOR 4012 dual 4-input NAND 4072 dual 4-input OR 4082 dual 4-input AND 4069 hex NOT (inverting buffer)

Logic Gates

Developments in TTL and CMOSOften there are different pin-outs in the two family

types.

CMOS chips are available which are the same numbers due to the popularity of TTL.

74HC High speed CMOS operating 2V to 6V74HCT High speed CMOS with TTL compatible

supplies74ACT Advanced CMOS with TTL compatible levels

and pin-outs74AC Advanced CMOS with CMOS compatible

levels and TTL pin-outs

Logic Gates

Logic Problem.Getting back to our example, we can see that

we would require:2 x 2-input AND 7408 (4 x 2-input AND)

4081 (4 x 2-input AND)1 x inverter (NOT) 7404 (6 x inverter)

4069 (6 x inverter)1 x 3-input OR Not available?

4075 (3 x 3-input OR)

This is a total of 3 chips and we end up not using 9 gates within the packages.

Logic Gates

Convert the circuit to NAND only.

ORAND

AND

NOT

1 2 3

4 5 6 7

8 9

Note. We require:8 x 2-input NAND 2 x 74001 x 3-input NAND 1 x 7410

again 3 chips. Logic Gates

BUT By observation we can see that NANDs 2

and 3 simply invert 1’s output then invert it again. This means that they cancel each other out and can be removed.

This is also true for NANDs 5 and 6 and NANDs 8 and 9, leaving us with

Logic Gates

This requires: 2 x 2-input NAND 1 x 74001 x 3-input NAND 1 x 7410With a little understanding of logic gates we

can reduce the requirements to only one chip by using the fact that:

So we need:3 x 3-input NANDs 1 x 7410

Logic Gates

Note.

Conversions from AND, OR, NOT to NAND only rarely produce a less complex circuit but normally the complexity is similar. The advantage lies in the fact that NAND chips are readily available and are inexpensive due to the number sold and that any gates left over can be used in other circuits as all circuits use the same gate types.

Logic Gates

Logic Circuits TTL and CMOS

Transistor Transistor Logic (TTL) NAND Gate.

R1R2

R3

R4

Q1 Q2

Q3

Q4

D

F

abc

Logic Gates

Complementary Metal Oxide Semiconductor CMOS NOR gate

Output

Input A

Input B

Vs+

Q1

Q2

Q3

Q4

Logic Gates

Technology Silicon gate

CMOS

Metal gateCMOS

StdTTL

Low-power

SchottkyTTL

Schottky

TTL

Advanced

Low –power

SchottkyTTL

AdvancedSchottky

TTL

Device series SN74HC 4000 SN74 SN74LS SN74AS SN74ALS SN74AS

Power diss per gate (mW)

StaticAt 100kHz

0.00000250.17

0.0010.1

1010

22

1919

11

8.58.5

Progation delay time

(nS)

8 105 10 10 3 4 1.5

Maximun clock (MHz)

40 12 35 40 125 70 200

Maximum output

drive (mA)

4 1.6 16 8 20 8 20

Fan out LS loads

Same series10*

4*

4010

2020

5010

2080

5040

Maximum input

current(mA)

0.0001 -0.0001 -1.6 -0.4 -2.0 -0.1 -0.5* dependant on frequencyLogic Gates

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© 2009 University of Wales Newport

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Logic Gates