Interfacing ics for microprocessor

PERIPHERALS AND INTERFACING

Prepared By,R-THANDAIAH PRABU M.E.,

Lecturer - [email protected]

65,536 possible I/O ports

Data transfer between ports and the processor is over data bus

8088 uses address bus A[15:0] to locate an I/O port

AL (or AX) is the processor register that takes input data (or provide output data)

I/O I/O I/O

Data bus

Address bus A[15:0]

AL

AX

8088

Introduction (cont’d)

Introduction

• I/O devices serve two main purposes– To communicate with outside world– To store data

• I/O controller acts as an interface between the systems bus and I/O device– Relieves the processor of low-level details– Takes care of electrical interface

• I/O controllers have three types of registers– Data– Command– Status

Introduction (cont’d)

Introduction (cont’d)• To communicate with an I/O device, we need

– Access to various registers (data, status,…)• This access depends on I/O mapping

– Two basic ways

» Memory-mapped I/O

» Isolated I/O

– A protocol to communicate (to send data, …)• Three types

– Programmed I/O

– Direct memory access (DMA)

– Interrupt-driven I/O

Accessing I/O Devices• I/O address mapping

– Memory-mapped I/O• Reading and writing are similar to memory read/write • Uses same memory read and write signals• Most processors use this I/O mapping

– Isolated I/O• Separate I/O address space• Separate I/O read and write signals are needed• Pentium supports isolated I/O

– 64 KB address space» Can be any combination of 8-, 16- and 32-bit I/O ports

– Also supports memory-mapped I/O

Memoryaddressingspace

I/Oaddressingspace

I/O

Memory addressingspace

00000

FFFFF

0000

FFFF

00000

FFFFF

Direct I/O Memory-mapped I/O

Accessing I/O Devices (cont’d)• Accessing I/O ports in 80x86

– Register I/O instructionsin accumulator, port8 ; direct format

– Useful to access first 256 ports

in accumulator,DX ; indirect format– DX gives the port address

– Block I/O instructions• ins and outs

– Both take no operands---as in string instructions

• ins: port address in DX, memory address in ES:(E)DI• outs: port address in DX, memory address in ES:(E)SI

8088 Port Addressing Space

Addressing SpaceFFFF

0000

00F8

00FF

Accessed directly byinstructions

Accessed throughDX

Accessing directly by instructions

IN AL, 80HIN AX, 6HOUT 3CH, ALOUT 0A0H, AX

Accessing through DX

IN AL, DXIN AX, DXOUT DX, ALOUT DX, AX

Input Port Implementation

8088

Data Bus

Address busDecoder

InputGating device

Other control signals

— The outputs of the gating device are high impedance when the processor is not accessing the input port

— When the processor is accessing the input port, the gating device transfers input data to CPU data bus

— The decoding circuit controls when the gating device has high impedance output and when it transfers input data to data bus


Circuit Implementation

Data bus Input dataTri-statebuffer

CE

RD IO/M

A7A6A5A4A3A2A1A0


Output Port Implementation

Circuit Implementation

Data bus Output dataLatch

CLK

WR IO/M

A7A6A5A4A3A2A1A0

Output Port Implementation

An Example I/O Device

• Keyboard– Keyboard controller scans and reports

– Key depressions and releases

• Supplies key identity as a scan code– Scan code is like a sequence number of the key

» Key’s scan code depends on its position on the keyboard

» No relation to the ASCII value of the key

Interfacing the Keyboard to 8051 microcontroller

• The key board here we are interfacing is a matrix keyboard. This key board is designed with a particular rows and columns. These rows and columns are connected to the microcontroller through its ports of the micro controller 8051. We normally use 8*8 matrix key board. So only two ports of 8051 can be easily connected to the rows and columns of the key board.

• When ever a key is pressed, a row and a column gets shorted through that pressed key and all the other keys are left open. When a key is pressed only a bit in the port goes high. Which indicates microcontroller that the key is pressed. By this high on the bit key in the corresponding column is identified.

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• Once we are sure that one of key in the key board is pressed next our aim is to identify that key. To do this we firstly check for particular row and then we check the corresponding column the key board.

• To check the row of the pressed key in the keyboard, one of the row is made high by making one of bit in the output port of 8051 high . This is done until the row is found out. Once we get the row next out job is to find out the column of the pressed key. The column is detected by contents in the input ports with the help of a counter. The content of the input port is rotated with carry until the carry bit is set.

• The contents of the counter is then compared and displayed in the display. This display is designed using a seven segment display and a BCD to seven segment decoder IC 7447.

• The BCD equivalent number of counter is sent through output part of 8051 displays the number of pressed key.

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Circuit diagram of INTERFACING KEY BOARD TO 8051.

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Circuit diagram of INTERFACING KEY BOARD TO 8051.

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• Keyboard is organized in a matrix of rows and columns as shown in the figure. The microcontroller accesses both rows and columns through the port.

• The 8051 has 4 I/O ports P0 to P3 each with 8 I/O pins, P0.0 to P0.7,P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7. The one of the port P1 (it understood that P1 means P1.0 to P1.7) as an I/P port for microcontroller 8051, port P0 as an O/P port of microcontroller 8051 and port P2 is used for displaying the number of pressed key.

• Make all rows of port P0 high so that it gives high signal when key is pressed.

• See if any key is pressed by scanning the port P1 by checking all columns for non zero condition.

• If any key is pressed, to identify which key is pressed make one row high at a time.

• Initiate a counter to hold the count so that each key is counted.

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• Check port P1 for nonzero condition. If any nonzero number is there in [accumulator], start column scanning by following step 9.

• Otherwise make next row high in port P1.

• Add a count of 08h to the counter to move to the next row by repeating steps from step 6.

• If any key pressed is found, the [accumulator] content is rotated right through the carry until carry bit sets, while doing this increment the count in the counter till carry is found.

• Move the content in the counter to display in data field or to memory location

• To repeat the procedures go to step 2.

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A “short list” of embedded systems

And the list goes on and on

Anti-lock brakesAuto-focus camerasAutomatic teller machinesAutomatic toll systemsAutomatic transmissionAvionic systemsBattery chargersCamcordersCell phonesCell-phone base stationsCordless phonesCruise controlCurbside check-in systemsDigital camerasDisk drivesElectronic card readersElectronic instrumentsElectronic toys/gamesFactory controlFax machinesFingerprint identifiersHome security systemsLife-support systemsMedical testing systems

ModemsMPEG decodersNetwork cardsNetwork switches/routersOn-board navigationPagersPhotocopiersPoint-of-sale systemsPortable video gamesPrintersSatellite phonesScannersSmart ovens/dishwashersSpeech recognizersStereo systemsTeleconferencing systemsTelevisionsTemperature controllersTheft tracking systemsTV set-top boxesVCR’s, DVD playersVideo game consolesVideo phonesWashers and dryers

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• A programmable keyboard and display interfacing chip.

• Scans and encodes up to a 64-key keyboard. And Controls up to a 16-digit numerical display.

• Keyboard section has a built-in FIFO 8 character buffer.

• The display is controlled from an internal 16x8 RAM that stores the coded display information.

• 8279 has 8 control words to be considered before It is programmed

Programmable Keyboard/Display Interface - 8279

SJCET 0 DATA 1 CONTROL

CHIP SELECT

DATA BUS

CONTROL STROB

SHIFT KEY

Interrupt request

OUTPUT DISPLAY

Scan line

RETURN LINE

RETURN LINE

RETURN LINE

BLANK DISPLAY

3 Mhz

PIN DESCRIPTION

Interfacing the 8279 to the Microprocessor

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• The 8279 is decoded to function at 8-bit I/O address 10H & 11H

• 10H – data port

• 11H – control port

• PAL16l8 is used to decode the I/O address for 8279

• A0 selects either the data or control port

• IRQ, since it is a interrupt pin, this signal is not connected to microprocessor.

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8279 interfaced to 8088 microprocessor :

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Keyboard Interface:

• The keyboard matrix can be any size from 2x2 to 8x8.

• The I/O port number decoded is the same, 10H & 11H

• The 74LS138 drives active low column strobe signals for the keyboard on one line at a time .

• Selection Pins SL2-SL0 sequentially scan each column of the keyboard

• The internal circuitry of 8279 scans RL pins, searches for key closure.

• RL pins incorporate internal pull-ups, no need for external resistor pull-ups.

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Programming the Keyboard Interface :

• before any keystroke is detected, the 8279 must be programmed

• the first 3 bits of the number sent to the control port (11H) select

one of the 8 different control words

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Programming the Keyboard Interface :

Control Word Description:

• First three bits given below select one of 8 control registers (opcode).

000DDMMM

• Mode set: Opcode 000.

DD sets displays mode.

MMM sets keyboard mode.

• DD field selects either:

• 8- or 16-digit display

• Whether new data are entered to the rightmost or leftmost display position.

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I/O Interface

• Control Word Description:• MMM field:

• Encoded Mode: SL outputs are active-high, follow binary bit pattern 0-7 or 0-15 depending on 8 or 16 digit display.

• Decoded Mode: SL outputs are active-low (only one of the four outputs will be low at any time).Pattern output: 1110, 1101, 1011, 0111.

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I/O Interface

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FIFO status register

•Code given in text for reading keyboard.

•Data returned from 8279 contains row data that need to be translated to ASCII:

I/O Interface

Display Interface

• Six Digit Display Interface of 8279

• The Interface uses a PAL16L8 to decode the 8279 at I/O Ports

• 20H for Data

• 21H for Control/Status

• The Segment data are supplied to the displays thru the OUTA & OUTB of 8279

• Bits are buffered by a segment driver (2003A) to drive the segment inputs to the display

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I/O Interface

Six Digit Display Interface of 8279

8251 UART

• Universal asynchronous receiver transmitter (UART) : provides serial communication.

• 8251 functions are integrated into standard PC interface chip.– 8255 used to a be a parallel interface

• Allows many communication parameters to be programmed.

Serial communication

• Characters are transmitted separately:

time

bit 0 bit 1 bit n-1

No char

start stop...

Serial communication parameters

• Baud (bit) rate.

• Number of bits per character.

• Parity/no parity.

• Even/odd parity.

• Length of stop bit (1, 1.5, 2 bits).

8251 CPU interface

CPU 8251

status(8 bit)

data(8 bit)

serialport

Tx /Rx

Programming I/O

• Two types of instructions can support I/O:– special-purpose I/O instructions;– memory-mapped load/store instructions.

• Intel x86 provides in, out instructions. Most other CPUs use memory-mapped I/O.

• I/O instructions do not preclude memory-mapped I/O.

8251 USART Interface

A7A6A5A4A3A2A1

IO/M

D[7:0]

RD RD

WR WRA0 C/D

CLK CLKTxC

RxC

TxD

RxD

8251 RS232

Programming 8251

8251 mode register

7 6 5 4 3 2 1 0 Mode register

Number of Stop bits

00: invalid01: 1 bit10: 1.5 bits11: 2 bits

Parity0: odd1: even

Parity enable0: disable1: enable

Character length

00: 5 bits01: 6 bits10: 7 bits11: 8 bits

Baud Rate

00: Syn. Mode01: x1 clock10: x16 clock11: x64 clock

Programming 8251

8251 command register

EH IR RTS ER SBRK RxE DTR TxE command register

TxE: transmit enableDTR: data terminal ready, DTR pin will be lowRxE: receiver enableSBPRK: send break character, TxD pin will be lowER: error resetRTS: request to send, CTS pin will be lowIR: internal resetEH: enter hunt mode

Programming 8251

8251 status register

DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY status register

TxRDY: transmit readyRxRDY: receiver readyTxEMPTY: transmitter emptyPE: parity errorOE: overrun errorFE: framing errorSYNDET: sync. character detectedDSR: data set ready

PROGRAMMABLE DMA CONTROLLER 8257

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DMA• Direct memory access (DMA)

– Problems with programmed I/O• Processor wastes time polling

– In our example

» Waiting for a key to be pressed,

» Waiting for it to be released

• May not satisfy timing constraints associated with some devices

– Disk read or write

– DMA• Frees the processor of the data transfer responsibility

DMA Example• A hard disk data transfer rate of 5MB/s

– One byte every 200 ns !!

• A microprocessor hardly can execute even one instruction in 200 ns.– Multiple instructions would be required to

accomplish data transfer• read the byte from the hard disk• place it in memory• increment a memory pointer• test for another byte to read

DMA

DMA

• DMA is implemented using a DMA controller– DMA controller

• Acts as slave to processor

• Receives instructions from processor

• Example: Reading from an I/O device– Processor gives details to the DMA controller

» I/O device number

» Main memory buffer address

» Number of bytes to transfer

» Direction of transfer (memory I/O device, or vice versa)

DMA• Steps in a DMA operation

– Processor initiates the DMA controller • Gives device number, memory buffer pointer, …

– Called channel initialization• Once initialized, it is ready for data transfer

– When ready, I/O device informs the DMA controller• DMA controller starts the data transfer process

– Obtains bus by going through bus arbitration– Places memory address and appropriate control signals– Completes transfer and releases the bus– Updates memory address and count value– If more to read, loops back to repeat the process

– Notify the processor when done• Typically uses an interrupt

I/O Data Transfer (cont’d)

DMA controller details

8255 Programmable Peripheral Interface


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• 8255 PPI has three 8-bit registers• Port A (PA)

• Port B (PB)

• Port C (PC)

– These ports are mapped as follows8255 register Port address

PA (input port) 60H

PB (output port) 61H

PC (input port) 62H

Command register 63H


Data bus

8088

D[7:0]

A0A1

RDWR

RESET

CS

Control port

PA[7:0]

PB[7:0]

PC[7:0]

A7A6A5A4A3A2

IO/MA1 A0 Port

0 00 11 01 1

PAPBPCControl

• Mapping I/O ports is similar to mapping memory– Partial mapping– Full mapping

• Keyboard scan code and status can be read from port 60H– 7-bit scan code is available from

• PA0 – PA6

– Key status is available from PA7• PA7 = 0 – key depressed• PA0 = 1 – key released

I/O Data Transfer• Data transfer involves two phases

– A data transfer phase• It can be done either by

– Programmed I/O– DMA

– An end-notification phase• Programmed I/O• Interrupt

• Three basic techniques– Programmed I/O– DMA– Interrupt-driven I/O

I/O Data Transfer (cont’d)

• Programmed I/O– Done by busy-waiting

• This process is called polling

• Example– Reading a key from the keyboard involves

• Waiting for PA7 bit to go low – Indicates that a key is pressed

• Reading the key scan code• Translating it to the ASCII value• Waiting until the key is released

Programming 8255

8255 has three operation modes: mode 0, mode 1, and mode 2

Programming 8255

Mode 0:

— Ports A, B, and C can be individually programmed as input or output ports— Port C is divided into two 4-bit ports which are independent from each other

Mode 1:

— Ports A and B are programmed as input or output ports— Port C is used for handshaking

PA[7:0]

STBA

IBFA

INTRAPC3PC5PC4

PB[7:0]

STBB

IBFB

INTRBPC0PC1PC2

PC6, 7

8255

PA[7:0]

OBFA

ACKA

INTRAPC3PC6PC7

PB[7:0]

OBFB

ACKB

INTRBPC0PC1PC2

PC4, 5

8255

Programming 8255

Mode 2:

— Port A is programmed to be bi-directional— Port C is for handshaking— Port B can be either input or output in mode 0 or mode 1

PA[7:0]

OBFA

ACKA

INTRA

PC4

PC6PC7

STBA

IBFA

PC0

PC3PC58255

PC1

PC2

PB[7:0]

In Out In OutIn Out

Mode 0

STBB OBFB IBFB ACKB

INTRB INTRB

Mode 1

INTERRUPT INTRODUCTION• An interrupt is an event which informs the CPU that its

service (action) is needed.

• Sources of interrupts:

– internal fault (e.g.. divide by zero, overflow)

– software

– external hardware :

• maskable

• nonmaskable

– reset

Basic Procedure for Processing Interrupts

• When an interrupt is executed, the mp:

– finishes executing its current instruction (if any).

– saves (PUSH) the flag register, IP and CS register in the stack.

– goes to a fixed memory location.

– reads the address of the associated ISR.

– Jumps to that address and executes the ISR.

– gets (PULL) the flag register, CS:IP register from the stack.

– continues executing the previous job (if any).

8088/86 Hardware Interrupts pins

INTR: Interrupt Request. – Input signal into the CPU– If it is activated, the CPU will finish the current instruction and

respond with the interrupt acknowledge operation

• NMI: NonMaskable interrupt. – Input signal– Examples of use: power failed. Memory error

• INTA: Interrupt Acknowledge. – Output signal

Programmable Interrupt Controllers (PIC)

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8259 Chip

• The Intel 8259 is a family of Programmable Interrupt Controllers (PIC) designed and developed for use with the Intel 8085 and Intel 8086 microprocessors. The 8259 acts as a multiplexer, combining multiple interrupt input sources into a single interrupt output to interrupt a single device.

Pin description• 8-bit bi-directional data bus, one address line is needed,

PIC has two control registers to be programmed

• The direction of data flow is controlled by RD and WR.

• CS is as usual connected to the output of the address decoder.

• Interrupt requests are output on INT which is connected to the INTR of the processor. Int. acknowledgment is received by INTA.

• IR0-IR7 allow 8 separate interrupt requests to be inputted to the PIC.

• sp/en=1 for master , sp/en=0 for slave.

• CAS0-3 inputs/outputs are used when more than one PIC to cascaded.

• It is a tool for managing the interrupt requests.

• 8259 is a very flexible peripheral controller chip:

– PIC can deal with up to 64 interrupt inputs

– interrupts can be masked

– various priority schemes can also programmed.

• originally (in PC ) it is available as a separate IC

• Later the functionality of (two PICs) is in the motherboards chipset.

• In some of the modern processors, the functionality of the PIC is built in.

• A Programmable Interrupt Controller (PIC) is a device which allows priority levels to be assigned to its interrupt outputs. When the device has multiple interrupt outputs to assert, it will assert them in the order of their relative priority. Common modes of a PIC include hard priorities, rotating priorities, and cascading priorities. PIC often allow the cascading of their outputs to inputs between each other.

• PIC typically have a common set of registers: • Interrupt Request Register (IRR), In-Service Register (ISR), Interrupt Mask

Register (IMR).

– The IRR specifies which interrupts are pending acknowledgement, and is typically a symbolic register which can not be directly accessed.

– The ISR register specifies which interrupts have been acknowledged, but are still waiting for an End Of Interrupt (EOI).

– The IMR specifies which interrupts are to be ignored and not acknowledged.

All interrupt requests must pass through the PIC’s interrupt request register (IRR) and interrupt mask register (IMR). If put in service, the appropriate bit of the in-service (IS) register is set.

8259 Internal Diagram

Basic Interrupt Event• External device sends an interrupt signal, to one of the Interrupt Request (IR) pin, or an internal interrupt

occurs.

• The 8259 Chip signal to the CPU the interrupt via the INT pin.

• The CPU finishes the present instruction and sends Interrupt Acknowledge (INTA).

• The interrupt type is sent to the CPU via the Data bus.

• The contents of the flag registers are pushed onto the stack.

• Both the interrupt and flags are cleared. This disables the IR pin.

• The contents of the code segment register (CS) are pushed onto the Stack.

• The contents of the instruction pointer (IP) are pushed onto the Stack.

• The interrupt vector contents are fetched, from and then placed into the IP and into the CS so that the next instruction executes at the Interrupt Service Routine (ISR) addressed by the interrupt vector.

• While returning from the interrupt-service routine by the Interrupt Return (IRET) instruction, the IP, CS and Flag registers are popped from the Stack and return to their state prior to the interrupt.

Modes

• Fully Nested mode

• Special Fully Nested mode

• Nonspecific Rotating

• Specific Rotating

• Special Mask

• Polling

Control Word (initialization)

Operation Command Words

• After the Initialization Command Words (ICWs) are programmed into the 8259, the chip is ready to accept interrupt requests at its input lines. However, during the 8259 operation, a selection of algorithms can command the 8259 to operate in various modes through the Operation Command Words.

Example of two cascaded PICs

OPERATION

• PIC is to be initialized and programmed to control its operation.

• The operation in simple words:

when an interrupt occurs , the PIC determines the highest priority, activates the processor via its INTR input, and sends the type number onto the data bus when the processor acknowledges the interrupt.

• Priority:

What is used in PC is fully nested mode. That is the lowest numbered IRQ input has highest priority. Lower priority interrupts will not be forwarded to the processor until the higher priority interrupts have been serviced.

ICW1, ICW2

ICW3, ICW4

8259 in PC XT

ICW1: 13HICW2: 08HICW3: 09H

Interrupt Sources in PC

ADC & DAC

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Why ADC ?• Digital Signal Processing is more popular

– Easy to implement, modify– Low cost

• Data from real world are typically Analog

• Needs conversion system – from raw measurements to digital data– Consists of

• Amplifier, Filters• Sample and Hold Circuit, Multiplexer• ADC

ADC

• Analog-to-Digital converter (ADC):A circuit that converts an analog voltage to digital.

Analog to Digital Conversion ADC

•

N (MAX) bitADC

output code = n0110001010001001001000101011:::

Input voltage = V)

V+ref

V-ref

ADC Major characteristics

• n=converted code, V=input voltage,

• The linearity measures how well the transition voltages lie on a straight line.

• The differential linearity measures the equality of the step size.

integer

1,where ,

2 2 1

. 0, 10 , see the figure on next page.

ref ref refN

ref

V V V Vn V

V

e g V V mV

Analog to digital converter example

• Convert an analog level to digital output

• e.g. V-ref=0V, V=10mV.

ADC

• Conversion Time: The time required to convert an analog voltage to digital.

• For an 8-bit ADC:Output = Vin x 255

Vref

Conversion rate=inverse of conversion time

Converter Errors• Offset Error

• Gain Error

• Can be eliminated by initial adjustments

• Integral Linearity Error

• Differential Linearity Error

• Nonlinear Error

– Hard to remove

Terminologies• Converter Resolution

– The smallest change required in the analog input of an ADC to change its output code by one level

• Converter Accuracy– The difference between the

actual input voltage and the full-scale weighted equivalent of the binary output code

– Maximum sum of all converter errors including quantization error

• Conversion Time– Required time (tc) before the

converter can provide valid output data

• Converter Throughput Rate– The number of times the input

signal can be sampled maintaining full accuracy

– Inverse of the total time required for one successful conversion

– Inverse of Conversion time if No S/H(Sample and Hold) circuit is used

S/H increase Performance

• S/H (Sample and Hold)

– Analog circuits that quickly samples the input signal on command and then holds it relatively constant while the ADC performs conversion

– Aperture time (ta)• Time delay occurs in S/H circuits between the time the hold command

is received and the instant the actual transition to the hold mode takes place

• Typically, few nsec

Converting bipolar to unipolar• Using unipolar converter when

input signal is bipolar

– Scaling down the input– Adding an offset

• Bipolar Converter

– If polarity information in output is desired

– Bipolar input range• Typically, 0 ~ 5V

– Bipolar Output• 2’s Complement• Offset Binary• Sign Magnitude

• Input signal is scaled and an offset is added

scaled

Addoffset

ADC Various Approaches

• 3 Basic Types

• Digital-Ramp ADC

• Successive Approximation ADC

• Flash ADC

Digital-Ramp ADC

• The output of the DAC is applied to the other terminal of the comparator.

• Since the output of the DAC is increasing with the counter, it will trigger the comparator at some point when its voltage exceeds the analog input.

• The transition of the comparator stops the binary counter, which at that point holds the digital value corresponding to the analog voltage.

Digital-Ramp ADC

• Conversion from analog to digital form inherently involves comparator action where the value of the analog voltage at some point in time is compared with some standard.

• A common way to do that is to apply the analog voltage to one terminal of a comparator and trigger a binary counter which drives a DAC.

Counter Type ADC• Block diagram

• Waveform

• Operation– Reset and Start Counter– DAC convert Digital output of

Counter to Analog signal– Compare Analog input and

Output of DAC• Vi < VDAC

– Continue counting

• Vi = VDAC

– Stop counting

– Digital Output = Output of Counter

• Disadvantage– Conversion time is varied

• 2n Clock Period for Full Scale input

Tracking Type ADC

• Tracking or Servo Type– Using Up/Down

Counter to track input signal continuously

• For slow varying input

• Can be used as S/H circuit

– By stopping desired instant

– Digital Output

– Long Hold Time

• Disabling UP (Down) control, Converter generate

– Minimum (Maximum) value reached by input signal over a given period

Successive Approximation ADC

• Most Commonly used in medium to high speed Converters

• Based on approximating the input signal with binary code and then successively revising this approximation until best approximation is achieved

• SAR(Successive Approximation Register) holds the current binary value

• Block Diagram

Successive Approximation ADC• Circuit waveform

• Conversion Time– n clock for n-bit ADC

– Fixed conversion time

• Serial Output is easily generated– Bit decision are made

in serial order

Dual Slope Integrating ADC• Operation

– Integrate

– Reset and integrate

• Applications

– DPM(Digital Panel Meter), DMM(Digital Multimeter)

• Excellent Noise Rejection

– High frequency noise cancelled out by integration

– Proper T1 eliminates line noise

– Easy to obtain good resolution

Voltage to Frequency ADC• VFC (Voltage to Frequency

Converter)

– Convert analog input voltage to train of pulses

• Counter

– Generates Digital output by counting pulses over a fixed interval of time

• Low Speed• Good Noise Immunity• High resolution

– For slow varying signal

– With long conversion time

• Applicable to remote data sensing in noisy environments

– Digital transmission over a long distance

Flash ADC

• The resistor net and comparators provide an input to the combinational logic circuit, so the conversion time is just the propagation delay through the network - it is not limited by the clock rate or some convergence sequence.

Parallel or Flash ADC

• Very High speed conversion– Up to 100MHz for 8 bit

resolution– Video, Radar, Digital

Oscilloscope• Single Step Conversion

– 2n –1 comparator– Precision Resistive

Network– Encoder

• Resolution is limited– Large number of

comparator in IC

ADC080x, 8-Bit µP Compatible A/D Converters

• CMOS 8-bit successive approximation A/D converters that use a differential potentiometer ladder—similar to the 256R products.

• These A/Ds appear like memory locations or I/O ports to the microprocessor and no interfacing logic is needed.

• Differential analog voltage inputs allow increasing the common-mode rejection and offsetting the analog zero input voltage value.

• In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution.

ADC080x Features• Compatible with 8080 µP derivatives—no interfacing logic needed - access time - 135 ns

• Easy interface to all microprocessors, or operates “stand alone”

• Differential analog voltage inputs

• Logic inputs and outputs meet both MOS and TTL voltage level specifications

• Works with 2.5V (LM336) voltage reference

• On-chip clock generator

• 0V to 5V analog input voltage range with single 5V supply

• No zero adjust required

ADC080x, interfacing

D A C

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Digital-to-Analog Conversion

• When data is in binary form, the 0's and 1's may be of several forms such as the TTL form where the logic zero may be a value up to 0.8 volts and the 1 may be a voltage from 2 to 5 volts.

• The data can be converted to clean digital form using gates which are designed to be on or off depending on the value of the incoming signal.


• Data in clean binary digital form can be converted to an analog form by using a summing amplifier.

• For example, a simple 4-bit D/A converter can be made with a four-input summing amplifier.

DAC

• Parallel Interface: Transfers 8-bits (or more) at once.

• Digital-to-Analog Converter (DAC) converts 8-digital data to analog.

AD/DA (v.9a) 116

•

NMAX (bit length)

DAC

Input code n(NMAX bit Binary code)

0110001010001001001000101011::

Output voltage = Vout(n) V+ref ( High Reference Voltage)

V-ref (Low Reference Voltage)

Digital to analog converter (DAC)

DAC Formula & Resolution• Vout = Input x Vref

256 (for 8-bit)

• Vout = DAC output analog voltage

• Input = Decimal value of binary input

• Vref = Reference DC voltage

Resolution

The worst case error introduced when converting. In an 8-bit DAC, there are 255 possible steps. The resolution is the smallest step size, or 1/255, 0.39%.

Digital-to-analog conversion

reference voltage in “multiplying” DACi.e., 00...0 => 0 volts; 11....1 => k volts (slightly less)k / 2n = “step size”

0 1 2 10 1 2 1

out

2 2 2 2

2

nn

n

x x x xV k

DAC: basic equation

• At n=0, Vout(0) = V-ref

• At max. n= 2NMAX -1, – Vout cannot reach V+ref , a kind of tree-planting problem– E.g. NMAX=4, n=0, 1, 2, … 15

• Some DACs have internal reference voltage settings, some can be set externally.

( )

2out

V Vref ref

V n V nref NMAX

V n Vref

V

V-ref

DAC output V+ref

DAC: characteristics

• Glitch: A transient spike in the output of a DAC that occurs when more than one bit changes in the input code.– Use a low pass filter to reduce the magnitude– Use sample and hold circuit is a better solution

• Settling time: Time for the output to settle to typically 1/4 LSB after a change in DA output.


• 2 Basic Approaches

– Weighted Summing Amplifier

– R-2R Network Approach

Weighted Sum DAC

• One way to achieve D/A conversion is to use a summing amplifier.

• This approach is not satisfactory for a large number of bits because it requires too much precision in the summing resistors.

• This problem is overcome in the R-2R network DAC.

Weighted Sum DAC

R-2R Ladder DAC

Typical Application

Education

Interfacing ics for microprocessor