Ground bounce mtcmos

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 5, MAY 2011 763

Ground Bouncing Noise Suppression Techniques forData Preserving Sequential MTCMOS Circuits

Hailong Jiao, Student Member, IEEE, and Volkan Kursun, Member, IEEE

Abstract—Ground distribution network noise produced duringsleep-to-active mode transitions is an important reliability concernin standard multi-threshold CMOS (MTCMOS) circuits. Differentnoise-aware sequential MTCMOS circuits are explored in thispaper. A low-leakage data retention sleep mode is implementedwith smaller centralized sleep transistors to suppress the groundbouncing noise produced during reactivation events in sequentialMTCMOS circuits. Ground bouncing noise, leakage power con-sumption, data stability, and area overheads of different sequentialMTCMOS circuits are evaluated with a 90-nm CMOS technology.The peak amplitude of ground bouncing noise is reduced by up to94.16% with the noise-aware MTCMOS techniques as comparedto the conventional Mutoh flip-flop. The application space ofdifferent data retention MTCMOS circuit techniques is identifiedwith various design metrics in this paper.

Index Terms—Data retention, flip-flops (FFs), latches, lowleakage sleep mode, multi-threshold CMOS (MTCMOS), on-chipnoise, power and ground distribution networks, power gating.

I. INTRODUCTION

W ITH THE aggressive scaling of CMOS technology,the subthreshold leakage current is exponentially in-

creased [1]. One of the widely used leakage power reductionstrategies is MTCMOS [1]–[8], [10], [11]. In an MTCMOScircuit, high threshold voltage (high- ) sleep transistors(header and footer) are used to cut off the power supply or theground connection to the idle low threshold voltage (low- )circuit blocks to suppress the subthreshold leakage current asillustrated in Fig. 1.

When the MTCMOS technique is directly applied to a se-quential circuit, such as a flip-flop (FF), the data in the storageelement is lost during the sleep mode. A data-recovery process istypically necessary when the system is awakened from the sleepmode. The data recovery process during wake-up events causessignificant degradation in system performance and increases thepower consumption [5], [11]. The development of low-leakagesequential MTCMOS circuit techniques with low-cost and low-complexity data retention capability is therefore highly desir-able. Several MTCMOS FFs that provide a low-leakage datapreserving sleep mode are presented in [2]–[5] and [11].

When a conventional sequential MTCMOS circuit transi-tions from the idle mode to the active mode, high instantaneouscurrents flow through the sleep transistors. Large voltage fluc-

Manuscript received June 11, 2009; revised September 19, 2009. First pub-lished February 17, 2010; current version published April 27, 2011.

The authors are with the Department of Electronic and Computer Engi-neering, Hong Kong University of Science and Technology, Clear Water Bay,Kowloon, Hong Kong (e-mail: [email protected]; [email protected]).

Digital Object Identifier 10.1109/TVLSI.2009.2039761

tuations occur on both the real power line (power bouncingnoise) and the real ground distribution network (groundbouncing noise) as shown in Fig. 1. The employment of mul-tiple autonomous power-gating domains is preferable for amore effective control of the leakage power consumption inMTCMOS integrated circuits. Autonomous low- sequen-tial and combinational logic circuits with individual distributedsleep transistors coexist in a multi-domain MTCMOS inte-grated circuit as shown in Fig. 1. Each idle circuit block canbe individually disabled, regardless of the activity of the othercircuit blocks, to suppress the leakage currents. Bouncing noisegenerated in one power-gating domain during a wake-up eventis transferred through the shared power and ground distributionnetworks to the surrounding active circuit blocks [10]. Thenode voltages and logic states of the active circuit blocks arethereby disturbed in a multi-domain MTCMOS circuit. Theground bouncing noise is expected to become an increasinglyimportant reliability issue in future deeply scaled multi-domainMTCMOS integrated circuits with shrinking noise margins[10].

The ground bouncing noise produced by different sequentialMTCMOS circuits is characterized in this paper. The leakagepower consumption, the data stability, and the area overheads ofdifferent power gating structures with data retention capabilityare evaluated. The paper is organized as follows. The conven-tional MTCMOS flip-flop and various alternative power gatingtechniques to lower the ground bouncing noise in sequentialMTCMOS circuits are described in Section II. Experimental re-sults are presented to characterize different sequential powergating structures in Section III. This paper is summarized inSection IV.

II. DATA PRESERVING MTCMOS FLIP-FLOPS

The data is lost in the low-leakage sleep mode when the stan-dard MTCMOS circuit techniques (gated-ground, gated- ,and gated- and ground) are directly applied to a sequen-tial circuit. Various specialized power gating techniques toachieve low leakage sequential circuits with data retention ca-pability are described in this section. The conventional MutohMTCMOS FF [2], [3] is reviewed in Section II-A. The SRAMflip-flop (SRAM-FF) [5] is described in Section II-B. Differentnoise-aware power gating techniques which can suppressthe ground bouncing noise in sequential MTCMOS circuitswhile providing a low-leakage data retention sleep mode arepresented in Section II-C.

A. Conventional Mutoh MTCMOS Flip-Flop

The first-ever published MTCMOS FF with data retentioncapability (called the Mutoh-FF in this paper) is shown in Fig. 2

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764 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 5, MAY 2011

Fig. 1. Conventional multi-domain MTCMOS circuit with multiple autonomous low-�� circuit blocks with individual distributed sleep transistors. High-�� sleep transistors are represented with a thick line in the channel region. �� . �� .

Fig. 2. Mutoh-FF with data retention capability [2], [3]. High-�� transistorsare represented with a thick line in the channel region.

[2], [3]. The Mutoh-FF provides a low-leakage sleep modewhere the data is maintained in the master latch. Distributed andlocalized header and footer sleep transistors are utilized in themaster and slave latches to eliminate the sneak leakage currentpaths. Although the Mutoh-FF is capable of maintaining thedata while lowering the leakage power consumption, the circuitsuffers from high area overhead as compared to the standardsingle low- FF [5]. Furthermore, the Mutoh-FF suffersfrom high ground bouncing noise during the transitions fromthe data retention mode to the active mode, thereby seriouslydegrading the reliability of the surrounding active circuitry.

B. SRAM Flip-Flop

The SRAM-FF proposed in [5] is a fusion of a statichigh- memory cell and an MTCMOS flip-flop with thestandard gated-ground technique. An SRAM look-alike dataretention cell is combined with the slave latch to implementa low-complexity and low-leakage data retention sleep modeas illustrated in Fig. 3. A centralized footer sleep transistor isused with the SRAM-FF, thereby lowering the MTCMOS areaoverhead. The sleep signal of the footer is also used for the dataretention and restoration operations, thereby simplifying thecontrol scheme of the SRAM-FF. The technique is effective forsignificantly reducing the leakage power consumption in idlesequential circuits [5]. However, the ground bouncing noiseproduced by the SRAM-FF is not evaluated and the relatedpotential reliability concerns are not addressed in [5].

Fig. 3. SRAM-FF with data retention cell [5]. High-�� transistors are rep-resented with a thick line in the channel region.

C. Noise-Aware Power Gating Techniques

Different noise-aware MTCMOS circuit techniques orig-inally intended for combinational circuits are presented inthis section. The application space of these previously pub-lished noise-aware power gating techniques is expanded tothe sequential circuits. The effectiveness of the techniques forsuppressing the ground bouncing noise as well as the leakagecurrents while providing a data retention sleep mode in idleflip-flops is evaluated in the following sections.

A trimode power gating structure is proposed in [7] to lowerthe ground bouncing noise produced during the activation of idleMTCMOS circuits. The trimode circuit technique is a modifica-tion of the standard gated-ground MTCMOS circuits for lowernoise. A high- pMOS data preserving transistor (Parker) isconnected in parallel with the footer to implement a low-leakage data retention PARK mode in idle flip-flops as shown inFig. 4(a). During the PARK mode, the Parker is activated while

is maintained cutoff. The virtual ground line is maintained atthe threshold voltage of the Parker . The circuit is capableof lowering the leakage power consumption while retaining thedata by maintaining a reduced yet significant voltage difference

between the power supply and the virtual groundline in the PARK mode.

JIAO AND KURSUN: GROUND BOUNCING NOISE SUPPRESSION TECHNIQUES 765

Fig. 4. Implementation of a low-leakage data retention mode with different noise-aware power gating techniques. (a) Trimode power gating structure in the PARKmode [7]. (b) Dual-switch power gating structure in the HOLD mode [8]. (c) The three-transistor controlled MTCMOS circuit technique with a low-�� dozetransistor (3-L) in the DOZE mode. High-�� sleep transistors are represented with a thick line in the channel region. �� 0 V. �: active transistor. X: cutoff transistor.

A small-sized centralized footer is used with the tri-mode circuit. The current produced by the smaller footer is re-duced, thereby lowering the ground bouncing noise producedduring the transitions from the data retention mode to the ac-tive mode as compared to the Mutoh-FF. The ground bouncingnoise produced by the trimode circuit is also suppressed dueto the lower range of the voltage swing on the virtual groundline during the reactivation events as compared to the standardgated-ground MTCMOS circuits [10].

An alternative noise-aware power gating structure(dual-switch circuit technique) is described in [8]. Thedual-switch circuit technique is an extension of the standardgated- and ground MTCMOS technique. As illustrated inFig. 4(b), a low-leakage data retention HOLD mode (similarto the PARK mode in [7]) is realized by turning on and

while the header and the footer are maintainedcutoff. The leakage power consumption is reduced while thedata is preserved by maintaining a reduced yet significantvoltage difference between the virtuallines in the HOLD mode. The sizes of the header and the footerin the dual-switch circuit are minimized by utilizing centralizedsleep transistors. The ground bouncing noise produced duringthe transitions from the data retention mode to the active modeis thereby mitigated as compared to the Mutoh-FF. The totalvoltage swings on the virtual lines of the dual-switch circuitare also lower, thereby further reducing the ground bouncingnoise produced during reactivation events as compared to thestandard gated- and ground MTCMOS circuits [10].

Another alternative version of the standard gated- andground MTCMOS technique is also explored in this paper tosuppress the ground bouncing noise while implementing a dataretention sleep mode in sequential circuits. The three-transistor

controlled circuit technique is proposed in [10] to lower theground bouncing noise produced by combinational MTCMOScircuits. In this paper, the technique is applied to a FF as shownin Fig. 4(c). An additional high- or low- pMOS sleeptransistor (Dozer) is connected in parallel with the footer to im-plement a low-leakage data retention DOZE mode in sequentialMTCMOS circuits.

In the low-leakage data retention DOZE mode, the headerand the Dozer are turned on. The footer is turned off. The vir-tual power line is maintained at . The virtual groundline is stabilized at the threshold voltage of the Dozer .The leakage power consumption is reduced while the data inthe storage element is preserved since a reduced yet significantvoltage difference is maintained between the vir-tual lines in the DOZE mode. In the active mode, the footer isturned on to discharge the virtual ground line to . Thelow- sequential circuit thereby operates with high perfor-mance.

The sizes of the sleep transistors are minimized since central-ized sleep transistors are employed with the three-transistor con-trolled circuit. The ground bouncing noise is suppressed by re-ducing the instantaneous current conducted by the smaller sleeptransistors as compared to the Mutoh-FF during the transitionsfrom the low-leakage data retention mode to the active mode.The ground bouncing noise in the three-transistor controlled cir-cuit is also mitigated by lowering the range of voltage swingon the virtual lines as compared to the standard gated- andground MTCMOS circuits during the reactivation events [10].

In addition to offering a low-leakage data retention mode,the noise-aware MTCMOS techniques (the trimode, thedual-switch, and the three-transistor controlled MTCMOStechniques) also provide an optional minimum leakage deep


Fig. 5. Implementation of an optional minimum leakage deep sleep mode with different noise-aware power gating techniques. (a) Trimode power gating structure[7]. (b) Dual-switch power gating structure [8]. (c) The three-transistor controlled MTCMOS circuit technique with a low-�� doze transistor (3-L). High-�� sleep transistors are represented with a thick line in the channel region. �� 0 V. �� .� : cutoff transistor.

sleep mode as illustrated in Fig. 5. When the data in idle sequen-tial MTCMOS circuits are not required to be maintained (whenthe data can be sacrificed to minimize leakage), the trimode,the dual-switch, and the three-transistor controlled MTCMOScircuits can transition to an alternative minimum leakage deepsleep mode where the data are lost. Maximum leakage savingsare achieved by turning off the sleep transistors, the Parker, thedual switches [ and in Fig. 5(b)], and the Dozer in thedeep sleep mode at the cost of losing the presleep circuit state.

The primary focus of the works presented in [7], [8], and[10] is the application of the trimode, the dual-switch, and thethree-transistor controlled techniques to suppress the groundbouncing noise in combinational MTCMOS circuits. Thetechniques are not considered for the sequential circuits in[8] and [10]. The ground bouncing phenomenon in sequen-tial MTCMOS circuits is explored in the following sections.Leakage power consumption, hold static noise margin, andarea overheads of different MTCMOS circuit techniques areevaluated.

III. CHARACTERIZATION OF THE SEQUENTIAL

MTCMOS TECHNIQUES

The UMC 90-nm multi-threshold voltage CMOS technology[13] (High- 320 mV, low- 72 mV,high- 273 mV, low- 56 mV, and

1 V) is used in this paper for the characterization ofthe ground bouncing noise, the leakage power consumption,the data stability, and the area overheads with the differentMTCMOS techniques. Seven 32-bit shift registers are designedbased on the following techniques: the standard single low-CMOS, the Mutoh-FF [2], [3], the SRAM-FF [5], the tri-mode

MTCMOS [7], the dual-switch MTCMOS [8], the three-tran-sistor controlled MTCMOS with high- doze transistor(3-H) [10], and the three-transistor controlled MTCMOS withlow- doze transistor (3-L).

For all the techniques, the sleep transistors are sized as listedin Table I to achieve similar (within 5%) sum of setup time andClock-to- propagation delays . The sizes of thesleep transistors in the SRAM, the trimode, the dual-switch, the3-H, and the 3-L shift registers can be further reduced by ex-ploiting the mutually exclusive switching patterns (the data inthe adjacent FFs of the shift registers never switch at the sametime) [4]. Alternatively, the sleep transistors of the different FFsin the Mutoh shift register cannot be shared. Individual, dis-tributed, and localized sleep transistors are required to elimi-nate the sneak leakage paths within every Mutoh-FF [3]. Thetotal size of the sleep transistors in the Mutoh shift register istherefore significantly larger as compared to the SRAM, the tri-mode, the dual-switch, the 3-H, and the 3-L shift registers aslisted in Table I. Different tapered buffer chains are employedto provide similar signal rise and fall times to the sleep transis-tors with each technique.

Section III is organized as follows. The ground bouncingnoise with the noise-aware power-gated shift registers is char-acterized in Section III-A. The leakage power consumed bythe shift registers in the data retention mode is compared inSection III-B. The hold static noise margins of the FFs in thedata retention mode are presented in Section III-C. The areaoverheads of the shift registers are evaluated in Section III-D.A comprehensive design metric is proposed to compare theoverall electrical quality of the sequential MTCMOS circuittechniques in Section III-E.


TABLE IACCUMULATED SIZES OF THE SLEEP TRANSISTORS OF THE 32-BIT SHIFT

REGISTERS WITH DIFFERENT TECHNIQUES

A. Ground Bouncing Noise

The ground bouncing noise produced by the different se-quential MTCMOS circuits is characterized in this section.The chip-package interface model used to evaluate the groundbouncing noise is introduced in Section III-A1. The groundbouncing noise produced by different MTCMOS circuit tech-niques is compared in Section III-A2. The dependence ofground bouncing noise on transistor sizes is evaluated inSection III-A3.

1) Chip-Package Interface Model: A chip-package electricalmodel is a circuit representation of the physical characteristicsof a package [15], [16]. A package model consists of two parts:the on-chip power distribution network and the I/O lead. Theparasitics of the on-chip power distribution network are howevertypically negligible as compared to the I/O lead parasitics [12].

The complexity of the package is increased with the growingdie size, lower supply voltage, and higher power consump-tion of the CMOS integrated circuits in each new technologygeneration. Advanced packaging technologies are employedwith the complex integrated circuits such as the state-of-the-arthigh-performance microprocessors. Alternatively, more matureand lower cost packaging technologies (such as dual in-linepackage) are typically used with the medium scale integratedcircuits and embedded microcontrollers [15], [16]. The packagemodel of the commonly used and well characterized 40-pindual in-line package (DIP-40) is shown in Fig. 6. DIP-40 isassumed in this paper to evaluate the ground bouncing noisephenomenon in sequential MTCMOS circuits. The parasiticresistance, inductance, and capacitance of the DIP-40 are 0.217

, 8.18 nH, and 5.32 pF [6], [14], respectively, as illustrated inFig. 6.

2) Comparison of Ground Bouncing Noise With DifferentCircuit Techniques: The ground bouncing noise produced withdifferent circuit techniques during the transition from the dataretention mode to the active mode is evaluated in this section.The peak amplitudes of the ground bouncing noise induced onthe real ground distribution network with different techniquesare listed in Table II. The percent reductions of ground bouncingnoise produced with different techniques as compared to theMutoh shift register are shown in Figs. 7 and 8 at 25 C and110 C, respectively.

The total size of the sleep transistors is significantly largerin the Mutoh shift register as compared to the other MTCMOScircuit techniques. The Mutoh shift register therefore produceshigher instantaneous currents and higher noise during the

Fig. 6. DIP-40 used in this paper to evaluate the ground bouncing noise withdifferent techniques [6], [14].

Fig. 7. Percent reduction of ground bouncing noise produced with differentMTCMOS circuit techniques as compared to the conventional Mutoh techniqueat 25 C.

Fig. 8. Percent reduction of ground bouncing noise produced with differentMTCMOS circuit techniques as compared to the conventional Mutoh techniqueat 110 C.

transitions from the data retention mode to the active mode.The SRAM, the trimode, the dual-switch, the 3-H, and the 3-L


TABLE IIPEAK AMPLITUDES (mV) OF THE GROUND BOUNCING NOISE WITH DIFFERENT CIRCUIT TECHNIQUES

shift registers lower the peak ground bouncing noise by up to86.96%, 94.10%, 83.67%, 92.12%, and 93.20%, respectively,as compared to the Mutoh shift register during the reactivationevents at 25 C. Alternatively, up to 86.95%, 94.16%, 83.61%,91.98%, and 93.11% reductions of peak ground bouncing noiseare achieved by the SRAM, the trimode, the dual-switch, the3-H, and the 3-L shift registers, respectively, as compared tothe Mutoh shift register at 110 C.

The sizes of the sleep transistors with the trimode shift reg-ister are smaller, thereby alleviating the current surge producedduring the transition from the data retention mode to the ac-tive mode as compared to the Mutoh, the dual-switch, the 3-H,and the 3-L shift registers. Furthermore, the voltage swing onthe virtual line of the trimode shift register is lower as com-pared to the SRAM and the dual-switch shift registers duringthe transition from the data retention mode to the active mode.The trimode shift register therefore produces the lowest groundbouncing noise among the MTCMOS shift registers evaluated inthis paper. As compared to the SRAM, the dual-switch, the 3-H,and the 3-L shift registers, the trimode shift register reduces thepeak ground bouncing noise by up to 54.74%, 67.58%, 37.07%,and 34.20%, respectively, during the reactivation events at 25C. Alternatively, at 110 C, the trimode shift register lowers the

peak ground bouncing noise by up to 56.19%, 64.48%, 33.15%,and 30.85%, as compared to the SRAM, the dual-switch, the3-H, and the 3-L shift registers, respectively.

The footers are sized the same in the 3-H and the 3-L shiftregisters. The 3-H and the 3-L shift registers however employhigh- and low- Dozers, respectively. The steady-stateDOZE-mode voltage on the virtual ground line of the 3-L shiftregister is therefore lower as compared to the 3-H shift register.The lower voltage swing on the virtual ground line of the 3-Lshift register reduces the peak ground bouncing noise by up to16.37% at 25 C and by up to 15.78% at 110 C as compared tothe 3-H shift register during the transition from the low-leakagedata retention mode to the active mode.

For the dual-switch shift register, since two additionalcontrolling transistors are used, the charging and dischargingspeeds of the virtual lines are faster as compared to the 3-H,the 3-L, and the trimode shift registers during the transitionfrom the data retention mode to the active mode. Furthermore,the voltage swings on the virtual lines of the dual-switch shiftregister are larger, thereby producing a higher

peak ground bouncing noise as compared to the 3-H, the 3-L,and the trimode shift registers during the reactivation events.The 3-H and the 3-L shift registers reduce the peak amplitudeof the ground bouncing noise by up to 51.30% and 58.08%, re-spectively, as compared to the dual-switch shift register duringthe transition from the low-leakage data retention mode to theactive mode at 25 C. Alternatively, up to 51.30% and 58.08%reductions of peak ground bouncing noise are achieved by the3-H and the 3-L shift registers, respectively, as compared to thedual-switch shift register at 110 C.

The size of the sleep transistor in the SRAM shift registeris smaller as compared to the other MTCMOS shift registers.However, the voltage swing on the virtual ground line of theSRAM shift register is higher , thereby increasing thepeak amplitude of the ground bouncing noise by up to 120.99%,66.02%, and 91.87% as compared to the trimode, the 3-H, andthe 3-L shift registers, respectively, at 25 C. Alternatively, theSRAM shift register increases the peak ground bouncing noiseby up to 128.25%, 63.00%, and 93.53% as compared to thetrimode, the 3-H, and the 3-L shift registers, respectively, at110 C. The dual-switch technique increases the peak amplitudeof the ground bouncing noise by 25.19% to 47.34% at 25 C andby 22.93% to 61.56% at 110 C (depending on the sizes of thedual switches) due to the larger sleep transistors as compared tothe SRAM shift register.

3) Dependence of Ground Bouncing Noise on the TransistorSizes: The dependence of the ground bouncing noise on thetransistor sizes is evaluated in this section. The sizes of the ad-ditional controlling transistors (Parker for the trimode circuit,dual switches for the dual-switch circuit, and Dozer for the 3-Hand the 3-L circuits) determine the steady-state data retentionmode voltages on the virtual lines. The effective resistances ofthe additional controlling transistors are reduced with the in-creased transistor widths, thereby lowering the steady-state dataretention mode voltages on the virtual ground lines. Therefore,the voltage swings on the virtual ground lines of the trimode,the dual-switch, the 3-H, and the 3-L circuits are reduced withthe increased transistor widths. The steady-state data retentionmode virtual line voltages of the trimode, the dual-switch, the3-H, and the 3-L shift registers at 110 C are listed in Table III.Note that the steady-state data retention mode voltage on thevirtual power line (Virtual- ) of the dual-switch circuit in-creases with the increased widths of the dual switches. The


TABLE IIISTEADY-STATE VOLTAGES (mV) OF THE VIRTUAL LINES OF THE NOISE-AWARE

MTCMOS CIRCUITS IN THE DATA RETENTION MODE

voltage swing on the virtual power line of the dual-switch cir-cuit is therefore also reduced during the transition from the dataretention mode to the active mode.

The discharging speeds of the virtual lines of the dual-switch,the 3-H, and the 3-L circuits are enhanced with the increasedtransistor widths since the dual switches and the Dozers aremaintained active during the transition from the data retentionmode to the active mode. However, the decreased voltageswings on the virtual lines play a more important role on theamount of ground bouncing noise produced by these circuits.As listed in Table II, the ground bouncing noise produced bythe dual-switch, the 3-H, and the 3-L circuits decreases withthe increased transistor widths. Alternatively, with the trimodecircuit, the discharging speed of the virtual ground line doesnot depend on the size of the Parker since the Parker is turnedoff. As listed in Tables II and III, the ground bouncing noiseproduced by the trimode circuit decreases due to the lowervoltage swing on the virtual ground line when the size of theParker increases.

B. Leakage Power Consumption

The leakage power consumption of the 32-bit shift registersdesigned with the seven circuit techniques are characterized inthis section. The data retention sleep mode input of each shiftregister is assumed to be either “0” or “1”. The data stored ineach FF of the shift registers are assumed to be the same (eitherall “0” or all “1”). The leakage power consumed by the shiftregisters with four different combinations of idle-mode registerinput and stored-data is listed in Table IV. The percent leakagepower reductions provided by different MTCMOS circuit tech-niques in the data retention mode (as compared to the standardsingle low- shift register) at 25 C and 110 C are shownin Figs. 9 and 10, respectively.

The SRAM shift register consumes the lowest leakage poweramong the circuit techniques evaluated in this paper. The Mutohshift register consumes higher leakage power due to the signifi-cantly larger sleep transistors and the larger buffers used to drivethe sleep transistors as compared to the SRAM shift register.The SRAM shift register achieves up to 94.11% reduction inleakage power consumption as compared to the Mutoh shift reg-ister in the data retention mode.

The additional controlling transistors in the trimode, the dual-switch, the 3-H, and the 3-L circuits are turned on to maintaina reduced yet significant voltage difference between the powerand ground connections of the low- sequential circuits inthe data retention mode. Relatively larger leakage currents are

Fig. 9. Percent leakage power reduction provided by different MTCMOS cir-cuit techniques in the data retention mode as compared to the standard singlelow-�� shift register at 25 C.

Fig. 10. Percent leakage power reduction provided by different MTCMOS cir-cuit techniques in the data retention mode as compared to the standard singlelow-�� shift register at 110 C.

therefore produced by these sequential circuits in the data re-tention mode (see Fig. 4) as compared to the deep sleep mode(see Fig. 5). The low- Dozer in the 3-L circuit conductshigher leakage current, thereby consuming the highest leakagepower among the data retention sequential MTCMOS circuitsevaluated in this paper. The voltage difference between the vir-tual lines of the dual-switch circuit issmaller, thereby reducing the leakage power consumption by upto 46.93%, 49.88%, and 55.81% as compared to the trimode,the 3-H, and the 3-L circuits, respectively, in the data retentionmode. The size of the sleep transistor in the trimode circuit issmaller, thereby achieving up to 5.60% and 26.32% leakage sav-ings as compared to the 3-H and the 3-L circuits, respectively, inthe data retention mode. When the sizes of the additional con-trolling transistors in the tri-mode, the dual-switch, the 3-H, and


TABLE IVLEAKAGE POWER CONSUMPTION (nW)

Fig. 11. Circuit configuration for measuring the hold SNM of the flip-flops�� 0 V. �� .

the 3-L circuits are increased, the leakage currents conducted bythe additional controlling transistors are enhanced in the dataretention mode, thereby consuming higher leakage power as il-lustrated in Figs. 9 and 10.

C. Hold Static Noise Margin

The hold static noise margin (SNM) is the metric used to char-acterize the data stability of the FFs in the low-leakage data re-tention mode [9]. The measurement setup to characterize thenoise margins of the FFs is shown in Fig. 11. The hold staticnoise margins of the different MTCMOS FFs with data retentioncapability are listed in Table V. The normalized (with respect tothe hold SNM of the SRAM-FF at 25 C) hold static noise mar-gins of the different MTCMOS FFs are shown in Fig. 12.

The strongest data stability is provided by the SRAM-FF inthe low-leakage data retention mode as listed in Table V. Thehold static noise margins of the Mutoh and the SRAM flip-flopsare determined by the voltage transfer characteristics (VTC)of the high- inverters ( and in Figs. 2 and 3).Alternatively, the hold static noise margins of the trimode, thedual-switch, the 3-H, and the 3-L flip-flops are determined bythe VTC of the low- inverters ( and in Fig. 4)in the data retention mode. The VTC of the cross-coupledhigh- inverters have narrower transition regions, thereby

Fig. 12. Hold static noise margins of different MTCMOS techniques normal-ized to the hold SNM of the SRAM-FF at 25 C.

TABLE VHOLD STATIC NOISE MARGINS (mV) OF DIFFERENT MTCMOS TECHNIQUES

WITH DATA RETENTION CAPABILITY

enhancing the hold SNM as compared to the low- in-verters. Furthermore, since the power and ground of and


Fig. 13. Butterfly curves of the cross-coupled inverters (�� and �� ) in theSRAM-FF �� C� and the dual-switch FF (transistor size � 0.12 �mand � � 110 C). � � 1.0 V.

in the Mutoh-FF and the SRAM-FF are connected to thereal power and ground networks, the hold static noise margins(dependent on the effective supply voltage experienced by thecross-coupled inverters) are higher as compared to the trimode,the dual-switch, the 3-H, and the 3-L flip-flops. The hold SNMis enhanced by up to 1.95 , 12.4 , 1.95 , and 1.82 by theMutoh-FF as compared to the trimode, the dual-switch, the3-H, and the 3-L FFs, respectively. Similarly, the SRAM-FFincreases the hold SNM by up to 2.03 , 12.89 , 2.02 , and1.89 as compared to the trimode, the dual-switch, the 3-H,and the 3-L FFs, respectively.

For the dual-switch FF, the voltage difference between thepower and ground connections of and in the data re-tention mode is smaller as compared tothe other data retention FFs evaluated in this paper, thereby pro-viding the weakest data stability as listed in Table V and as il-lustrated in Fig. 13. When the input voltages of andincrease, the voltages on the virtual lines of the dual-switch FFare enhanced. The increased input voltages and the enhancedvirtual line voltages have opposing effects on the output voltagesof and , thereby causing a non-monotonic VTC (increases with for 0.48 V; decreases with

in the transition region; increases with the increasedfor 0.64 V 1 V) in the dual-switch FF as illustrated

in Fig. 13.For the trimode and the 3-H flip-flops, the voltage differences

between the power and ground connections of andare similar in the data retention mode, thereby achieving sim-ilar hold static noise margins. For the 3-L FF, the voltage dif-ference between the power and ground connections of and

in the data retention mode is larger due to the low-Dozer, thereby enhancing the hold SNM by up to 29.67% and28.81% as compared to the trimode and the 3-H flip-flops, re-spectively. When the sizes of the additional controlling transis-tors are increased, the voltage differences between the powerand ground connections of and in the data retentionmode are increased for the trimode, the dual-switch, the 3-H,

Fig. 14. Area overheads of different MTCMOS circuit techniques as comparedto the standard single low-�� circuit.

and the 3-L FFs (see Table III). The hold static noise marginsof these four circuit techniques are therefore enhanced with theincreased transistor size.

D. Area Overhead Comparison

The area overheads of the shift registers with different circuittechniques are evaluated by considering the accumulated sizesof the sleep transistors, the buffer chains driving the sleep tran-sistors, the additional controlling transistors (such as the Dozeror the Parker), and the data retention elements (in the Mutohand the SRAM shift registers). The widths of the Dozer, theParker, and the dual switches are assumed to be either 0.12 or28.8 m. The area overheads of the different power gating struc-tures are shown in Fig. 14 as the percent of the total transistorwidth (pMOS and nMOS) of the standard single low- shiftregister.

The trimode shift register (with a relatively small Parker) hasthe smallest area overhead among the MTCMOS techniquesevaluated in this paper. Alternatively, the area overhead of theMutoh shift register is the highest due to the larger distributedsleep transistors and the stronger buffer chains needed to drivethe sleep transistors as compared to the other circuit techniques.The SRAM, the trimode, the dual-switch, the 3-H, and the3-L shift registers reduce the area overhead by up to 88.87%,90.87%, 85.16%, 85.16%, and 85.16%, respectively, as com-pared to the Mutoh shift register.

E. Comprehensive Comparison of Different MTCMOSTechniques

The sequential MTCMOS techniques evaluated in this paperare ranked differently for various design metrics as listed inTable VI. A more comprehensive design metric is used next toevaluate the overall electrical quality of the different sequentialMTCMOS circuit techniques. The Quality Metric is shown inthe equation at the top of the page.

The SRAM-FF is identified as the most preferable circuittechnique among the sequential MTCMOS circuits evaluated inthis paper. Alternatively, the Mutoh-FF displays the lowest elec-trical quality due to the significantly increased ground bouncing


Quality Metric

TABLE VIPERFORMANCE COMPARISON OF DIFFERENT MTCMOS TECHNIQUES WITH

DATA RETENTION CAPABILITY

noise, higher leakage power consumption, and larger area over-head as compared to the other sequential MTCMOS techniquesevaluated in this paper. The Quality Metric is enhanced by

, , , , and by the SRAM-FFtechnique as compared to the Mutoh-FF, the trimode, the dual-switch, the 3-H, and the 3-L circuit techniques, respectively.

IV. CONCLUSION

The conventional Mutoh-FF provides a low-leakage dataretention sleep mode. However, the Mutoh-FF produces sig-nificant ground bouncing noise during the transitions from thedata retention mode to the active mode. Various alternativenoise-aware sequential MTCMOS circuit techniques withlow-leakage data retention capability are explored and charac-terized in this paper.

The instantaneous currents produced by the noise-awaresequential MTCMOS circuits with smaller centralized sleeptransistors are reduced, thereby significantly suppressing theground bouncing noise as compared to the Mutoh-FF duringthe transitions from the data retention mode to the active mode.The lowest ground bouncing noise is produced by the trimodetechnique among the MTCMOS circuits evaluated in thispaper. The trimode, the SRAM-FF, the 3-H, and the 3-L tech-niques suppress the ground bouncing noise by up to 94.16%,86.96%, 92.12%, and 93.20%, respectively, as compared to theMutoh shift register during the reactivation events. The lowestleakage power consumption is provided by the SRAM-FF.The MTCMOS shift register with SRAM-FFs offers up to94.11% leakage power savings as compared to the Mutoh shiftregister. Furthermore, the SRAM-FF is identified as the mostrobust circuit, providing significantly higher data stability inthe low-leakage data retention sleep mode as compared to otherMTCMOS FFs evaluated in this paper.

The attractive application space of different noise-aware se-quential MTCMOS circuit techniques is evaluated with variousimportant design metrics. The SRAM-FF is identified as themost preferable circuit with superior electrical quality amongthe sequential MTCMOS circuit techniques evaluated in thispaper.

REFERENCES

[1] V. Kursun and E. G. Friedman, Multi-Voltage CMOS Circuit Design.New York: Wiley, 2006.

[2] S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Ya-mada, “1-V power supply high-speed digital circuit technology,” IEEEJ. Solid-State Circuits, vol. 30, no. 8, pp. 847–854, Aug. 1995.

[3] J. Kao and A. Chandrakasan, “MTCMOS sequential circuits,” in Proc.IEEE Eur. Solid-State Circuits Conf., Sep. 2001, pp. 317–320.

[4] J. Kao, S. Narenda, and A. Chandrakasan, “MTCMOS hierarchicalsizing based on mutual exclusive discharge patterns,” in Proc.IEEE/ACM Design Automat. Conf., Jun. 1998, pp. 495–500.

[5] Z. Liu and V. Kursun, “New MTCMOS flip-flops with simple controlcircuitry and low leakage data retention capability,” in Proc. IEEE Int.Conf. Electron., Circuits, Syst., Dec. 2007, pp. 1276–1279.

[6] S. Kim, S. V. Kosonocky, and D. R. Knebel, “Understanding and min-imizing ground bounce during mode transition of power gating struc-tures,” in Proc. IEEE/ACM Int. Symp. Low Power Electron. Design,Aug. 2003, pp. 22–25.

[7] S. Kim, S. V. Kosonocky, D. R. Knebel, K. Stawiasz, and M. C. Pa-paefthymiou, “A multi-mode power gating structure for low-voltagedeep-submicron CMOS ICs,” IEEE Trans. Circuits Syst. II, Exp. Briefs,vol. 54, no. 7, pp. 586–590, Jul. 2007.

[8] M. H. Chowdhury, J. Gjanci, and P. Khaled, “Controlling groundbounce noise in power gating scheme for system-on-a-Chip,” in Proc.IEEE Comput. Soc. Annu. Symp. VLSI, Apr. 2008, pp. 437–440.

[9] S. A. Tawfik and V. Kursun, “Low-power and compact sequential cir-cuits with independent-gate FinFETs,” IEEE Trans. Electron Devices,vol. 55, no. 1, pp. 60–70, Jan. 2008.

[10] H. Jiao and V. Kursun, “Ground bouncing noise suppression tech-niques for MTCMOS circuits,” in Proc. IEEE Asia Symp. QualityElectron. Design, Jul. 2009, pp. 64–70.

[11] V. Kursun, S. A. Tawfik, and Z. Liu, “Leakage-aware design ofnanometer SoC,” in Proc. IEEE Int. Symp. Circuits Syst., May 2007,pp. 3231–3234.

[12] P. Heydari and M. Pedram, “Ground bounce in digital VLSI circuits,”IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 2, pp.180–185, Apr. 2003.

[13] United Microelectronics Corporation, Hsinchu, Taiwan, “UMC90 nanometer CMOS technology,” 2009. [Online]. Available:http://www.umc.com/english/process/g/asp

[14] The Metal Oxide Semiconductor Implementation Service (MOSIS),Marina del Rey, CA, “MOSIS ceramic packages,” 2009. [On-line]. Available: http://www.mosis.com/Technical/Packaging/Ce-ramic/menu-pkg-ceramic.html

[15] Intel Corporation, Santa Clara, CA, “Intel package information,” 2009.[Online]. Available: http://www.intel.com/design/packtech/pack-book.htm

[16] Advanced Micro Devices (AMD) Incorporated, Sunnyvale,CA, “AMD package technology,” 2009. [Online]. Available:http://www.amd.com/us/products/technologies/packaging.tech-nology/Pages/packaging-technology.aspx

Hailong Jiao (S’09) received the B.S. degree inelectronic engineering from Shandong University,Shandong, China, in 2004, and the M. S. degree inmicroelectronics from the Institute of Microelec-tronics, Chinese Academy of Sciences, Beijing,China, in 2008. He is currently pursuing the Ph.D.degree in electronic and computer engineeringfrom the Hong Kong University of Science andTechnology, Hong Kong, under the supervision ofProf. V. Kursun.

His research interests include the areas of lowpower and variations-tolerant integrated circuit design, multi-threshold voltageintegrated circuit design, power gating techniques, and power distributionnetwork reliability analysis. Furthermore, he also has interests in device circuitcodesign and design for manufacturability.


Volkan Kursun (S’01–M’04) received the B.S.degree in electrical and electronics engineeringfrom the Middle East Technical University, Ankara,Turkey, in 1999, and the M.S. and Ph.D. degreesin electrical and computer engineering from theUniversity of Rochester, NY, in 2001 and 2004,respectively.

He performed research on mixed-signal thermalinkjet integrated circuits with Xerox Corporation,Webster, NY, in 2000. During Summers 2001 and2002, he was with Intel Microprocessor Research

Laboratories, Hillsboro, OR, where he was responsible for the modeling anddesign of high frequency monolithic power supplies. During Summer 2008, hewas a Visiting Professor with the Chuo University, Tokyo, Japan. He servedas an Assistant Professor with the Department of Electrical and ComputerEngineering, University of Wisconsin—Madison, from August 2004 to August2008. He has been an Assistant Professor with the Department of Electronicand Computer Engineering, Hong Kong University of Science and Technology,People’s Republic of China, since August 2008. His current research interestsinclude the areas of low voltage, low power, and high performance integrated

circuit design and emerging integrated circuit technologies. He has morethan one hundred publications and five issued and two pending patents in theareas of high performance integrated circuits and emerging semiconductortechnologies. He is the author of the book Multi-Voltage CMOS Circuit Design(Wiley, 2006).

Dr. Kursun serves on the technical program and organizing committees of theIEEE/ACM International Symposium on Low Power Electronics and Design(ISLPED), the ACM/SIGDA Great Lakes Symposium on VLSI (GLSVLSI),the IEEE International Symposium on Circuits and Systems (ISCAS), theIEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC),the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), theIEEE/ACM International Symposium on Quality Electronic Design (ISQED),the IEEE/ACM Asia Symposium on Quality Electronic Design (ASQED), andthe IEEE Asian Solid-State Circuits Conference (A-SSCC). He served on theeditorial board of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART

II: EXPRESS BRIEFS from 2005 to 2008. Dr. Kursun is an Associate Editor of theJournal of Circuits, Systems, and Computers (JCSC), the IEEE TRANSACTIONS

ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, and the IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: REGULAR PAPERS.

Education

Ground bounce mtcmos