XC9500XL
XC9500XL OverviewOptimized for 3.3-V systems
0.35 micron FastFLASH technology 4 Layers of Metal compatible levels with 5.0/2.5V Reprogramming Endurance = 10,000 Charge Retention = 20 years
Meets performance requirements high fMAX = 200 MHz / fast tPD = 4 ns
Best ISP/JTAG support in industry
Best pinlocking in industry
Advanced packaging - New CSPs !
XC9500XL ArchitectureNew extra-wide function block inputs
– Uniform– Identical Functional Blocks– Identical Macrocells– Identical I/O pins – 5 ns pin-to-pin– 36 to 288 Macrocells (6400 gates)– Abundant Global Product Term Resources– Hysteresis on all inputs– Pullup/Bus Hold Option on Pins at power on – Great synthesis results– Best pinlocking results
FastCONNECT II Switch Matrix
Very High Speed Switch Matrix
2nd Generation switch matrix
Used Fast Flash technology
Greater connectability for all signals
High routability at high utilization
Software delivers high speed automatically
Substantial power reduction
XC9500XL Feedback Paths
FastCONNECT
Pin
LocalMacrocell
FastCONNECT
FB X
Macrocell
Macrocell
Pin feedback
FastCONNECT feedback
Local feedback
XC9500XL Function BlockHandles SDRAM address width with 54 inputs
highest function block fan-in on fast CPLDs
XC9500XL Macrocell
Local macrocell clock inversion control
Flexible clocking and three-state control
Product Term Allocator Cascading
2 p-terms requiredhere
5 available here
5 available here
5 native p-terms
3 available here
Total = 18requires 2 cascade timesadded to tPD
Voltage Compatibility
CORELOGIC
VCCINT = 3.3V VCCIO = 3.3V/2.5V
Note: output p-channel gives full rail swing
Voltage Compatibility 2.5/3.3/5V
5V
3.3V
Any 5V TTL
device
XC9500XL
Any 2.5/3.3V
device
VCCIO VCCINT
5V
3.3V
3.3V
2.5/3.3V
2.5V
VCCINT
XC9500XL Voltage Compatibility Summary
VIL
VIH
VOL
VOH
5V CMOS 5V TTL 3.3V LVCMOS 3.3V LVTTL 2.5V Normal
3.3V 3.3V
X XX
X
X
X
X
X
X
X
X
X
X
XX
X
X
X
EIA Standard Voltage Levels
No Power Supply Sequencing Restriction
Input Signal Hysteresis
VOH
VOL
1.40V 1.45V
VOUT
VIN (VOLTS)
(VOLTS)
50 mV
Power Optimization
67% decrease from 5V CPLDs
Low power option per macrocell
Even lower power if I/Os swing 0-2.5V
FastCONNECT II lower power than XC9500
I/Os swing full VCCIO range with p-channel pullups (shuts off attached external logic)
ISP (In System Programming)
Original XC9500 JTAG and ISP instructions
New instruction: CLAMP permits pin by pin definition of logic level
Added S/W support with XACT M1.5
Same third party and ATE support package as XC9500 CPLDs (HP, GenRAD, Teradyne)
XC9500XL Fits In Industry Standard JTAG Chains
XC9500 XC4000EX
uP
DSP
ASICXC9500
TDI
TDO
TMSTCK
Third Party ATE Support
Hewlett-Packard
Teradyne
Gen-RAD
Common Support for both Xilinx FPGAs and CPLDs.
Advanced CSP Packaging
Supports high-growthmarket segments:Communications,Computers, Consumer
Uses standard IRtechniques for mounting
to PC board
What’s Key for Pin-Locking
Must retain pinouts as the design evolves best done when the design software initially assigns pins different from pinout pre-assigning strong function of utilization in typical CPLD architectures result of both architecture and software strategy
Pin-locking is valuable eliminates or reduces PC Board rework minimizes time to market, saves money lowers designer frustration, risk
3 Keys to Pin-Locking
FunctionBlock
FastCONNECT
JTAG
Global3-State
GlobalS/R
GlobalClocks
FunctionBlock
FunctionBlock
FunctionBlock
FunctionBlock
FunctionBlock
FunctionBlock
2nd generation switch matrix:
Complete interconnect of all pins & blocks
All pin-to-pin paths at full speed
FunctionBlock
Fully PopulatedSwitch Matrix
3 Keys to Pin-Locking
ToFastCONNECT
23 Global3-State
GlobalClocks
I/O
I/O
FromFastCONNECT
54
Macrocell 1
ANDArray
Macrocell 18
ProductTermAllocator
•
Wide FunctionBlock Fan-in
Flexible MacrocellLogic Allocation
XC9500XL Supports Design Changes with Fixed Pinouts
Design Change XC9500XL Feature
Add another input FastCONNECT switch matrixpin or FB output with 100% connectivity
Add more logic in XC9500 allows expansionthe macrocell up to 90 P-terms
Add additional input 54 total inputs are available connections to the FB plus FastCONNECT
AND gate capability
Pin-Locking Compare Table
Routability Excellent Good* Poor Good
Notes: * Decreases with density
Xilinx
XC9500XL
Altera
Max7KS
Lattice
1K/2K/3K
AMD
Mach5
54
Yes
90
Yes
32
No No
No
36
No
18/24
No No
32 32
32
Fully populated switch
Maximum pterms/Mcell
Bi-directional individual
product term allocation
Function block fan-in
XC9500XL Other Features
Enhanced Data Security Features Read security bits prevent unauthorized reading Write security bits prevent accidental program/erase
Reduced power option per macrocell
3.3v/5v outputs
24 mA, 100% PCI compliant
Output Noise Reduction Slew rate control User programmable ground pin
capability
User Programmable Ground Pin
User I/O Pin
Ground Pin
User I/O Pin
Internal Logic
Additional Ground Pin• Lower ground inductance• Reduce ground noise
54-input Function Block
CLAMP instruction
2.5V/3.3V/5V I/O Capability
Invertible Local & Global P-Term Clocks and OEs
Input Hystersis +/-50mV
Bus Hold
Common ISP/JTAG Support for CPLDs/FPGAs
Superior connectivity & performance
Better control of board & system signals during ISP
Easy multi-voltage interfacing
Max number of clock & OE options
Improves noise margin; better slowsignal response
Totally controlled board initialization
One language supports all Xilinx products
Xilinx Feature System Designer Benefit
XC9500XLSystem Designer’s CPLD
Xilinx CPLD Solutions
tPD (pin-to-pin speed)
tSU (set-up speed)
Icc (supply current - typ)
Specification XC9500-5XL* XC9500-5**
tCO (clock-to-out speed)
tOE (output enable speed)
fSYS (system speed)
Voltage
5ns*
3.7ns
11mA (Low Power)18mA (Hi Perf)
3.5ns
4ns
178.6MHz
3.3V
5ns
4ns
30mA (Low Power)50mA (Hi Perf)
4ns
5ns
100MHz
5V
* XC9500XL also available in 4ns version** New 5V speed specifications (as of 9/98)
5ns COMPARISON
XC9500XL Family
9536XL
Macrocells
Usable Gates
tPD (ns)
36 72
800 1600 3200
4 5 5
196 178 178
PackagesQFPs
44PC64VQ
48CS
44PC64VQ100TQ
48CS
100TQ144TQ
144CS
288
6400
6
151
208PQ
352BG
9572XL 95144XL 95288XL
CSPs/BGA
fMAX (MHz)
144
144TQ
CPLD Solution for PC99 SDRAM Controller Example
Processor
Personal ComputerPersonal Computer SpartanXLUSB interface/
FireWireinterface
Dev
ice
Bay
MemoryXC9500XLSDRAMController
USB,FireWire
interfaces
USBUSBFireWireFireWire
Challenges Facing the Design Engineer
100 MHz minimum speed
Multiple SDRAM protocols
Sufficient address width
Clock flexibility
Resources for future expansion
Small package
HDL entry
Cost control
Minimal programming overhead
Board layout before design is complete
Design time
Three-state flexibility
3.3V/2.5V
Memory Interface Block Diagram
SDR
AM
s
Clock
WriteReset
Address[23:0] Address[11:0]
CSRASCAS
WE
Data[15:0]
Complete SDRAM Controller in a single CPLD
Mic
ropr
oces
sor
CPLD SDRAM Controller
SDRAM Interface Close-up
Address[23:0]
Data[15:0]
ADDR[11:0]
Clock
Reset
Write
CS
RAS
CAS
WE
ADDR[23:12]
ADDR[11:0]
Refresh Counter
Address DecodeChip
SelectMode
Register
State Machine
Design in VHDL, Verilog, ABEL,
etc.
Submit designto WebFITTER
Evaluateresults
1 2 3
CPLD Design on the Web
No software to load no user resources needed no license
WebFITTER software always current no upgrade CDs
Runs fast on network (minutes)
WebFITTER Intro Page
WebFITTER Activity Report
WebFITTER Report File
SDRAM Controller Implementation in XC9500XL
Results for XC95144XL
Utilization 52% of capacity available for other logic
Speed faster than required for 133 MHz clock
Lowest-cost solution
Compare to chip sets and other CPLDs