Computer and Information Sciences College /
Computer Science Department
The Processor:
Datapath and
Control
Chapter 5 The Processor: Datapath and Control
Big Picture: Where are We Now?
Performance of a machine is determined by:
ISA
CLK time
CPI
Processor design (Datapath and control) will determine:
CLK time
CPI
Single Cycle Processor
Advantage: one CLK per instruction
Disadvantage: Long cycle time
Processor (CPU)
Control (“brain”)
Datapath (“brawn”)
Arithmetic-
Logic Unit
(ALU)
Ex: What are the single cycle processor advantage and disadvantage?
REGISTER TRANSFER LANGUAGE
MICROOPERATION
The operations on the data in registers are called microoperations.
The functions built into registers are examples of microoperations Shift Load Clear Increment …
REGISTER TRANSFER LANGUAGE
For any function of the computer, the register transfer language can be
used to describe the (sequence of) microoperations
A symbolic language for describing the internal organization of
digital computers
RTL: An elementary operation performed (during one clock pulse), on the information stored in one or more registers
R f(R, R)
f: shift, load, clear, increment, add, subtract, complement,
and, or, xor, …
ALU
(f)
Registers
(R)
1 clock cycle
Ex: Define the microoperation? Define the RTL?
Implementing MIPS
We're ready to look at an implementation of the MIPS instruction set
Simplified to contain only
arithmetic-logic instructions: add, sub, and, or, slt
memory-reference instructions: lw, sw
control-flow instructions: beq, j
op rs rt offset
6 bits 5 bits 5 bits 16 bits
op rs rt rd funct shamt
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
R-Format
I-Format
op address
6 bits 26 bits
J-Format
Ex: What are the main MIPS instruction sets and its format types?
Register Transfer Language RTL
The Fetch/Execute Cycle High-level abstract view of fetch/execute implementation
use the program counter (PC) to read instruction address
fetch the instruction from memory and increment PC
use fields of the instruction to select registers to read
execute depending on the instruction
repeat…
First step is to fetch the instruction from memory
IR MEM[PC]
Ex: Write the RTL for fetch and execute for each instruction?
Overview: Processor Implementation Styles
Single Cycle
perform each instruction in 1 clock cycle
clock cycle must be long enough for slowest instruction; therefore,
disadvantage: only as fast as slowest instruction
Multi-Cycle
break fetch/execute cycle into multiple steps
perform 1 step in each clock cycle
advantage: each instruction uses only as many cycles as it needs
Pipelined
execute each instruction in multiple steps
perform 1 step / instruction in each clock cycle
process multiple instructions in parallel – assembly line
Ex: What are the Processor Implementation Styles?
Functional Elements Two types of functional elements in the hardware:
1) elements that operate on data (called combinational elements)
2) elements that contain data (called state or sequential elements)
Combinational Elements and Sequential Elements
Works as an input output function, e.g., ALU
Combinational logic reads input data from one register and writes output data to another, or same, register
read/write happens in a single cycle – combinational element cannot store data
from one cycle to a future one
Flipflops and latches are 1-bit state elements, equivalently, they are 1-bit memories
The output(s) of a flipflop or latch always depends on the bit value stored, i.e., its
state, and can be called 1/0 or high/low or true/false
The input to a flipflop or latch can change its state depending on whether it is
clocked or not…
Clock cycle
State
element
1
Combinational logic
State
element
2
State
elementCombinational logic
Combinational logic hardware units
Building a Datapath
Datapath: Elements that process data and addresses in the CPU
(Registers, ALUs, mux’s, memories….)
Build a MIPS datapath:
Fetch Instructions
Read operands and execute instructions.
PC
Instruction
memory
Instruction address
Instruction
a. Instruction memory b. Program counter
Add Sum
c. Adder
Three elements used to store and fetch instructions and increment the PC
Datapath
P C
I n s t r u c t i o n
m e m o r y
R e a d a d d r e s s
I n s t r u c t i o n
4
A d d
Ex: Draw the datapath for fetch instruction process?
Datapath for Instruction Fetch
Instruction <- MEM[PC]
PC <- PC + 4
RDMemory
ADDR
PC
Instruction
4
ADD
Ex: Write the RTL, draw the datapath and draw with color pen the dataflow
for instruction fetch process?
We don’t know if instruction
is a Branch/Jump or
one of the other instructions
until we have fetched
and interpreted the
instruction from memory
Datapath: R-Type Instruction
R[rd] R[rs] op R[rt] ; op : add; sub; or; slt ALU control
RegWrite
RegistersWrite register
Read data 1
Read data 2
Read register 1
Read register 2
Write data
ALU result
ALU
Data
Data
Register
numbers
a. Registers b. ALU
Zero5
5
5 3
InstructionRegisters
Write register
Read data 1
Read data 2
Read register 1
Read register 2
Write data
ALU result
ALU
Zero
RegWrite
ALU operation3
Two elements used to implement R-type instructions
Datapath
Ex: Write the RTL, draw the datapath for R-type instruction execution process?
:
Datapath for R-Type Instruction
add rd, rs, rt
R[rd] <- R[rs] + R[rt];
5 5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
op rs rt rd functshamt
Operation
ALU Zero
Instruction
3
Ex: Write the RTL, draw the datapath and color with pen the data flow for
R-type instruction execution process?
Datapath: Load/Store Instructions
1) Read register operands
2) Calculate address using 16-bit offset
3) Use ALU, and sign extend offset
Load: Read memory and update register
Store: write register value to memory
16 32Sign
extend
b. Sign-extension unit
MemRead
MemWrite
Data
memoryWrite data
Read data
a. Data memory unit
Address
Instruction
16 32
RegistersWrite register
Read data 1
Read data 2
Read register 1
Read register 2
Data
memoryWrite data
Read data
Write data
Sign
extend
ALU result
Zero
ALU
Address
MemRead
MemWrite
RegWrite
ALU operation3
Two additional elements used To implement load/stores
Datapath
MEM[R[rs] + sign_extend(offset)] <- R[rt]
R[rt] <- MEM[R[rs] + s_extend(offset)];
Datapath for Load Instructions
lw rt, offset(rs)
R[rt] <- MEM[R[rs] + s_extend(offset)];
Ex: Write the RTL, draw the datapath and color with pen the data flow
for load instruction execution process?
sw rt, offset(rs)
MEM[R[rs] + sign_extend(offset)] <- R[rt]
Datapath for Store Instructions
Ex: Write the RTL, draw the datapath and color with pen the data
flow for store instruction execution process?
Datapath: Branch Instruction
1) Read register operands
2) Compare operands (use ALU, subtract and check zero flag)
3) Calculate target address 1) Sign extended displacement
2) Shift left 2 places
3) PC PC+4
16 32Sign
extend
ZeroALU
Sum
Shift
left 2
To branch
control logic
Branch target
PC + 4 from instruction datapath
Instruction
Add
RegistersWrite register
Read data 1
Read data 2
Read register 1
Read register 2
Write data
RegWrite
ALU operation3
Datapath
No shift hardware required: simply connect wires from input to output, each shifted left 2 bits
Ex: Draw the datapath for branch instruction execution process?
Datapath for Branch Instruction
Ex: Write the RTL, draw the datapath and color with pen the data flow
for branch instruction execution process?
beq rs, rt, offset
if (R[rs] == R[rt]) then
PC <- PC+4 + s_extend(offset<<2)
op rs rt offset/immediate
5 5
16
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
E
X
T
N
D
16 32
Zero
ADD
<<2
PC +4 from
instruction
datapath
MIPS Datapath I: Single-Cycle
Input is either register (R-type) or sign-extended lower half of instruction (load/store)
Combining the datapaths for R-type instructions and load/stores using two multiplexors
Data is either from ALU (R-type) or memory (load)
Chapter 5 The Processor: Datapath and Control
Datapath for R-type Instruction
add rd,rs,rt 5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
32
M
U
X
MUXALUSrc
MemtoReg
Ex: Write the RTL, draw the datapath and color with pen the data flow
for R-type instruction execution process?
Datapath for Load Instruction
lw rt,offset(rs) 5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
32
M
U
X
MUXALUSrc
MemtoReg
Ex: Write the RTL, draw the datapath and color with pen the data
flow for Load instruction execution process?
Datapath for Store Instruction
sw rt,offset(rs) 5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
32
M
U
X
MUXALUSrc
MemtoReg
Ex: Write the RTL, draw the datapath and color with pen the data flow
for Store instruction execution process?
MIPS Datapath II: Single-Cycle
PC
Instruction memory
Read address
Instruction
16 32
Registers
Write register
Write data
Read data 1
Read data 2
Read register 1
Read register 2
Sign extend
ALU result
Zero
Data memory
Address
Write data
Read data
M u x
4
Add
M u x
ALU
RegWrite
ALU operation3
MemRead
MemWrite
ALUSrcMemtoReg
Adding instruction fetch
Separate instruction memory as instruction and data read occur in the same clock cycle
Separate adder as ALU operations and PC increment occur in the same clock cycle
Chapter 5 The Processor: Datapath and Control
MIPS Datapath III: Single-Cycle
PC
Instruction memory
Read address
Instruction
16 32
Add ALU result
M u x
Registers
Write register
Write data
Read data 1
Read data 2
Read register 1
Read register 2
Shift
left 2
4
M u x
ALU operation3
RegWrite
MemRead
MemWrite
PCSrc
ALUSrc
MemtoReg
ALU result
ZeroALU
Data memory
Address
Write data
Read data M
u x
Sign extend
Add
Adding branch capability and another multiplexor
Instruction address is either PC+4 or branch target address
Extra adder needed as both adders operate in each cycle
New multiplexor
Important note: in a single-cycle implementation data cannot be stored during an instruction – it only moves through combinational logic Question: is the MemRead signal really needed?! Think of RegWrite…! Ex: Draw the complete datapath for fetch and execute MIPS instruction in single cycle processor?
Datapath Executing add
add rd, rs, rt
5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
32
M
U
X
ALUSrc
MemtoReg
ADD
<<2
RD
InstructionMemory
ADDR
PC
4
ADD
ADD
M
U
X
M
U
X
PCSrc
Ex: Draw the complete datapath for fetch and execute R-type MIPS
instruction in single cycle processor and color the data flow?
Datapath Executing lw
lw rt,offset(rs)
5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
32
M
U
X
ALUSrc
MemtoReg
ADD
<<2
RD
InstructionMemory
ADDR
PC
4
ADD
ADD
M
U
X
M
U
X
PCSrc
Ex: Draw the complete datapath for fetch and execute Load MIPS
instruction in single cycle processor and color the data flow?
Datapath Executing sw
sw rt,offset(rs)
5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
32
M
U
X
ALUSrc
MemtoReg
ADD
<<2
RD
InstructionMemory
ADDR
PC
4
ADD
ADD
M
U
X
M
U
X
PCSrc
Ex: Draw the complete datapath for fetch and execute store MIPS
instruction in single cycle processor and color the data flow?
Datapath Executing beq
beq r1,r2,offset
5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
32
M
U
X
ALUSrc
MemtoReg
ADD
<<2
RD
InstructionMemory
ADDR
PC
4
ADD
ADD
M
U
X
M
U
X
PCSrc
Ex: Draw the complete datapath for fetch and execute branch MIPS
instruction in single cycle processor and color the data flow?
Processor = Datapath + Control
CPU = Datapath+ Control Control unit takes input from
the instruction code
Control unit tasks
Selecting the operations to perform (ALU control input)
write enable (possibly, read enable also) signals for each storage
element
Controlling the flow of data for each multiplexor
Control
Logic
op rs rt rd shamt funct R-format
instruction
To datapath
6 6
Ex: What are the control unit tasks?
Defining Control
Note that funct field only present in R-format instruction -
funct controls ALU only
To simplify control, define Main, ALU control separately –
using multiple levels will also increase speed – important
optimization technique
ALUop inputs will be defined
Control
Logic
Main
Control
ALU
control
op
funct
op
funct
ALU-
con ALUop
Ex: What are the main control and ALU control units inputs and outputs?
Defining ALU Control
ALUcon ALU function Instruction(s) supported
0000 AND R-format (and)
0001 OR R-format (or)
0010 add R-format (add), lw, sw
0110 subtract R-format (sub), beq
0111 set on less than R-format (slt)
1100 NOR R-format (nor)
ALUcon
A
L
U
Zero
Result
A
B
Instruction Desired
opcode ALU Action ALUOp funct ALUcon
lw add 00 xxxxxx 0010
sw add 00 xxxxxx 0010
beq subtract 01 xxxxxx 0110
R-type add 10 100000 (add) 0010
R-type subtract 10 100010 (sub) 0110
R-type logical AND 10 100100 (and) 0000
R-type logical OR 10 100101 (or) 0001
R-type set on less 10 101010 (slt) 0111
Chapter 5 The Processor: Datapath and Control
Design ALU Control
ALUOp Funct Field
a1 a0 f5 f4 f3 f2 f1 f0 ALUcon
0 0 x x x x x x 0010
x 1 x x x x x x 0110
1 x x x 0 0 0 0 0010
1 x x x 0 0 1 0 0110
1 x x x 0 1 0 0 0000
1 x x x 0 1 0 1 0001
1 x x x 1 0 1 0 0111
Operation2 (msb) =
ALUOp0 OR (ALUOp1 AND F1)
Operation1 = ALUOp1 NOR F2
Operation0 (lsb) =
ALUOp1 AND (F3 OR F0)
O p e r a t i o n 2
O p e r a t i o n 1
O p e r a t i o n 0
A L U O p 1
F 3
F 2
F 1
F 0
A L U O p 0
A L U O p
ALUcon
4th bit=0 funct
Design the Main Control derived from the instruction code
Main
Control
RegDst Branch MemRead MemtoReg ALUop MemWrite ALUSrc RegWrite
op
2
Ex: What are the main control inputs and outputs?
R-Type Memory Access Instructions Branch on Equal
beq lw sw
RegDst = 1
RegWrite = 1
ALUSrc = 0
Branch = 0
MemtoReg = 0
MemRead = 0
MemWrite = 0
ALUOp = 10
RegDst = 0
RegWrite = 1
ALUSrc = 1
Branch = 0
MemtoReg = 1
MemRead = 1
MemWrite = 0
ALUOp = 00
RegDst = X
RegWrite = 0
ALUSrc = 1
Branch = 0
MemtoReg = X
MemRead = 0
MemWrite = 1
ALUOp = 00
RegDst = X
RegWrite = 0
ALUSrc = 0
Branch = 1
MemtoReg = X
MemRead = 0
MemWrite = 0
ALUOp = 01
Design the Main Control
Ex: What are the control signals for each instruction type?
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0 0 1 0 0 0 1 0lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 1 0 0 0
beq X 0 X 0 0 0 1 0 1
*
Design the Main Control
R-format Iw sw beq
Op0
Op1
Op2
Op3
Op4
Op5
Inputs
Outputs
RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp1
ALUOpO
Signal R- lw sw beq name format Op5 0 1 1 0
Op4 0 0 0 0
Op3 0 0 1 0
Op2 0 0 0 1
Op1 0 1 1 0
Op0 0 1 1 0
RegDst 1 0 x x
ALUSrc 0 1 1 0
MemtoReg 0 1 x x
RegWrite 1 1 0 0
MemRead 0 1 0 0
MemWrite 0 0 1 0
Branch 0 0 0 1
ALUOp1 1 0 0 0
ALUOP2 0 0 0 1
Inp
uts
O
utp
uts
Truth table for main control signals
Datapath with Control II
PC
Instruction memory
Read address
Instruction [31–0]
Instruction [20 16]
Instruction [25 21]
Add
Instruction [5 0]
MemtoReg
ALUOp
MemWrite
RegWrite
MemRead
Branch
RegDst
ALUSrc
Instruction [31 26]
4
16 32Instruction [15 0]
0
0M u x
0
1
Control
AddALU
result
M u x
0
1
RegistersWrite register
Write data
Read data 1
Read data 2
Read register 1
Read register 2
Sign extend
M u x
1
ALU result
Zero
PCSrc
Data memory
Write data
Read data
M u x
1
Instruction [15 11]
ALU control
Shift left 2
ALU
Address
MIPS datapath with the control unit: input to control is the 6-bit instruction opcode field, output is seven 1-bit signals and the 2-bit ALUOp signal
Ex: Draw the complete datapath for fetch, execute with control signals
for MIPS instruction in single cycle processor?
Control Signals: R-Type Instruction
Control signals
shown in blue
1
0
0
0
1
??? Value depends on
funct
0
0
5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
I32
M
U
X
ALUSrc
MemtoReg
ADD
<<2
RD
InstructionMemory
ADDR
PC
4
ADD
ADD
M
U
X
M
U
X
PCSrc
MUX RegDst
5
rd
I[15:11]
rt
I[20:16]
rs
I[25:21]
immediate/
offset
I[15:0]
0
1
0
1
1
0
10
Ex: Draw with color pen the data flow and determine the control signals for
R-type instruction type?
5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
I32
M
U
X
ALUSrc
MemtoReg
ADD
<<2
RD
InstructionMemory
ADDR
PC
4
ADD
ADD
M
U
X
M
U
X
PCSrc
MUX RegDst
5
rd
I[15:11]
rt
I[20:16]
rs
I[25:21]
immediate/
offset
I[15:0]
0
1
0
1
1
0
10
Control Signals:lw Instruction
0
Control signals
shown in blue
0
010
1
1
1
0
1
Ex: Draw with color pen the data flow and determine the control
signals for Load instruction?
5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
I32
M
U
X
ALUSrc
MemtoReg
ADD
<<2
RD
InstructionMemory
ADDR
PC
4
ADD
ADD
M
U
X
M
U
X
PCSrc
MUX RegDst
5
rd
I[15:11]
rt
I[20:16]
rs
I[25:21]
immediate/
offset
I[15:0]
0
1
0
1
1
0
10
Control Signals:sw Instruction
0
Control signals
shown in blue
X 010
1
X
0
1
0
Ex: Draw with color pen the data flow and determine the control
signals for store instruction?
5 516
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Register File
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
DataMemory
ADDR
MemWrite
5
Instruction
I32
M
U
X
ALUSrc
MemtoReg
ADD
<<2
RD
InstructionMemory
ADDR
PC
4
ADD
ADD
M
U
X
M
U
X
PCSrc
MUX RegDst
5
rd
I[15:11]
rt
I[20:16]
rs
I[25:21]
immediate/
offset
I[15:0]
0
1
0
1
1
0
10
Control Signals: beq Instruction
Control signals
shown in blue
X
110
0
X
0
0
0
1 if Zero=1
Ex: Draw with color pen the data flow and determine the control
signals for branch instruction?
Single-Cycle Design Problems
Performance Issues
o Longest delay determines clock period
◦ Critical path: load instruction
Instruction memory → register file → ALU → data
memory → register file
o Not feasible to vary period for different instructions
o Violates design principle
o Making the common case fast
o We will improve performance by pipelining
Ex: What is the longest instruction path in single cycle processor
Summary 5 steps to design a processor
◦ 1. Analyze instruction set => datapath requirements
◦ 2. Select set of datapath components & establish clock methodology
◦ 3. Assemble datapath meeting the requirements
◦ 4. Analyze implementation of each instruction to determine setting of
control points that effects the register transfer
◦ 5. Assemble the control logic
MIPS makes it easier
◦ Instructions same size
◦ Source registers always in same place
◦ Immediate same size, location
◦ Operations always on registers/ immediates
Single cycle datapath => CPI=1, Clock Cycle Time =>Long
The MIPS architecture was designed to be pipelined
Ex: Write the five steps to design a processor?
Why MIPS is easier to implement Pipeline processor?