AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC All rights reserved, 2010, Thales Alenia Space
Tem
plate reference : 100181670S-E
N
University of Pavia
Politecnico di Milano
STARX32: A Complete On-Chip X-Ray Spectroscopy Readout System
with Imaging Capability
Presented by P. Bastia on behalf of the STARX32 team
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
CONTEXT
A Industry-University team formed in Italy to search a solution to this technological challenge
In the last decade the Detector technology became mat ure for realization oflarge 2D X-ray detector array in GaAs, CdZnTe and simil ar materials
ORIGIN OF THE PROJECT
To use these arrays in a space instrument a Read Out Integ rated Circuit ismandatory, this ROIC should be low-power, low-noise, h i-speed, highlyintegrated … and in general subjected to all limitation of space environment.
No device with these characteristics existed around 2002 when ESA started a dedicated technological program “Large Format Detector Readout ”
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
CONTEXTCONTEXT
TEAM ORGANIZATION
OVERALLPROJECT MANAGEMENT
FRONT-END SECTION DESIGN
ADC & READOUT LOGIC DESIGN
TEST EQUIPMENT DESIGN & MFG
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
CONTEXTMILANO plant, formerly:
More than 30 year experience in development of space instruments for x-rays, gamma-rays, cosmic-rays, and scientific payload in general.
IBIS GAMMA RAY IMAGER
AGILEGAMMA RAYOBSERVATORY
ALTEA COSMIC RAY DETECTOR
PLANCK LFIHIGHLY INTEGRATED READOUT ELECTRONICS
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
CONTEXT
Politecnico di Milano, Department of Electronics Engi neeringand Information Science
• particular skills in designing ultra low noise front end for X-ray detectors (more than 100 papers on the subject)
University of Pavia, Integrated Microsystem Laborator y
• member EUROPRACTICE
• large experience in mixed-signal ASIC development
UNIVERSITY TEAMS
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
REQUIREMENTS REVIEW
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
REQUIREMENTS REVIEW
≈ 500 µW/channelPower
consumption
~106 cps total rate capability> 10 kcps/channelEvent rate
system-on-a-chip including all readout logic
and ADC
on-chip≥ 9 bit resolution
ADC
1-10µs selectableShaping peak
time
with Cdet < 400fF and Idet< 2 pA
detector connected
< 30 electrons r.m.s.
ENC
0.5 – 50 keV in GaAs120 – 12000
electronsInput charge
range
bump-bonding required between detector and ASIC
Square array of channels
(300µm pitch)Layout
1024:1 mux-ing required32 x 32Number of channels
RemarksValueParameter
A SET OF CHALLENGING REQUIREMENTS
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
REQUIREMENTS REVIEW
2D array layout Bump-Bonding needed
Pixel-Individual analog modules
low ENCLow-noise analog section
control of internal interference
on-chip ADCcomplex conversionmanagement logic
low powerconsumption
300 x 300 µm² cells
high sensitivity !
limited design resources
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
ARCHITECTURAL DESIGN
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
ARCHITECTURAL DESIGN
OVERALL BLOCK DIAGRAM
• Four quadrant• 256RPCs/quadrant• 16 ADCs/quadrant• Quadrant Trigger Logic• Global Trigger Logic• Acquisition I/F• Configuration I/F• Calibration Network• Probe Network
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
RPC DESIGN
READOUT PIXEL CELL
300µm
300µm
AVAILABLE AREA
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
RPC DESIGN
•Dedicated preamplifiers supply line
•P-MOS input stage & cascode
•Continuous reset with subthresholdtransistor
•On/Off features
•Calibration input
• 100µm x 100µm occupation
• 120 µW power dissipation
CHARGE PREAMPLIFIER FEATURES
SIMPLIFIED SCHEMATICS
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
PZC, SHAPER AND STRETCHER
• Reset circuit non linearitycompensation
• Current-mode shaper
• DC cancellation
• Adjustable peak time1,2,4,5,6,7,9,10 µs
• Equalization gain w.r.t.shaping time
•250 µW power dissipation
RPC DESIGN
SIMPLIFIED BLOCK DIAGRAM
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
RPC TRIGGER CIRCUITRY
RPC DESIGN
• Amplitude discriminator
• Fine THR tuning
• Peak discriminator
• Current-mode trigger to periphery
• Reset Logic
• 110µW power dissipation
SIMPLIFIED BLOCK DIAGRAM
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
RPC DESIGN
INPUT PAD
RPC LAYOUT
PREAMPLIFIERSHAPER
STRETCHER
OUTPUT BUFFER
TRIGGER & RESET LOGIC
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
ADC DESIGN
ADCs
• 16 RPC/ADC
• Wilkinson, 10 bit
• sine/differential clock
• on-chip adjustable ramp slope
• < 2 mW power dissipation
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
READOUT LOGIC
QTU/GTU
• Sparse Readout
• Multiple events management
• Global FIFO
• Fast parallel acquisition I/F
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
ANCILLARY ON-CHIP FACILITIES
CALIBRATION NETWORK
•three independent nets
•internal or external pulsing
PROBE NETWORK• interesting nodes inspection
ON BOARD DACS• Threshold and preamplifierreset adjustable bytelecommand
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
PROTOTYPES
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
PROTOTYPES
Four foundry runs:
• 16x16 study prototype #1 (MPW)
• 16x16 study prototype #2 (MPW)
• 32x32 prototype (STARX32 v.1) (dedicated run)
• 32x32 “final” (STARX32 v.2) (dedicated run)
Selected Technology: AMS C35 0.35µm CMOS
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
TESTING
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
TESTING
DEDICATED TEST SYSTEM
Device mounted on carrier hybrid
Shielded box with local biasing
ReadOut box ( FPGA )
Fast digital I/O card for data
Standard I/O card forconfiguration
PC-controlled
Control and Analysis SW
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
TESTING
CARRIER HYBRID
provides a light-tightand protectedenvironment for the device under test
allows easy mating/demating with the test equipment
Hosts some ancillarypassives for filtering/biaspurposes
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
TESTING
TYPICAL RPC SIGNALS
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
TESTING
ENC MEASUREMENTS (room-T, no-detector)
0 2 4 6 8 1010
15
20
25
Equ
ival
ent n
oise
cha
rge
[ ele
ctro
ns r
.m.s
. ]
Shaping Time [ µs ]
STAR-X32 v.1
RPC 48-4r.m.s. voltmeter
Minimum ENC:
~ 16 electrons rms at 6µs peak time
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
TESTING
END-TO-END LINEARITY
(include on-board ADC)
INL < 0.25 %
Range ~1000 to 10000 electrons
Stimulus via calibration network
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
TESTING
END-TO-END spectrum
(stimulus by on board calibration)
Line details
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
TESTING
QUICK-LOOK ANALYSIS
• all RPCs found working
• thin individual spectra lines
• gain/offset spread …
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
TESTING
PEAK WIDTH
noise estimation from peak w idth
0
5
10
15
20
25
0 200 400 600 800 1000
channel ID, 0=(0,0) to 1023=(31,31)
aver
age
peak
wid
th [e
lect
rons
rm
s]
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
TESTING
PEAK WIDTH
peak w idth distributionmean = 16 electrons rms, sigma = 1.2 electrons rms
0
50
100
150
200
250
300
350
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
peak w idth [electrons rms]
occu
renc
ies
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
TEST WITH DETECTOR
without detector with detector
• Custom-made 32x32 pixels p-n Silicon detector procured for test in realistic condition
• Bump-Bonded on some samples of STARX-32, one sample put on carrier hybrid
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
TEST WITH DETECTOR
• bump-bonding process functionally OK (just 1 out of 102 4 missing bond found)
• process possibly critical w.r.t. pixels performance:
FINDINGS
reverse currents much higher than expected,
up to > 50 nA/cm²,
is this due to bump-bonding process ?
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
TEST WITH DETECTOR
FINDINGS
• inter-pixel cross-talk
some signals from an activeRPC can AC-couple to nearby
RPCs via detector
Additional shielding (metal) above disturbing nodes
implemented in final prototype.
effectiveness to be tested soon
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
TEST WITH DETECTOR
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
RADIATION TEST
Radiation Test have been performed atESTEC Co-60 Facility
Total Dose = up to 59 kradIntermediate steps every 8 kradTotal Irradiation Time = 3 Days
TID TEST
In view of possible application on spaceborne instruments…
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
RADIATION TEST
A dedicated Test Board has been designed and manufactured.
The board has been used both for biasing during irradiation and for measurements.
The board is able to host up to 6 chips together and to stimulate and test up to 5 chip at the same time.
TEST BOARD
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
RADIATION TEST
TID TEST RESULTS
• most of RPC parameters do not show significant variations up to 60 krad
• one RPC bias show constant negative trend ~1% at 60 krad (tolerable)
• only marginal drifts on ADCs
• two samples needed re-adjustof the rest voltage above 40 krad
The test results suggest that the AMS 0.35 µm CMOS technology used in the LFDR prototype is radtolerant at least to 60 krad.
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
SUMMARY & CONCLUSIONS
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AMICSA 2010 workshop, 5-7 september 2010, ESA-ESTEC
SUMMARY & CONCLUSIONS
• We presented the latest development for the STARX32 proj ect
• The overall performances are very good, e.g. ENC and p ower dissipation, moreover radiation tolerance (TID) has been proven up to > 50 krad
• As expected for such a challenging design task we are im proving the design through successive prototypes and extended test campai gns
• Control of internal interference is of paramount importanc e and the major reason for the need of multiple prototypes
• Bump-Bonded detector requires carefull “top” shielding o f the front end cell
• The 4-th prototype (STARX32 v.2) has been manufactured in May 2010 and is presently under test, results so far are encouragin g, we are lookingforward to bump-bond a sample with a detector for comple te end-to-end test