1
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
2008
Electronic Devices Architectures for the NANO-CMOS Era. From Ultimate CMOS Scaling to Beyond CMOS devices
S.Deleonibus, CEA-LETI,
MINATEC, CEA-Grenoble 17 rue des Martyrs 38054 Grenoble Cedex 09 France.
Tel : 33 (0)4 38 78 59 73 Fax: 33 (0)4 38 78 51 83
email: [email protected]
2
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Outline
•Introduction : Facts on context and ITRS
•Scaling of Si MOSFET
Materials boosters: HiK, back to metal gate!,
MOSFET scaling: channel engineering ; FD SOI & boosted SOI
Multigate, Nanowires
Source and drains technology
•Alternative Architectures and Materials Boosters for continued
Nanoelectronics scaling
Opportunities for other Materials on Silicon?
Alternatives for Non Volatile Memories boosters facing a brick wall
3D styles integration on Silicon: monolithic,
Is there a «Beyond CMOS»?
•Conclusions
3
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Scaling: a success story…thanks to innovation
1,00E+00
1,00E+01
1,00E+02
1,00E+03
1,00E+04
1,00E+05
1,00E+06
1,00E+07
1,00E+08
1,00E+09
1,00E+10
1958 1963 1968 1973 1978 1983 1988 1993 1998 2003 2008 2013 2018
Date
Num
ber
oftr
ansi
stor
s pe
rch
ip
100µm
10µm
1µm
0,10µm
10 nm
CriticalDimension
4004
8080
808680286
i386
i486Pentium
Pentium II
Pentium III
Pentium IV
Itanium
1k4k
16k
64k
256k
1M4M
16M
64M128M
256M512M
1G2G
4G
microprocessors
dynamic memories(DRAM)
contacts « plugs »(3 lev met)
vias « plugs »,CMP(4 lev met)
FSG(6 lev met)
damascene(5 lev met)
Cu (7 lev met)
Cu+H(M)SQ (9 lev met)
polymers
+ALD (10 lev met)
ULK(11 lev met)
poly gate
polycide
1 billionOffice PC
Main Frame
C.T.V.
VCRDefense
Home PC
Portable Internet
Convergence
10 millions
STI, salicide
DigitalCamera
HiK +metal gate
1,00E+00
1,00E+01
1,00E+02
1,00E+03
1,00E+04
1,00E+05
1,00E+06
1,00E+07
1,00E+08
1,00E+09
1,00E+10
1958 1963 1968 1973 1978 1983 1988 1993 1998 2003 2008 2013 2018
Date
Num
ber
oftr
ansi
stor
s pe
rch
ip
100µm
10µm
1µm
0,10µm
10 nm
CriticalDimension
4004
8080
808680286
i386
i486Pentium
Pentium II
Pentium III
Pentium IV
Itanium
1k4k
16k
64k
256k
1M4M
16M
64M128M
256M512M
1G2G
4G
microprocessors
dynamic memories(DRAM)
contacts « plugs »(3 lev met)
vias « plugs »,CMP(4 lev met)
FSG(6 lev met)
damascene(5 lev met)
Cu (7 lev met)
Cu+H(M)SQ (9 lev met)
polymers
+ALD (10 lev met)
ULK(11 lev met)
poly gate
polycide
1 billionOffice PC
Main Frame
C.T.V.
VCRDefense
Home PC
Portable Internet
Convergence
10 millions
STI, salicide
DigitalCamera
HiK +metal gate
Moore’s law: 2Xdevices/year
Electronic Device Architectures for the Nano-CMOS EraFrom Ultimate CMOS Scaling to Beyond CMOS Devices
Editor: S.Deleonibus, Pan Stanford Publishing, Oct 2008
4
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Semiconductor Market applications successive waves
Source : Semico Research Corp. May 2004 IPI Report
5
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Three major product families(ITRS aware of CMOS scaling limits)
• High Performance (HP) t=CV/I
– Connection to power network
• Low Operating Power (LOP)
– Intermittent Nomadic Function
• Low Stand-by Power (LSTP) Pstat= VddxIoff
– Permanent Nomadic Function
Nomadic consumer and professional products:
largest market share continuously increasing
Pdyn=CVdd2 f
Ptot=Pstat+ Pdyn
6
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
ITRS forecast evolution
95
100
105
110
115
120
125
94 97 98 99 101 103 105 107
Date roadmap
Pro
duct
ion
star
t
2020
2015
2010
2005
1994 1997 1998 1999 2001 2003 2005 2007
2000
1995
2000
22nm(9nm)35nm(25nm)
50nm(35nm)70nm(50nm)
100nm(70nm)
130nm(100nm)
180nm(140nm)
250nm
45nm(18nm)
32nm(13nm)
65nm(25nm)
100nm(45nm)
130nm(65nm)
18nm(7nm)
2025
16nm(6nm)14nm(5nm) 11nm(4.5nm)
Roadmap of the roadmap: acceleration and… smooth slow down
Electronic Device Architectures for the Nano-CMOS EraFrom Ultimate CMOS Scaling to Beyond CMOS Devices
Editor: S.Deleonibus, Pan Stanford Publishing, Oct 2008
7
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Lg=3.8nm MOSFETS-D Suk et al, VLSI Tech Symposium, Kyoto 2009,p142(Samsung)
8
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
• Currently, 3 % of the world-wide energy is consumed b y the ICT infrastructure – which causes about 2 % of the world-wide CO2 emissions– comparable to the world-wide CO2 emissions by airplanes or ¼
of the world-wide CO2 emissions by cars• ICT: 10% of electrical energy in industrialized nation s
– 900 Bill.. kWh / year = Central and South Americas• The transmitted data volume increases approximately b y a
factor of 10 every 5 years
Source: TU Dresden
Ecological Footprint of ICTs reported by Intergovernmental Panel Climate Change(IPCC)
9
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Outline
•Introduction : Facts on context and ITRS
•Scaling of Si MOSFET
Materials boosters: HiK, back to metal gate!,
MOSFET scaling: channel engineering ; FD SOI & boosted SOI
Multigate, Nanowires
Source and drains technology
•Alternative Architectures and Materials Boosters for continued
Nanoelectronics scaling
Opportunities for other Materials on Silicon?
Alternatives for Non Volatile Memories boosters facing a brick wall
3D styles integration on Silicon: monolithic,
Is there a «Beyond CMOS»?
•Conclusions
10
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Scaling supply voltage challenges on MOSFET
Issues to address(trade of Performance & Power):
room temperature operation
threshold voltage control
parasitic effects
The most severe constraints are due to :doping concentration fluctuations, small volume,asymetry
FDSOI : low channel doping (reduced variability)
short channel effects low ∆VT vs. VT - low Vsupply -Tox thickness,doping concentration, Xj
leakage current in subthreshold regimeeven with S=60mV/dec(FDSOI) and VT = 0,20V (Vsupply=0,5V) we will get Ioff = 1nA/µm
tunnel currents SiO2 tunneling dielectric , F-N high doping level, direct tunneling
between S/D
P = Pstat + Pdyn Pstat= VddxIoff and Pdyn=CVdd2 f
11
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Statistical dopant fluctuations in a bulk device
• random distribution of channel dopants
– Poisson’s law: σdoping = √ N/volume• number of dopants in the active area decreases with scaling
– statistical fluctuations of threshold voltage: 150 mV VT decay for VT=200mV( Lg=25nm)
0.01
0.1
1
10
100
1000
104
0.01 0.1 1
σσ σσ N/N
Nom
bre
d'im
pure
tés
Lg (µm)
S.Deleonibus et al. ESSDERC 1999
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Classical MOSFET scalingChannel length K
Voltage UGate oxide K
Junction depth KElectric field U/K2
Channel doping U/KParasitic capacitance K(ACox,ACj)
Current (vel. sat.) U2/K(U)Delay(vel. sat.) K2/U(K)
Power (vel. sat.) U3/K(U2)Speed.Power product KU2 After Baccarani et al. IEDM 1984
13
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Linear Down scaling trends
H.Iwai, Microelectronic Engineering 86 (2009) 1520–1528
14
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Information technology based on switchingWhat is the smallest energy needed to qualify an information bit ?
(noise, power consumption, « make it green something »,…)
Switching devices characteristics :• Heisenberg’s uncertainty principle
• Statistical mechanics. Entropy maximization( Ω accessible states: 2 in binary system)
• Systems statistical failures
• Electrostatics Short channel effects: DIBL, Charge sharing,…• Variability (inherent process characteristics, process perfomances,…)
Electrostatics and variability are the 1st order limi tation to scaling
Design:• Device operation mode : 4 th independent electrode, Dynamic
threshold,…• Design/technology specific solutions: interconnect, local/global clock
(multicores), mixed logic/memory
τh≥E aJE 5
min 10−=
Ω≥ kTLnE aJE 310.3 −≥
≥
ττ mbfN
kTLnE.
aJE 25.0≥
2/1
min
).
(
=L
mbf
C
NkTLn
V ττ
Vmin≈10mV
(CL=0.4fF)
−
+−=∆ 1214
2/1
j
jox
ox
FTx
W
W
x
L
tV
εεϕ
22
,
∂∂+
∂∂∝ TSi
Si
tL
tSCEVt
T
V
L
V σσσ
15
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Increasing part of leakage current in power consumption
Source: Yasushi Yamagata and Kiyotaka Imai
NEC Electronics Corp., Advanced Device Development Div.,
Solid State Technology, November, 2004
Initially published in Nikkei Microdevices (SST partner)
16
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
High K dielectric integration:Replacing SiO2
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
2005 2007 2009 2011 2013 2015 2017 2019
Calendar Year
J g(A
/cm
2)
0
5
10
15
20
25
EO
T (A
)
J g, simulated for SiON, planar bulk
Jg, limit for SiON, planar bulk
EOT, planar bulk
EOT, UTB FD
EOT, DG
High-k needed beyond thiscrossover point
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
2005 2007 2009 2011 2013 2015 2017 2019
Calendar Year
J g(A
/cm
2)
0
5
10
15
20
25
EO
T (A
)
J g, simulated for SiON, planar bulk
Jg, limit for SiON, planar bulk
EOT, planar bulk
EOT, UTB FD
EOT, DG
High-k needed beyond thiscrossover point
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
2005 2007 2009 2011 2013 2015 2017 2019
Calendar Year
J g(A
/cm
2)
0
5
10
15
20
25
EO
T (A
)
J g, simulated for SiON, planar bulk
Jg, limit for SiON, planar bulk
EOT, planar bulk
EOT, UTB FD
EOT, DG
High-k needed beyond thiscrossover point
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
2005 2007 2009 2011 2013 2015 2017 2019
Calendar Year
J g(A
/cm
2)
0
5
10
15
20
25
EO
T (A
)
J g, simulated for SiON, planar bulk
Jg, limit for SiON, planar bulk
EOT, planar bulk
EOT, UTB FD
EOT, DG
High-k needed beyond thiscrossover point
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
2005 2007 2009 2011 2013 2015 2017 2019
Calendar Year
J g(A
/cm
2)
0
5
10
15
20
25
EO
T (A
)
J g, simulated for SiON, planar bulk
Jg, limit for SiON, planar bulk
EOT, planar bulk
EOT, UTB FD
EOT, DG
High -k needed beyond thiscrossover point
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
2005 2007 2009 2011 2013 2015 2017 2019
Calendar Year
J g(A
/cm
2)
0
5
10
15
20
25
EO
T (A
)
J g, simulated for SiON, planar bulk
Jg, limit for SiON, planar bulk
EOT, planar bulk
EOT, UTB FD
EOT, DG
High-k needed beyond thiscrossover point
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
2005 2007 2009 2011 2013 2015 2017 2019
Calendar Year
J g(A
/cm
2)
0
5
10
15
20
25
EO
T (A
)
J g, simulated for SiON, planar bulk
Jg, limit for SiON, planar bulk
EOT, planar bulk
EOT, UTB FD
EOT, DG
High-k needed beyond thiscrossover point
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
2005 2007 2009 2011 2013 2015 2017 2019
Calendar Year
J g(A
/cm
2)
0
5
10
15
20
25
EO
T (A
)
J g, simulated for SiON, planar bulk
Jg, limit for SiON, planar bulk
EOT, planar bulk
EOT, UTB FD
EOT, DG
High-k needed beyond thiscrossover point
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
2005 2007 2009 2011 2013 2015 2017 2019
Calendar Year
J g(A
/cm
2)
0
5
10
15
20
25
EO
T (A
)
J g, simulated for SiON, planar bulk
Jg, limit for SiON, planar bulk
EOT, planar bulk
EOT, UTB FD
EOT, DG
High-k needed beyond thiscrossover point
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
2005 2007 2009 2011 2013 2015 2017 2019
Calendar Year
J g(A
/cm
2)
0
5
10
15
20
25
EO
T (A
)
J g, simulated for SiON, planar bulk
Jg, limit for SiON, planar bulk
EOT, planar bulk
EOT, UTB FD
EOT, DG
High -k needed beyond thiscrossover point
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
2005 2007 2009 2011 2013 2015 2017 2019
Calendar Year
J g(A
/cm
2)
0
5
10
15
20
25
EO
T (A
)
J g, simulated for SiON, planar bulk
Jg, limit for SiON, planar bulk
EOT, planar bulk
EOT, UTB FD
EOT, DG
High-k needed beyond thiscrossover point
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
2005 2007 2009 2011 2013 2015 2017 2019
Calendar Year
J g(A
/cm
2)
0
5
10
15
20
25
EO
T (A
)
J g, simulated for SiON, planar bulk
Jg, limit for SiON, planar bulk
EOT, planar bulk
EOT, UTB FD
EOT, DG
High-k needed beyond thiscrossover point
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
2005 2007 2009 2011 2013 2015 2017 2019
Calendar Year
J g(A
/cm
2)
0
5
10
15
20
25
EO
T (A
)
J g, simulated for SiON, planar bulk
Jg, limit for SiON, planar bulk
EOT, planar bulk
EOT, UTB FD
EOT, DG
High-k needed beyond thiscrossover point
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
2005 2007 2009 2011 2013 2015 2017 2019
Calendar Year
J g(A
/cm
2)
0
5
10
15
20
25
EO
T (A
)
J g, simulated for SiON, planar bulk
Jg, limit for SiON, planar bulk
EOT, planar bulk
EOT, UTB FD
EOT, DG
High-k needed beyond thiscrossover point
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
2005 2007 2009 2011 2013 2015 2017 2019
Calendar Year
J g(A
/cm
2)
0
5
10
15
20
25
EO
T (A
)
J g, simulated for SiON, planar bulk
Jg, limit for SiON, planar bulk
EOT, planar bulk
EOT, UTB FD
EOT, DG
High -k needed beyond thiscrossover point
Tox=1.2nm Active area(10cm2 circuit): 1cm2
Pstat(0.5V)= 5W => 500W/m2(1/2 AM1)
Pstat(1V) = 50W => 5kW/m2
Pstat(1.5V) = 750W !! => 75kW/m2!! (Small Nuclear Power station installed power!!)
( )
−−= ToxEU2mqh
4πexpP 0
- E
U0
Tox
- E
U0
Tox
direct tunneling
17
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
HiK gate dielectrics
H. Iwai et al., IEDM Tech Digest 2002, pp. 625-627, Dec 2002, San Francisco(CA).
SixOxN y
or large
mobility gap
SiHigh K
materialGate
(poly,metal)
ox
ioxi tt ε
ε=
18
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
By courtesy: H.Iwai, TIT
19
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
High K dielectrics: transistor optimization
A.Poncet et al. SISPAD 2001
Short channel effect can be an issue with HiK:
Increased coupling between source & drain in thicker insulator
source
gateextension
drain
Gate insulator
20
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Difficulties in down scaling EOT
By courtesy H.Iwai,
SC Kyungpook National Univ.,
Korea, March 2009
21
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Metal Workfunctions Φm
Nb 3.99-4.30
Al 4.06-4.20
Ta 4.12-4.25
Mo 4.30-4.60
Zr 3.90-4.05
V 4.12-4.30
Ti 3.95-4.33
TaN 4.2-3.9
Ec
Ev
Ei
Co 4.41-5.00 Ru 4.60-4.71
W 4.10-5.20 Rh 4.75-4.98
Os 4.70-4.83 Au 4.52-4.77
Cr 4.50-4.60 Pd 4.80-5.22
ZrSi2
TiSi2
TaSi2
CrSi2
MoSi2
WSi2
NiSi2
CoSi2
RhSi
PdSi
WNx
TiNx 4.60-4.90
qχSi= 4.05eV
qϕmSi(Ei)=4.61eV
Vacuum level
Re 4.72-5.00
Ir 5.00-5.70
Pt 5.32-5.50
RuO2 4.90-5.20
Eg=1.12eV
SMSze Physics of Semiconductor Devices 1981
J.Hauser IEDM 1999 Short Course
TaSixNy
WSixNy
WCxNy
TiSixNy
ϕϕϕϕmn(Ei+0.2V)
ϕϕϕϕmp(Ei-0.2V)
ϕmn+(Ei+0.55V)
ϕmp+(Ei-0.55V)
Midgap
ox
BFFBT
C
QVV −Φ+= 2 ox
oxms
ox
oxmsFB
C
Q
C
QV −Φ=−Φ=
sMMS Φ−Φ=Φ
Silicon
tox
tdepletion
tinversionS D
G
Cg-ox
Cg-depl.
Cg-inv.
Tgateeletcrode
Cg =1
1
Cg-ox
1
Cg-depl
1
Cg-inv+ +
tox
tdepletion
tinversionS D
G
Cg-ox
Cg-depl.
Cg-inv.
Tgateeletcrode
tox
tdepletion
tinversionS D
G
Cg-ox
Cg-depl.
Cg-inv.
Tgateeletcrode
Tgateeletcrode
Cg =1
1
Cg-ox
1
Cg-ox
1
Cg-depl
1
Cg-depl
1
Cg-inv
1
Cg-inv+ +
reduce gate depletion capacitance
22
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Damascene Metal gate and HfO2 CMOSNitride spacersHfO2TiN
Tungsten
TiN 10nm
HfO2 2.20nm (3nm as dep)
Amorphous layer 0.90 nm
wwwww
Nitride spacersHfO2TiN
Tungsten
TiN 10nm
HfO2 2.20nm (3nm as dep)
Amorphous layer 0.90 nm
wwwww
Jg@
Ivg
-VtI
= 1V
10 -7
10 -5
10 -3
10 -1
10 1
10 3
1 1,5 2 2,5 3
HfO2-NMOSHfO2-PMOSSiO2-NMOSSiO2-PMOS
EOT(nm)
Jg@
Ivg
-VtI
= 1V
10 -7
10 -5
10 -3
10 -1
10 1
10 3
1 1,5 2 2,5 3
HfO2-NMOSHfO2-PMOSSiO2-NMOSSiO2-PMOS
EOT(nm)
10 -7
10 -5
10 -3
10 -1
10 1
10 3
1 1,5 2 2,5 3
HfO2-NMOSHfO2-PMOSSiO2-NMOSSiO2-PMOS
EOT(nm)
LETI, ST: B.Guillaumot et al. Presented IEDM 2002
Dec. 10-12, 2002, San Francisco(CA)
23
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
HiK & Metal gate Dual gate CMOS
Gate last(Damascene) process flow
Advantages of gate last flow• High Thermal budget available for Midsection– Better Activation of S/D Implants
• Low thermal budget for Metal Gate– Large range of Gate Materials available
• Significant enhancement of strain– Both NMOS and PMOS benefit
Intel: K.Mistry et al, IEDM 2007
K.Kuhn, IEDM 2008 Short Course
-introduction @45nm node
-demonstration @32nm node(S.Natarayan et al. IEDM 2008)
24
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Main Mobility Enhancement Techniques
Liners
CESL SMT eSiGe
nMOS
Tensile
nMOS
Comp.
pMOS
Tensile
SixGe1-x
SSOI
Tensile bi-axial
nMOS+pMOS
SSOI
pMOS
Compressive
SEGCrystal/Channel
Bulk SOI
SubstrateSubstrate --basedbased ProcessProcess --basedbased
Channel Orient. Substrate Orient.
Natural µ enhancement
<100>
(110)
eSiC
nMOS
Tensile
Gate MEOL
Replac. Gate Contact
nMOS
Tensile
pMOS nMOS
Tensile
pMOS
Compressive
Difficult to managewith FDSOI ultra-thin film
C.Fenouillet Béranger, 215th ECS Spring 2009, San Francisco
25
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Strain and bandgap engineeringCompressive strain Tensile strain Tensile strain
SixGe1-x
Si
In Si1-x-yGexCy No strain if x=10y
Band offset and splitting
EcEv
lh hh ∆(4) ∆(2)
Si
SixGe1-x∆Ev=0.74x
Ev Ec
∆ (2) ∆(4)hh lh
Si
Si1-yCy∆Ec=-6.5y
Ev Ec
∆ (2) ∆(4)hh lh
SixGe1-x
Si ∆Ec=0.6x
Si
Si1-yCy
Si
SixGe1-x
a= 5.43
5.43<a<5.65
Compressive strain Tensile strain Tensile strain
SixGe1-x
Si
SixGe1-x
Si
In Si1-x-yGexCy No strain if x=10y
Band offset and splitting
EcEv
lh hh ∆(4) ∆(2)
Si
SixGe1-x∆Ev=0.74x
Ev Ec
∆ (2) ∆(4)hh lh
Si
Si1-yCy∆Ec=-6.5y
Ev Ec
∆ (2) ∆(4)hh lh
SixGe1-x
Si ∆Ec=0.6x
Band offset and splitting
EcEv
lh hh ∆(4) ∆(2)
Si
SixGe1-x∆Ev=0.74x
EcEv
lh hh ∆(4) ∆(2)
Si
SixGe1-x
EcEv
lh hh ∆(4) ∆(2)
Si
SixGe1-x∆Ev=0.74x
Ev Ec
∆ (2) ∆(4)hh lh
Si
Si1-yCy∆Ec=-6.5y
Ev Ec
∆ (2) ∆(4)hh lh
Si
Si1-yCy
Ev Ec
∆ (2) ∆(4)hh lh
Si
Si1-yCy∆Ec=-6.5y
Ev Ec
∆ (2) ∆(4)hh lh
SixGe1-x
Si ∆Ec=0.6x
Ev Ec
∆ (2) ∆(4)hh lh
SixGe1-x
Si ∆Ec=0.6x
Si
Si1-yCy
Si
Si1-yCy
Si
SixGe1-x
SiSi
SixGe1-x
a= 5.43
5.43<a<5.65
Bi-axial
nMOSnMOSnMOSnMOSnMOSnMOSnMOSnMOS
30nmsSiSiGe
30nmsSiSiGe
pMOS
nFET
SiSiSiSi
cccc----CES
LCES
LCES
LCES
LnFET
SiSiSiSi
cccc----CES
LCES
LCES
LCES
L
Uni-axialStressors
(CESL, source & drain,
salicide,…)
pMOSnMOS
26
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Strained Si + strained Ge channels
• Improved hole mobility in compressively strained Ge and electron mobility in tensily strained Si
• Symmetrical drain current for any dual channel CMOS=> tremendous advantage on design layout(WN=WP)
0
5 10-6
1 10-5
1.5 10-5
2 10-5
2.5 10-5
3 10-5
-1.2 -0.8 -0.4 0 0.4 0.8 1.2
x6
VD=+/-1.2V
W=400µm
LG=10µm
TiN CVD gate
x1.65
Gate overdrive VG-V
TH (V)
PMOS NMOS
s-Si
Si
s-Ge
SiDra
in C
urre
nt I D
sat (
A/µ
m)
80
160
240
320
400
480
560
0 2 105 4 105 6 105 8 105 1 106
Mob
ility
(cm
2 .V-1
.s-1
)
Effective field (V/cm)
s-Ge
s-Si
Si refs.
Si refs.
(holes)
(holes)
(electrons)
(electrons)
universal
universal
HfO2/TiN
gate stackelectrons
holes
LETI,Alliance: O.Weber et al., IEDM, 2005
27
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
-40
-20
0
20
40
60
80
100
0,01 0,1 1 10
Low
fiel
d M
obili
ty g
ain
(%)
Effective Gate Length (µm)
symbols = exp.lines=input for Id model
Strained Devices
= CESL-sSi
= sSi= sSiGe
LETI, Alliance, SOITEC:
F.Andrieu et al. VLSI Tech. Symp, 2005
F.Andrieu et al., ESSDERC 2005 Best paper AwardESL-sSi : ⊕m* reduction ⊕ strain enhancement sSiGe : ⊕m* reduction extra charged defects sSi : quantization effects phonon scattering not dominant
ESL-sSi : ⊕m* reduction ⊕ strain enhancement sSiGe : ⊕m* reduction extra charged defects sSi : quantization effects phonon scattering not dominant
Short channel issues on strained architectures
Bi axial
+Uniaxial
Bi axial
28
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Silicon On Insulator
A
B
SOI wafer A
New A B
Smart-Cutsplitting at 500°C
Annealing 1100°CCMP touch polishing
Wafer A becomes B
A
B
A
BB
SOI wafer AA
New A B
Smart-Cutsplitting at 500°C
Annealing 1100°CCMP touch polishing
Wafer A becomes B
SiO2
Si
tSi
L
LETI : M. Bruel, Elec. Lett., vol. 31, n° 14, p. 1201, 1995
A B
A
A
A
B
Initialsilicon
Oxidation
Smart-Cutimplant
Cleaning andbonding
Buried oxide
H+ ions5.1016 cm-2
AA B
A
A
A
B
A
B
Initialsilicon
Oxidation
Smart-Cutimplant
Cleaning andbonding
Buried oxide
H+ ions5.1016 cm-2
Smart-Cut process LETI invention
29
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Electrostatic integrity
F. Bœuf, VLSI 2009
FinFET
FDSOI
Bulk
Table 1. Characteristic scale length expressions for various thin film device
architectures calculated from 2D Poisson equation (from ref. 18-21).
Device Surface conduction Volume conduction
architecture Scale length Scale length
FDSOI
single gate oxSi
ox
Si ttεε
=λ
εε+
εε=λ
2t
tt Si
Si
oxoxSi
ox
Si
Double gate oxSi
ox
Si t2
t
εε
=λ
εε
+εε
=λ4
tt
2
t Si
Si
oxox
Si
ox
Si
Cylindrical
channel
εε+
+
εε=λ
4t
tt2
1ln2t
4t Si
Si
ox
Si
oxSiSi
ox
Si
T.Poiroux, G. Le Carval
in Electronic Device Architectures for the Nano-CMOS Era From Ultimate CMOS Scaling to Beyond CMOS
Devices, Editor: S.Deleonibus, Pan Stanford
Publishing, Oct 2008
0
50
100
150
200
250
300
10 20 30 40Gate Length (nm)
DIB
L (m
V/V
)
FinFET
Bulk
FDSOI (TSOI~9nm, EOT~1.7nm)
International Benchmarking
EOT~1nm
O.Weber et al, IEDM 2008
No channel doping of thin films
FDSOI devices
30
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Improved Figures of Merit from SOIImproved Figures of Merit from SOILower Power consumptionLower Power consumption for SRAMfor SRAM
same standby leakage @ 1.2V for the memory cell compared to bulk @25°C, lower leakage @
125°C
gain in speed, for samedynamic Power, compared to bulk
but also 30% dynamicPower reduction at samespeed, compared to bulk !
1
10
100
1000
10000
0.7 0.9 1.1 1.3 1.5 1.7Vdd (V)
Isb
(pA
)
SOI
BULK )
25°C
125°CSOI
Bulk
Tacc(Ptot)
5.0E-09
6.0E-09
7.0E-09
8.0E-09
9.0E-09
1.0E-08
1.1E-08
1.2E-08
1.3E-08
1.4E-08
1.5E-08
0.0005 0.001 0.0015 0.002 0.0025 0.003 0.0035 0.004
Ptot (W)
Tacc
(s)
BULK
SOI
130nm SOI
Tacc = tacc of memory + access to the I/O!
130nm BULK1.2V
1.2V
1Mb SRAM – Measured access time vs Total Power
PDSOI
LETI: C.Raynaud et al., ECS invited talk , May 2005 see also J-LPelloie ISSCC 1999
31
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
BOX 145nm
Tsi 10nm
TiN 10nm
HfSiON 2.5nm
Poly 80nm
NiPt
Bitcell 0.179µm2
BOX 145nm
Tsi 10nm
TiN 10nm
HfSiON 2.5nm
Poly 80nm
NiPt
Bitcell 0.179µm2
32nm Low Power FDSOI
C.Fenouillet Beranger et al., IEDM 2007
V.Barral et al., IEDM2007
VDD=1V Ioff=6pA/µm
0.248µm2 SNM (1.2V)=140mV
0.179µm2 SNM (1.2V)=230mV
300mm 6T SRAM
-12
-11
-10
-9
-8
-7
-6
-5
100 200 300 400 500 600 700 800
tSI
=11.8nmtSI
=8.6nmtSI
=5.5nm2.5nm<t
SI<4nm
tSI
=11.1nmtSI
=9.1nmtSI
=6.8nm2.5nm<t
SI<4.5nm
Off
curr
ent
log(
IO
FF)
(A/µ
m)
On current ION
(µA/µm)
n-SOIn-sSOI
+40%
Leff
=18nm
Quasi-ballistic transport enhanced by
confinement & strain
2.5nm Strained SOI
Lg=18nm
32
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
0
50
100
150
200
250
300
10 20 30 40Gate Length (nm)
DIB
L (m
V/V
)
FinFET
Bulk
FDSOI (TSOI~9nm, EOT~1.7nm)
International Benchmarking
EOT~1nm
0
20
40
60
80
100
120
2 4 6 8 10 12
DIB
L (m
V/V
)
Si film thickness tSI
(nm)
Lg= 20nm
Lg=30nm
Lg=40nm
Lg=80nm
Lg=120nm
Symb. : ExperimentModel
0
20
40
60
80
100
120
2 4 6 8 10 12
DIB
L (m
V/V
)
Si film thickness tSI
(nm)
Lg= 20nm
Lg=30nm
Lg=40nm
Lg=80nm
Lg=120nm
Symb. : ExperimentModel
Thinning TSi is effective to reduce SCE and DIBL
Scalability boosters: T Si
High electrostatic integrity in planar FDSOI vs. Bulk and FinFETs
LETI, SOITEC: Weber et al. , IEDM2008
33
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Variability : LER, OTF, RD
A.Asenov, Tech Dig. VLSI Tech Symposium, p.86, Kyoto 2007
-random dopants fluctuations
major issue @ nodes<45nm
adds to LER and OTF VT and
circuit behaviour
-superiority of thin film on bulk
34
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
0.5
1
1.5
2
2.5
3
10 20 30 40 50 60
AV
t (m
V.u
m)
Gate length L (nm)
Bulk platform
planar FDSOI ST 65nm
ST 45nm
IBM 90nm
Intel 45nm
Intel 65nm
[7]
UTBSOILETI
square : Vd=50mV
circle: Vd=1V
IBM alliance 32nm[3]
[1]
[10]
[11]
[9]
Record-high V T matching perf.
0
20
40
60
80
100
120
-105 -8
7-6
9-5
1-3
3-1
5 0 15 33 51 69 87 105
σ∆Vt=34.5mV
σVt=24.5mV
AVt=0.95mV.µm
Cou
nt
Vt shift ∆Vt (mV)
0
20
40
60
80
100
120
-105 -8
7-6
9-5
1-3
3-1
5 0 15 33 51 69 87 105
σ∆Vt=34.5mV
σVt=24.5mV
AVt=0.95mV.µm
Cou
nt
Vt shift ∆Vt (mV)
Best trade-off between VT variations and gate length scaling compared to bulk MOSFETs and FinFETs
L=25nmW=60nm
(σVt=σ∆Vt/√2 to compare measurements on pairs and on arrays of transistors in the literature)
O.WeberO.WeberO.WeberO.Weber et al., IEDM 2008et al., IEDM 2008et al., IEDM 2008et al., IEDM 2008
35
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
0.5
1
1.5
2
2.5
3
10 20 30 40 50 60
AV
t (m
V.u
m)
Gate length L (nm)
FinFETs
Planar FDSOI
Wfin
=10nm
UTBSOILETI
square : Vd=50mV
circle : Vd=1V
Wfin
=20nm
Wfin
=15nmW
fin=20nm
[14]
[13]
[1]
[12]
[13]
[15]
[15]
[16]
Record-high V T matching perf.
0
20
40
60
80
100
120
-105 -8
7-6
9-5
1-3
3-1
5 0 15 33 51 69 87 105
σ∆Vt=34.5mV
σVt=24.5mV
AVt=0.95mV.µm
Cou
nt
Vt shift ∆Vt (mV)
0
20
40
60
80
100
120
-105 -8
7-6
9-5
1-3
3-1
5 0 15 33 51 69 87 105
σ∆Vt=34.5mV
σVt=24.5mV
AVt=0.95mV.µm
Cou
nt
Vt shift ∆Vt (mV)
Best trade-off between VT variations and gate length scaling compared to bulk MOSFETs and FinFETs
L=25nmW=60nm
(σVt=σ∆Vt/√2 to compare measurements on pairs and on arrays of transistors in the literature)
O.WeberO.WeberO.WeberO.Weber et al., IEDM 2008et al., IEDM 2008et al., IEDM 2008et al., IEDM 2008
36
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
0 2 4 6 8 10 12
stan
dard
dev
iatio
n σ V
t (V)
1/(W.L)0.5 (µm-1)
"surface" sources
α α α α 1/(WL)0.5
"short channel" sources
Vt(L)
DIBL Vd=1V
Vd=50mV
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
0 2 4 6 8 10 12
stan
dard
dev
iatio
n σ V
t (V)
1/(W.L)0.5 (µm-1)
"surface" sources
α α α α 1/(WL)0.5
"short channel" sources
Vt(L)
L=25nmW=0.42µm
L=0.2µmW=0.42µm
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
0 2 4 6 8 10 12
stan
dard
dev
iatio
n σ V
t (V)
1/(W.L)0.5 (µm-1)
"surface" sources
α α α α 1/(WL)0.5
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
0 2 4 6 8 10 12
stan
dard
dev
iatio
n σ V
t (V)
1/(W.L)0.5 (µm-1)
22
,
∂∂+
∂∂∝ TSi
Si
tL
tSCEVt
T
V
L
V σσσ“short channel” sources
Sources of V T Variability in UTBSOI
• High-k (Qox, ε)
LW
NNTq oxit
ox
oxQoxVt
.
.,
+∝
εσ
22
,.
.
+
∝
ox
Tox
ox
ToxVtTLWq
Tkox
σεσασ ε
Si
TSiTSiVt
TLWq
Tk σβσ.
., ∝
mmVtLW
φφ σγσ.
, ∝
• SOI thickness
• Metal gate
“surface” sources
Pelgrom plot
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
0 2 4 6 8 10 12
stan
dard
dev
iatio
n σ V
t (V)
1/(W.L)0.5 (µm-1)
"surface" sources
α α α α 1/(WL)0.5
"short channel" sources
DIBL(TSi
)T
Si=12nm
TSi
=8nm
Vt(L)
DIBL
O.WeberO.WeberO.WeberO.Weber et al., IEDM 2008et al., IEDM 2008et al., IEDM 2008et al., IEDM 2008
37
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
0
10
20
30
40
50
60
Vt s
tand
ard
devi
atio
n σ V
t (m
V) FDSOI HK+Metal
Inte
r-w
afer
Tot
al b
atch
Ran
dom
(lo
cal)
Inte
r-di
e
Tot
al w
afer
L=25nm W=0.06µm
0
10
20
30
40
50
60
Vt s
tand
ard
devi
atio
n σ V
t (m
V)
Ran
dom
(lo
cal)
Inte
r-di
e
Tot
al w
afer
FDSOI HK+Metal
Inte
r-w
afer
Tot
al b
atch
Ran
dom
(lo
cal)
Inte
r-di
e
Tot
al w
afer
Bulk 65nm Sony
L=25nm W=0.06µm L=60nm W=0.13µm
Total V T variability
* Local random fluctuations, which are highly reduced in FDSOI compared to bulk as shown previously, remain
the major contribution to the total VT variations
W.L=0.015µm 2 W.L=0.078µm 2
* VT variability of FDSOI 32nm similar to bulk 65nm
O.WeberO.WeberO.WeberO.Weber et al., IEDM 2008et al., IEDM 2008et al., IEDM 2008et al., IEDM 2008
38
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Scaling rules for FDSOI
TSOI Range (Å)
TBOX (nm)
TSOI (nm)
Node
± 5± 6± 8± 10
7.5102550
6778
8nm11nm16nm22nm
DIBL=100mV/V
Range = ±4 Å!
0000
+5+5+5+5
----5555
SOI uniformity 300mm wafers
1 9 17
25
33
41
49
57
65
73
81
89
97
105
113
121
129
137
Wafer #
-10
-5
0
5
10
SO
I Thi
ckne
ssD
evia
tion
to ta
rget
(Å
)
SOI Thickness
Max
Mean
Min
XUT+/- 5 Å - SOI thickness deviation
O.WeberO.WeberO.WeberO.Weber et al., ULSI et al., ULSI et al., ULSI et al., ULSI vsTFTvsTFTvsTFTvsTFT,2009,2009,2009,2009
39
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
-12
-11
-10
-9
-8
-7
-6
-5
200 400 600 800 1000 1200
I OF
F (
A/µ
m)
ION
(µA/µm)
+50%+90%
+100%
open: W=50nmclose: W=10µm
nFET <110>
25nm<L<55nm
Vdd
=1V
SOIt-CESL
SSOI SSOI +t-CESL
Strain induced enhancement in narrow W
ION/IOFF performance & boosters
SSOI and tensile CESL enhance FDSOI nFETs performance
Nchannel : 1000µA/µm @ 1nA/µm and Vdd=1V
Compressive CESL enhance FDSOI pFETs performance
O.WeberO.WeberO.WeberO.Weber et al., ULSI et al., ULSI et al., ULSI et al., ULSI vsTFTvsTFTvsTFTvsTFT,2009,2009,2009,2009
40
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Towards High Performance CMOS…Co-integrated DDDDual Strained CCCChannel OOOOn IIIInsulator
down to 12nm gate length with a high-k/metal gate stackLETI, Alliance, SOITEC:
F. Andrieu et al., IEEE SOI conf., 2005
20nm
pFETs
LTiN=12nm
BOX
Si0.6Ge0.4
sSDOI
20nm
sSDOI
nFETs
LTiN=14 nmNiSi
Poly Si
TiN
HfO2
0
200
400
600
800
1000
-1.2 -0.6 0 0.6 1.2
Dra
in C
urre
nt (
µA
/µm
)
Drain Voltage (V)
WG=10µm
LG=15nm
DCOI
|VG-V
Tlin|=1V; 0.8V; ...
nMOS
pMOS
0
50
100
150
200
250
300
350
0 5 1012 1 1013
Si/HfO2
sSi/HfO2
DCOI/HfO2
Si/SiO2
sSi/SiO2
Hol
e M
obili
ty (
cm2 / V
s)
Inversion Charge Density (cm-2)
+100%
SOI or sSDOI
DCOI
LG=10µm
0
400
800
0 5 1012 1 1013
Si/HfO2
sSi/HfO2
Si/SiO2
sSi/SiO2
Ele
ctro
n M
obili
ty (
cm2 / V
s)
Inversion Charge Density (cm-2)
+85%+100%
SOI
sSDOI
LG=10µm
VT matching SOI -> LP
DCOI -> HP
41
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
sSOI(ΩΩΩΩΩΩΩΩFETFET like devices): length and width effect
Exp. gm,max
Theor. mobility
0
20
40
60
80
100
120
140
0.01 0.1 1 10
Enh
ance
men
t (%
)
Width (µm)
0
500
1000
1500
0 100 200 300 400 500 600x (nm)
xx (MPa)
Buried oxide
sSOI
(a)
(b)
~0.1µm
x (nm)
σ xx
(MP
a)
xzy
0
500
1000
1500
0 100 200 300 400 500 600x (nm)
xx (MPa)
Buried oxide
sSOI
(a)
(b)
~0.1µm
x (nm)
σ xx
(MP
a)
xzy
Mechanical Simulations demonstrating
the gain decrease (MESA isolation).
BOX
σxx
σyy
*Width: change
from bi-axial
into uni-axial strain
* CESL and bi axial
strains are cumulative
<100> most sensitive
10-7
10-6
10 100 1000
SOIsSOI
g m,m
ax (S
)Width (nm)
LG=10µm
VD=0.05V
+65%
+40%
LETI, Alliance, SOITEC:
F. Andrieu et al., VLSI Tech Symp, 2006
F.Andrieu et al., VLSI Tech Symp 2007
0
10
20
30
40
0 20 40 60 80 100
FD sSOI (this work)
PD sSOI or SGOIFD sSOI
sSi/SiGe
Gate Length (nm)
sSi/SiGe
I ON E
nhan
cem
ent (
%)
PD sSOI
This work
FD sSOI
[8]
[7]
[7]
[5]
FD sSOI
[9]
PD SGOI[10]
PD SGOI[11]
sSi/SiGe[12]
sSi/SiGe
FD sSOI[4]
Large devices
42
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
SOI: Threshold voltage thickness dependance
N+ poly gate
VT(V)
Tsi(nm)
222
2
×=∞
sie
nT
n
mE
hπQuantum confinement:
111
22
ox
siAffbT
C
TqNVV ++= φFully depleted SOI:
Bulk or PD SOI like
FDSOI
Quantum
confinement
LETI: J.Lolivier et al, ECS Spring 2002
43
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Thin Films Devices Relaxing optimization rule by architecture
TSi= ¼ Lg
TSi= 1 to 2 Lg
Planar Double-gate
Planar or Finfet
Trigate/nanowire
tsource
Gate
tsource
Gate
Gate source
t
Gate
SourceL
w
ThinSOI
Bulk or thick SOI
TSi= ½ Lg
w
TSi=2.5nm
Strain global & local
Lg=10nm
Barral et al.
IEDM2007
Andrieu et al
VLSI2006
Bernard et al.
VLSI 2008
Dupré et al.
IEDM 2008
Ernst et al.
IEDM 2008
Jahan et al.
VLSI2005
Vinet et al.
EDL 2005
4.8 nm
3.4 nm
4.8 nm
3.4 nm
44
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Planar Double gate by bonding
Lg~13nm
Lg~8nm
Lg~13nm
Lg~8nm
M.Vinet et al. IEEE EDL, May 2005
IonN(10nm) =1130µA/µm IoffN(10nm)=7µA/µm Lg=10nm; Lch=5nm
IonN(20nm) = 1250 µA/µm IoffN(20nm)= 1.3 µA/µm
Lg=20nm
LETI : M.Vinet et al. SSDM, Sept 2004 LETI: J.Widiez et al., SOI Conf 2004
Best papersAwards
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
-800 -400 0 400 800 1200Ion (µA/µm)
|Ioff|
(µA
/µm
)
DG
FDFD DG
LSTP LSTP
LOP
HP HP
LOP
PMOS NMOS
VbgVbg
Vbg-Vfg
Vbg-Vfg
1.101
11.10-1
1.10-2
1.10-3
1.10-4
1.10-5
1.10-61.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
-800 -400 0 400 800 1200Ion (µA/µm)
|Ioff|
(µA
/µm
)
DG
FDFD DG
LSTP LSTP
LOP
HP HP
LOP
PMOS NMOS
VbgVbg
Vbg-Vfg
Vbg-Vfg
1.101
11.10-1
1.10-2
1.10-3
1.10-4
1.10-5
1.10-6
0
0,02
0,04
0,06
0,08
0,1
0,12
0,14
0,16
-1,2-1-0,8-0,6-0,4-0,20
Dra
in c
urre
nt(µ
A/µ
m)
Top gate voltage (V)
Vbg=0.8 to -0.8V
DG mode
0
0,02
0,04
0,06
0,08
0,1
0,12
0,14
0,16
-1,2-1-0,8-0,6-0,4-0,20
Dra
in c
urre
nt(µ
A/µ
m)
Top gate voltage (V)
Vbg=0.8 to -0.8V
DG mode
From Low Standby Power to High Performance:
New design opportunities:
SRAM stability and Ileak reduction,
reduction of number transistors (4T SRAM, analog,…)
Best state of the art Ion/Iofffor Lg=10nm!!
45
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Stacked Multichannels and MultiNanowires« Top-Down » approach
LETI: Dupré et al. IEDM 2008, San Francisco(CA)Ernst et al., Invited talk IEDM 2008, San Francisco( CA) Bernard et al, VLSI Symposium 2008 Honolulu A.Hubert et al, ECS Spring Meeting, 2008,
10-12
10-10
10-8
10-6
10-4
10-2
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
Dra
in C
urre
nt I
D (
A/µ
m)
Gate Voltage VG (V)
VD=1.2VV
D=1.2V
NWFET
P N
VD=50mV
ION
=6.5mA/µm
IOFF
=27nA/µm
SS=68mV/decDIBL=15mV/VV
T=0.5V
C.E.T.=1.8nm
VD=50mV
ION
=3.3mA/µm
IOFF
=0.5nA/µm
SS=65mV/decDIBL=7mV/VV
T=-0.62V
LETI top down approach for Low Power and High performance
46
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Multichannel/Multigate nMOSFETsLSTP like with Hi Performance Ion
LETI/STSamsung
LETI/ST: E.Bernard et al, VLSI 2008
Ion=6.5mA/µm Ioff=27nA/µm
LETI/ST: Dupré et al.
IEDM 2008
ΦΦΦΦFET
47
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Roadmap requirementsfor source-drain extensions
Trade off between short channel effectsand MOSFET access resistance
Increaseactivation Junction depth vs sheet resistance for p-type substrat e
with ITRS Roadmap (2001/2003)
0
200
400
600
800
1000
1200
1400
0 20 40 60 80 100 120Junction depth Xj @10 18 (nm)
She
etre
sist
ance
(ΩΩ ΩΩ
/sq)
Theoretical box profilelimit
LTP C.Laviron et al
USJW2002
100 nm
45 nm
70 nm
130 nm
RTP results fromliterature(Fiory MRS 2001; Murrel JVST 2000; Lenoble Essderc 2000)
and LETI internalresults
32 nm
Reduce TED
PLAD
Mizuno et al IEDM 1997
Sasaki et al. VLSI 2004
SOIRTP
PLAD
48
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Schottky vs ohmic contact on degenerate extension
-5 0 5 10 15 20 250
50
100
150
200
250
300
350
Tot
ale
acce
ss r
esis
tanc
e (Ω
)
Source and drain silicon thickness (nm)
4 Ω.µm2
2 Ω.µm2
1 Ω.µm2
0.4 Ω.µm2
0.04 Ω.µm2
12nmTSi
salicide
source
12nm
salicide
12nmSilicide penetration
salicide
(Ω.µ
m)
Metallic S/D
Standardgeometry
-5 0 5 10 15 20 250
50
100
150
200
250
300
350
Tot
ale
acce
ss r
esis
tanc
e (Ω
)
Source and drain silicon thickness (nm)
4 Ω.µm2
2 Ω.µm2
1 Ω.µm2
0.4 Ω.µm2
0.04 Ω.µm2
12nmTSi
salicide
source
12nm
salicide
12nmSilicide penetration
salicide
(Ω.µ
m)
-5 0 5 10 15 20 250
50
100
150
200
250
300
350
Tot
ale
acce
ss r
esis
tanc
e (Ω
)
Source and drain silicon thickness (nm)
4 Ω.µm2
2 Ω.µm2
1 Ω.µm2
0.4 Ω.µm2
0.04 Ω.µm2
12nmTSi
salicide
source12nmTSi
salicide
source
12nm
salicide
12nm
salicide
12nmSilicide penetration
salicide
12nmSilicide penetration
salicide
(Ω.µ
m)
Metallic S/D
Standardgeometry
1016 at.cm-3 1017 at.cm-3 1018 at.cm-3 1019 at.cm-3 1020 at.cm-3 1021 at.cm-3
0.05eV 0.7 0.5 0.3 0.2 0.06 0.02
0.1eV 4 3 2 0.5 0.07 0.02
0.2eV 195 115 41 5 0.4 0.03
0.3eV 7255 4059 1236 108 3 0.07
Contact resistance (ohms) for various Schottky junct ion parameters. (contact surface 0.3x0.3µm 2)
ErSi2, YSi2 n-like
PtGe, PtSiGe p-like
Schottky like
contacts
* Higher activation in engineered extensions:
-high activation in Si LTP, PLAD, FTP
-new extension materials SiGe, Ge,…
* Ohmic contacts: midgap metal on
n+/p+ext., highly segregated ext. dopants *
Schottky like contacts interest on thin SOI *
Injection velocity at source(pot. Profile,
material, strain,…)
IST NANOCMOS
J.Lolivier ECS Spring 2003
X10:
49
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Metallic Sources and drains
LETI: Vinet et al, EDLetters, pp.748-750, July 2009
PtSi/p+ specific resistivity: 0.50µΩ.cm Extensions access resistance: 200µΩ.cm pMOS Lg=30nm:
Isat=787µA/µm@Ioff=57nA/µm
DIBL<100mV/V
- Ohmic contact on thin films source and drain
(dopants segregation)
=> suppression of ambipolar conduction
- accumulation mode MOSFET
- Variability reduction
TSi=10nm
Self aligned DGMOS:
tunable VT
HfO2
50
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Ultimate transport properties in SiBallistic transport (Planar DGMOS)
injTGSOXDS νr1
r1)V(VWCI
+−−=Quasi-ballistic model
* Decrease of the rSAT coefficient at low temperatures
* Increase of LG Increase of rSAT
Tunnelingcomponent
Thermioniccomponent
x
y
Energysubbandi
Valleyj
BallisticBallisticcurrentcurrentTunnelingcomponent
Thermioniccomponent
x
y
Energysubbandi
Valleyj
BallisticBallisticcurrentcurrent
Thermioniccurrent
Tunnelingcurrent
Ballisticand
DiffusiveTransport
Tunnelingcomponent
Thermioniccomponent
x
y
Energysubbandi
Valleyj
BallisticBallisticcurrentcurrentTunnelingcomponent
Thermioniccomponent
x
y
Energysubbandi
Valleyj
BallisticBallisticcurrentcurrent
Thermioniccurrent
Tunnelingcurrent
Ballisticand
DiffusiveTransport
0.15
0.2
0.25
0.3
0.35
40 80 120 160 200 240 280
LG=10nm
LG=20nm
LG=70nm
T (K)
Initial injection velocity at source Added to strain effectsReflexion on ionized dopants(channel or drain) Interface roughness will reduce ballisticity
Source architectures: electrostatics and material electronic properties
LETI: G.Bertrand et al, SNW2000 Honolulu(HI), ULIS2003Munchen(FRG), SSE 2004
V.Barral et al, ULIS 2006 Grenoble(France), SSE Special issue April 2007
51
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Outline
•Introduction : Facts on context and ITRS
•Scaling of Si MOSFET
Materials boosters: HiK, back to metal gate!,
MOSFET scaling: channel engineering ; FD SOI & boosted SOI
Multigate, Nanowires
Source and drains technology
•Alternative Materials and Architectures Boosters for continued
Nanoelectronics scaling
Opportunities for other Materials on Silicon?
Alternatives for Non Volatile Memories boosters facing a brick wall
3D styles integration on Silicon: monolithic,
Is there a «Beyond CMOS»?
•Conclusions
52
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
4
2,7
5,0
0.72
0,60
0,86
vsat(107cm/s)
1x1012cm -2
(1x1015)
10-27
2x1016
9x105
2x1013
2x1010
ni(cm-3)(m*em*h /m
2)T3/2
exp(-Eg/2kT)
0.1616.8_75078000InSb
Semi-metal
5.71000104-105104-105Graphene(CNT) sp2
5.7
12.513.0
16
11.9
Rel. K
5.47
1.420.70
0.66
1.12
Eg(eV)
>150018001800C-Diamondsp3
46400
400
8900
30 000GaAs InGaAs
59.919003900Ge
1415001400Si
sth (W/m/K)µp (cm2V-1s-1)
µn (cm2V-1s-1)
Material
Opportunities for other materials on SiliconS.Deleonibus et al., Int.Journ. High Speed Electronics, March 2006
Highest µn but Worst µn/µp!!
Well established high quality material(>40yrs experience) Oxidizable !
Silicon compatible Available in all fabsGaAs lattice constant matching
Opto/Power RF applications Ge compatible HP N channel
Highest σσσσth
Most compact logic
High short channel
effect immunity
Passive layer combine
w BOx
(thermal shunt)
Poor short channel
effect immunity
Electronic Device Architectures for the Nano-CMOS Era
From Ultimate CMOS Scaling to Beyond CMOS Devices
Editor: S.Deleonibus, Pan Stanford Publishing, Oct.2008
53
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Low band gap: pGeOI MOSFET
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-1.5 -1 -0.5 0 0.5 1 1.5
V GS (V)
I d(A
/µm
)
L G =70nm
V d=-0.1V
V d =-1V
0.1
1
10
0 100 200 300 400 500
I OF
F (
µA/µ
m)
@(V
g-V
t)=-V
d/3
ION
(µA/µm) @(Vg-V
t)=2V
d/3
Lg=60nm
80nm110nm
Ge bulk[6]
Ge epi [9]
Lg=125nmThis work
GeOI
Lg=120nm
Lg=70nm
Vd=-1.2VVd=-1.1VVd=-1.0V
optimized 70nm device (TCAD simul.)
0.1
1
10
0 100 200 300 400 500
I OF
F (
µA/µ
m)
@(V
g-V
t)=-V
d/3
ION
(µA/µm) @(Vg-V
t)=2V
d/3
Lg=60nm
80nm110nm
Ge bulk[6]
Ge epi [9]
Lg=125nmThis work
GeOI
Lg=120nm
Lg=70nm
Vd=-1.2VVd=-1.1VVd=-1.0V
optimized 70nm device (TCAD simul.)
[6] : T. Yamamoto et al., IEEE IEDM 2007[9] : G. Nicholas et al., IEEE TED 2007
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.1 1
Vt (V
) @
Vd=-
50m
V
Lg (µm)
w/o pockets
w. pockets
TCAD
Measured
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.1 1
Vt (V
) @
Vd=-
50m
V
Lg (µm)
w/o pockets
w. pockets
TCAD
Measured
K. Romanjek et al. ESSDERC 2008, SSE 2009
Φ =200mm GeOI: bulk Ge & condensed SiGe
• Controlled SCE (Vth=-0.1V) down to LG=70nm (TiN metal gate/HfO2)
• Improved transport properties– Large ION
– Low field mobility+50% gain (vs. SOI)
• Increased BTBT vs Si
54
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
III-V MOSFET: Low Power and High Performance
low VDD(0.5-0.7V) and improved
figures of merit are obtained
compared to Si
R.Chau, ESSDERC 2008, DRC 2006
55
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
SP2 Carbon: 0-Dimension to 3-Dimension
Fullerenes (C60) Carbon Nanotubes GraphiteGraphene
0D 1D 2D 3D
Band structure of graphene (Wallace 1947)
kx
ky
Energy
kx '
ky '
E
⊥′≈
kvE
F
rh
Zero effective mass particles moving with a constant speed vF
hole
electron
Band structure of graphene (Wallace 1947)
kx
ky
Energy
kx
ky
Energy
kx '
ky '
E
kx '
ky '
E
⊥′≈
kvE
F
rh
Zero effective mass particles moving with a constant speed vF
hole
electron
hole
electron
ky
kx
E
k1D
Semiconducting nanotube
Eg ~ 0.8 ev / d (nm)
ky
kx
ky
kx
E
k1D
Semiconducting nanotubeE
k1D
Semiconducting nanotube
Eg ~ 0.8 ev / d (nm)
Atomic orbital sp2 σ
π
Atomic orbital sp2 σ
π
σ
π
(since 1991)
Graphene(since 2004)
56
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
High mobility materials have been under intensive r esearch as an alternative to Silicon for higher performance mobility: Si (1,400 cm2/Vsec), InSb (77,000 cm2/Vsec)
Graphene mobility: > 100,000 cm2/Vsec @ room temperature
Enhanced Room Temperature Mobility of Graphene
104
105
106
-0.2 0.0 0.2
unsuspended best
before annealing
after annealing
Density ( 1012 cm-2)
Mobility (cm
2/V sec)
104
105
106
-0.2 0.0 0.2
unsuspended best
before annealing
after annealing
Density ( 1012 cm-2)
Mobility (cm
2/V sec)
100
90
80
70
60250200150100500
holeselectrons
T (K)
R(Ω) |n|=2X1011 cm-2
Resistance at High Density
0.24 Ω/K
0.13 Ω/K
Strong density dependence!100
90
80
70
60250200150100500
holeselectrons
T (K)
R(Ω) |n|=2X1011 cm-2
Resistance at High Density100
90
80
70
60250200150100500
holeselectrons
T (K)
R(Ω) |n|=2X1011 cm-2
Resistance at High Density
0.24 Ω/K
0.13 Ω/K
Strong density dependence!
GaAs: 0.7x107 cm/s
vFermi = 1x108 cm/sFor comparison:
Silicon: 1x107 cm/s
Operation current density > 1 mA/µm
GaAs: 0.7x107 cm/s
vFermi = 1x108 cm/sFor comparison:
Silicon: 1x107 cm/s
GaAs: 0.7x107 cm/s
vFermi = 1x108 cm/sFor comparison:
Silicon: 1x107 cm/s
Operation current density > 1 mA/µm
F
FsatE
vvΩ= h
0.8
0.6
0.4
0.2
0.00.50.40.30.20.10.0
EF (eV)
v sat
(108
cm/s
)
Saturation velocity
F
FsatE
vvΩ= h
0.8
0.6
0.4
0.2
0.00.50.40.30.20.10.0
EF (eV)
v sat
(108
cm/s
)
Saturation velocity
F
FsatE
vvΩ= h
0.8
0.6
0.4
0.2
0.00.50.40.30.20.10.0
EF (eV)
v sat
(108
cm/s
)
Saturation velocity
Meric, Han, Young, Kim, and Shepard (2008)
MOSFET HiK
57
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
S
D
GGraphene
M.C. Lemme et al., IEEE Electron Dev. Lett., April 2007
Graphene channel: monolayer/few layers channel
Field effect devicesTransport properties Carbon Electronics
-1.0 -0.5 0.0 0.5 1.0
1.4
1.6
1.8
2.0
2.2
I d (
µµ µµA)
top-gate electric field Etg
(MV/cm)
Ebg
(MV/cm)
-3.33 -1.67 -0.67
High and equal
e- and h+ mobility
High interest for
design!
MOSFET : µh=710cm2/Vs
µe=530cm2/Vs
MOSFET : µh: 1600 to 2200 cm2/V.s
µe : 800 to 1400 cm2/V.sJ.Kedzierski et al. , IEEE EDLetters, pp 745-747, vol 30, n°7, July 2009
58
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Carbon based materials• Graphene Nanoribbons
– Energy gap witdth dependanceHan, Oezyilmaz, Zhang and Kim PRL (2007)
– Crystallographic direction and roughness dependanceSon, et al, PRL. 97, 216803 (2006)
• Carbon Nanotubes – Fabrication E field direct growth– No dangling bonds– GAA MOSFET, Schottky S&D– BTBT @RT (SS<40mV/dec)
Band gap: 0.5 – 1 eV
On-off ratio: ~ 106
Mobility: ~ 100,000 cm2/Vsec @RT
Ballistic @RT ~ 300-500 nm
Fermi velocity: 106 m/sec
Max current density > 109 A/cm2
Ph. Avouris et al, Nature Nanotechnology 2,605 (2007)
Device Concepts
Conventional:(extended) CMOS, SET
Non-Conventional:Quantum Interference, Spintronics, valleytronics
Device Concepts
Conventional:(extended) CMOS, SET
Non-Conventional:Quantum Interference, Spintronics, valleytronics
Y.Zhang et al, Appl Phys Lett,79,3155 (2001)
59
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Band To Band Tunneling 3/ 2*4 2exp
3 | | ( )
gWKB
tunneling
g
ET
e E
m ≈ − ∆Φ +
Λh
Low « subthreshold » slope characteristics:
Tunnel Field Effect Transistor
ION independent of LG
Smaller S(< 60mV/dec )=>depends on VG
Smaller IOFF
But smaller ION also
Impact Ionization MOS
Eg lower limit
Role of Effective mass
High Electric field needed => Reliability issues
Rate:Impact Ionization
If mh* = me
* :Opportunities for low bandgap materials co integrated with CMOS on Si: strain, hybrid orientations, other materials: Ge, InGaAs, Carbon based(CNT, Graphene),…
60
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
SOI TFETs co-integrated with CMOSFETs
L=100nm; T=300K
•P mode: VDS<0 & VGS<0 •N mode: VSD>0 & VGD>0
Experimental demonstrationof Tunnel FET operations:
F.Mayer et al., IEDM 2008,
C.LeRoyer et al., ULIS 2009
Vth
VG
Log ID
IOFF
ideal switch
TFETMOSFET
Vth
VG
Log ID
IOFF
ideal switch
TFETMOSFET
SOI TFET w. LDDn
BOx
S D
GP mode N mode
61
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
10-14
10-12
10-10
10-8
10-6
-3 -2 -1 0 1 2 3VGS - VBtBt (V)
tSiGe= tSi= 20nm
GeOI xGe=15%
SOI
30%
LG= 400nm
VGD - VBtBt (V)
30%
SOI
xGe=15%
Functionnal SiGeOITFET with SOI process
Increase of Tunnel current with %Ge => ION increase
F.Mayer et al., IEDM 2008
From SOI to GeOI TFETs
62
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
nTunnel FET – Electrodes engineering : pGe Source
S.H.Kim, VLSI Tech. Symp., p178,2009
LG 0.25-5µmW 0.25-0.35µmTox 3nmTbox 200nmTSi 70nmTGe 21nmTsp 8nm
compatible with Low Power CMOS (<500MHz)
Ion/Ioff > 106@Lg=5µm; Ion/Ioff > 104@Lg=0.25µm
63
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Impact Ionisation MOS
-2.5
-2
-1.5
-1
-0.5
0
16.5 17 17.5 18
Vs (V)
Vg
T (V
)
0
20
40
60
80
100
S (
mV
/dec
)
VgT (V) S
0.0E+00
5.0E+05
1.0E+06
1.5E+06
0 100 200 300 400 500 600 700 800 900L IN (nm)
E (
V/c
m)
0
5
10
15
20
25
30
35
40
VB
R (
V)
E avalanche SiE avalanche GeVBR SiVBR Ge
DRAIN: N+ « Intrinsic area » P-
Gate
Vd=0V Vs < 0
SOURCE: P+
BOx
DRAIN: N+ « Intrinsic area » P-
Gate
Vd=0V Vs < 0
SOURCE: P+
BOx
2mV/dec
LETI: F.Mayer et al, SSE April 2007, F.Mayer et al, ESSDERC 2006
64
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Memory Technology Roadmap
Increasing importance of Embedded Memory in CPU (especially Flash NVMs) – 90% in 2009; 95% in 2014
65
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Comparison of NVM Characteristics
66
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Few electron phenomena will
appear in future NV memory
generations
10 10010
102
103
Num
ber
of e
lect
rons
perb
it, N
Flash TechnologyNode[nm]
∆∆∆∆VTh-max=3VNOR Flash
NAND Flash
Si-NanocrystalsMemories(NAND )
35nm
200
10 10010
102
103
Num
ber
of e
lect
rons
perb
it, N
Flash TechnologyNode[nm]
∆∆∆∆VTh-max=3VNOR Flash
NAND Flash
Si-NanocrystalsMemories(NAND )Si-Nanocrystals
Memories(NAND )
35nm
200
35nm
200
Number of carriers per operation
will reduce in future devices
67
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Nanocrystals for Non Volatile (Flash) Memories
Defect in conventional Flash memories
(Stress Induced Leakage Current):
=> retention
insulator
Tunn.Ox
Control gate
Floating gate
Control gate
Nanocrystals
Si substrate
Control gate
ADAMANT
N= 1012cm -2, ΦΦΦΦ= 5nm LPCVD Si
LETI: DeSalvo et al., IEDM 2003 Molas et al., IEDM2004Perniola et al., IEDM2005 Jacob et al., ESSDERC 2007
32Mbit NOR
68
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
SiNanocrystals and HiK for NAND Flash(a)
Poly-Si
SiN
Si
HfO2
(d)
(c)
60nm
60nm
HTO
SiN
Si
3nm
Poly-Si
Si
Si-ncs
HfAlO
HTO
SiO2
HTO
(b)
LETI: G.Molas et al. IEDM2007
SiO2
HTO
HTO
HfAlO Poly-Si(VG=16V)
J tun
FG
J IPD: experimentalmeasurements
J1
J2
VG
VFG
CIPD
Ctun
1 10 102 103 104 105
3
4
5
6
Cycle number
Vth
[V] Data
Experiment
S1 – IPD: O/HfO2/O
* HiK improves CG/SiNc coupling
ratio (NAND Flash)
*FinFlash improves
short channel effectLETI:
J.Razafindramora et al. ESSDERC 2007
L. Perniola et al., IEDM 2007
69
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Chalcogenide glasses: GeSbTe, AgInSbTe, ….
Y.N. Hwang et al., VLSI Tech Symp, p. ,2003
The Operation Principle of PCRAM
-Phase diagram well known (optical recording, …)
-Scalability (the samller the better)
-Endurance: 1012 P/E cycles proven (Intel IEDM 2001)
-Write disturb (Fantini, IMW 2009)
70
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Resistive Switching Memories
M2 AlCu
SiO
Si
WTiNPt
OxidePt
Al
TiN
WTiN
Pt or CuOxyde
Pt
AlCuTi/TiNM1
SiNM2 AlCu
SiO
Si
WTiNPt
OxidePt
Al
TiN
WTiN
Pt or CuOxyde
Pt
AlCuTi/TiNM1
SiN
Resistive RAM - 2 approaches studied :
• Binary metallic oxides (NiO, TiO, HfO2) and « inert »electrode (Pt)• SiO2 or low k as dielectric and Cu as soluble electrode
Electrical results on integrated resistors:
• NiO and TiO shows unipolarswitching• HfO2, Cu/SiO2 shows bipolar switching
Example(V.Jousseaume et al.,IITC 2009)
Waser & Aono, Nature
Materials,n°6,Nov2007
-Unipolar and Bipolar switching-Filamentary conduction - Cation and Anion induced Redox (Ag, Cu, O,…) -Molecules(PEDOT, Cu TCNQ,…)
71
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
-4T SRAM
- cold end process(bonding).
Opportunities for other SC(Ge,...)
- improved layout
-dynamically controlled VT:
improved RNM and SNM
Monolithic 3D
LETI: P.Batude et al., ICICDT June 2008,
Best Student paper Award
72
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
3D integration :vertical plugged polysilicon channelNAND Flash
Bit-Cost Scalable (BiCS) technology
H.Tanaka et al VLSI Tech Symp, p14,2007
73
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
3D stacked horizontal Nanowire Memory Matrix NAND Flash
LETI: T.Ernst et al., Invited paperIEDM 2008
3D Stacked Channel Integration Scheme (SiGe/Si superlattice epitaxy + selectiveepitaxy) allows for a new 3D crystalline nanowire memory matrix with common gate for
WL and reduced technological steps
74
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Toshiba, Stanford Univ.: K.Abe et al, ICICDT 2008, p.203
Logic + Stacked NVM:
High bandwith,
Power consumption,…
32 nm node : > 1TB/s per 1mm2
Resistive switches
3 D Xbar memory stacked on Logic
75
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
« More, More than, Beyond Moore »Tomorrow’s top added value markets
ITRS 2007
High growth with ‘More than Moore’ technologies:they require expertise in all technical domains and in-
depth knowledge of the targeted markets
76
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
System On Wafer.
Heterogenous Integration
On Silicon
80 µm diameter TSV
imagers packaging
3 µm diameter TSV
stacked ICs
FE RF AlN BAW
filters, switches,
passives
30GHz,; 0,3dB150MHz BW;
Q=2000
77
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Nanowire used for mass detection
- First 200 mm wafers with 3.5 millions NEMS
- Same process as MultiNanowires CMOS NWFET
Capacitive actuation & detection Capacitive actuation & piezo-resistive detection with nanowires Thermo-elastic actuation
& piezo-resistive detection.
15 nm oscillator
LETI: T.Ernst et al., IEDM 2008, Invited talk
Hzzgm /5.0≈δ
Q=870 resonatorGauge width = 80 nm
78
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
3D Roadmap: Overview of architectures
1101E21E31E41E51E61E71E81E9
Vertical 3D via pitch (µm)
Vertical Interconnect D
ensity (cm-2)
Flip chip solder bump min pitch
ITRS C65nm M1 min pitch
ITRS C65nm min Global metal pitch
Multi-level 3D IC(CPU + cache + DRAM + Analog + RF + sensor + IO)
3D Stacked memory (NAND, DRAM, …)
0.11101001000
2007 2009 2012 >2014
100% filled via
Vertical device on CMOS (NTC, NW, NEMS)
Low density 3D via Chip-level bonding
Logic ( multicore processor with cache memory)
Image Sensor
Digital Signal Processor
Via size=50µm
Via size=5-30µm
Via size=<5µmCPU
Cache memory
Via size=<2µmCPU
Cache Memory
DRAM / NVM
Analog
RF Power
Sensor I/O
Sensor I/O
High density 3D via wafer-level bonding
CMOS Image sensor (Sensor + DSP + RAM)
Targets for MEDEA+ project
65nm
45nm
32nm
ITRS
Optical
Interconnects
InP/SOI µ-laser1.6µm 0.5mA
Gephotodetector
79
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Beyond CMOS
ITRS 2007
Opportunities from CMOS (Graphene, Diamond, CNT)
to Beyond CMOS
µ0Graph=250 000cm2/.s
t Diamond, C spin decoher.=1
-Confined coherent
electronic waves
- Spin transfer
BalisticTransport
80
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Single Electronics SET
Coulomb blockade principle
LETI: G.Molas WODIM 2002
SEMemory
Wc
≈≈ ≈≈20
nm
Lc ≈≈≈≈ 20 nm
S
Si-dot
D
G
50 nm
Wc
≈≈ ≈≈20
nm
Lc ≈≈≈≈ 20 nm
S
Si-dot
D
G
50 nm
81
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Beyond CMOS candidates
• Carbon Nanoelectronics• High Performance, Low Power, Spintronics,
• Atomic switch, Electrochemical Metallic Switch• Memories and Mixing logic w memories
• CMOL and programmable switches• System architecture solution
• Coupled Spin Transfer• High Endurance NVM
• Collective Spin Transfer• Magnetic Cellular Automata
• Single Electron Transistor• Sensing, stochastic logic
• NEMS switches• Low Power and Reconfigurable Systems
ITRS, ERD section
S.Deleonibus , in « La Micro-Nanoélectronique. Enjeux et Mutations »
Editors JL leray, JC Boudenot, J.Gautier, CNRS Editions
82
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
More Moore
More thanMoore
Dual channel
xsSOI(N)/ Ge(P)
Advanced Devices and Systems Future Vision
UTBOX
22nm 16nm <11nm
sSOI
2010 20132009 2014 2016
FDSOI
11nm
Std SOI
HP options
Nanowire
3D Nanowires
3D stacked devices3D
Logic
2012 2015
3D
Year of transfer to Industry Development
III-V/Ge Heat sink C
Car
bon
elec
tron
ics(
Gra
phen
e, D
iam
ond)
Memory storing (SRAM, NVM) -
ZDRAM
3D stacked Mixed functions:
NV Logic +sensors/polymers
X bar
3D Sensing/Actuation
Bio, Mechanical &
Chemical –
(functionalization,
NEMS, Single
electronics, RF,
opto,… )
Diversified Logic(association to Memory, Passives, Sensors,…)
Beyond CMOS (e-wavesconfinement, Spin electronics)
Si
FeFe
Si
FeFe
83
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Conclusion :Nanoelectronics CMOS from Devices to Systems Perspectives
• Innovation from strong association System/Device/Materials Science and Engineering
• Si CMOS: Nanoelectronics Base platform beyond ITRS• Low Power consumption: major challenge (sub 1V VDD
CMOS). => Device/ system architecture optimization
(GAA nanowires, low slopes,design, 3D)=> Opportunities for new materials
(revised low BG III-V, Carbon)• Heterogeneous 3D co-Integration on Si, Low Power:
Add Functionalities for diversification. Monolithic, 3rd dimension in device, Stacked mixed functions, System On Wafer
• Durable Low Power solutions: health, environment, quality of life, IST,…
84
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
2006
Thank you for your attention
Acknowledgements
Professors Jean-Pierre Colinge (Tyndall), D.Tsoukalas(Univ. Athens)
ESSDERC 2009 Short Course and Program Committees Organization
CEA LETI Co-workers - Silicon Technologies Divisions
F.Andrieu, B. de Salvo, T.Ernst, O.Faynot, J.Buckely, C.Le Royer,
G.Molas,T.Poiroux, M.Vinet, O.Weber, M.Aid, P.Robert, N.Sillon,
G.Poupon
85
2008
© CEA 2006. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
S.Deleonibus, ESSDERC Short Course, September 2009
Electronic Device Architectures for the Nano-CMOS Era
From Ultimate CMOS Scaling to Beyond CMOS Devicesedited by Simon Deleonibus (CEA-LETI, France) Cloth July 2008 978-981-4241-28-1
Discusses the scaling limits of CMOS, the leverage brought by new materials, processes and device architectures (HiK and metal gate, SOI, GeOI, Multigate transistors, and others), the fundamental physical limits of switching based on electronic devices and new applications based on few electrons operation
Weighs the limits of copper interconnects against the challenges of implementation of optical interconnects
Reviews different memory architecture opportunities through the strong low-power requirement of mobile nomadic systems, due to the increasing role of these devices in future circuits
Discusses new paths added to CMOS architectures based on single-electron transistors, molecular devices, carbon nanotubes, and spin electronic FETs
Available at Amazon.com or any good bookstores.