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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Comparadorestructuralentity is
port(
a,b: in std_logic_vector (0 to 1 );
c: out std_logic);
end Comparadorestructuralentity;
architecture Comparadorestructuralarchitecture of Comparadorestructuralentity is
signal x: bit_vector(0 to 1);
begin
U0:xnor 2 port map (a(0), b(0), x(0));
U1:xnor 2 port map (a(1), b(1), x(1));
U2:and 2 port map (x(0), x(1), c);
end Comparadorestructuralarchitecture;
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ibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Comparadorifentity is
port(
a,b: in std_logic_vector( 1 downto 0 );
c: out std_logic );
end Comparadorifentity;
architecture Comparadorifarchitecture of Comparadorifentity is
begin
process (a,b)
begin
if (a=b) then
c
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Comparadorwhenentity is
port(
a,b: in std_logic_vector ( 1 downto 0 );
c: out std_logic );
end Comparadorwhenentity;
architecture Comparadorwhenarchitecture of Comparadorwhenentity is
begin
c
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Comparadorxnorentity is
port(
a,b: in std_logic_vector( 1 downto 0 );
c: out std_logic);
end Comparadorxnorentity;
architecture Comparadorxnorarchitecture of Comparadorxnorentity is
begin
c
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Decodificadorcaseentity is
port(
a: in std_logic_vector ( 3 downto 0 );
d: out std_logic_vector ( 0 to 6 ) );
end Decodificadorcaseentity;
architecture Decodificadorcasearchitecture of Decodificadorcaseentity is
begin
process (a)
begin
case a is
when "0000" => d d d d d d d d
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when "1000" => d d d
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Decodificadorifentity is
port(
a: in std_logic_vector ( 3 downto 0 );
d: out std_logic_vector ( 0 to 6 ) );
end Decodificadorifentity;
architecture Decodificadorifarchitecture of Decodificadorifentity is
begin
process (a)
begin
if a="0000" then d
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elsif a="1000" then d
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Decodificadorwithentity is
port(
a: in std_logic_vector (3 downto 0 );
d: out std_logic_vector (0 to 6 ) );
end Decodificadorwithentity;
architecture Decodificadorwitharchitecture of Decodificadorwithentity is
begin
with a select
d
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end Decodificadorwitharchitecture;
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Decodificadordecimalentity is
port(
x: in std_logic_vector ( 3 downto 0 );
a, b, c, d, e, f, g, h, i , j: out std_logic );
end Decodificadordecimalentity;
architecture Decodificadordecimalarchitecture of Decodificadordecimalentity is
begin
process (x) begin
a
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if x = "0000" then
a
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Flipflopdentity is
port(
D: in std_logic_vector ( 0 to 7 );
clk: in std_logic ;
Q: out std_logic_vector ( 0 to 7 ) );
end Flipflopdentity;
architecture Flipflopdarchitecture of Flipflopdentity is
begin
process (clk) begin
if (clk'event and clk ='1') then
Q
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Multiplexorboleanoentity is
port(
a, b, c, d: in std_logic_vector ( 1 downto 0 );
s: in std_logic_vector ( 1 downto 0 );
z: out std_logic_vector ( 1 downto 0 ) );
end Multiplexorboleanoentity;
architecture Multiplexorboleanoarchitecture of Multiplexorboleanoentity is
begin
z(1)
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end Multiplexorboleanoarchitecture;
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Sistemasecuencialentity is
port(
clk, x: in std_logic ;
z: out std_logic );
end Sistemasecuencialentity;
architecture Sistemasecuencialarchitecture of Sistemasecuencialentity is
type estados is (d0, d1, d2, d3);
signal edo_presente, edo_futuro: estados;
begin
proceso1: process (edo_presente, x) begin
case edo_presente is
when d0 => z
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if x='1' then
edo_futuro
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end Sistemasecuencialarchitecture;
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Sistemasecuencial2entity is
port(
clk, x: in std_logic ;
z: out std_logic );
end Sistemasecuencial2entity;
architecture Sistemasecuencial2architecture of Sistemasecuencial2entity is
type estados is (q0, q1, q2, q3, q4);
signal edo_pres, edo_fut: estados;
begin
proceso1: process (edo_pres, x) begin
case edo_pres is
when q0 => z
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if x = '0' then
edo_fut
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end process proceso1;
proceso2:process (clk) begin
if (clk'event and clk = '1') then
edo_pres
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