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May 2004 1
© 2004 A ctel Corporation
Designing Clean Analog PLL Power Supply in aMixed-Signal Environment
IntroductionMost system -level de sign s involve a mix of b ot h a na log a nd d igita l circuit compo nen ts. In some system s, a
single integrated circuit may consist of both. For instance, Actel's Axcelerator family of FPGA devices
contains analog clock-conditioning circuits such as Phase Locked Loops (PLLs) in addition to the digital
circuits. In gen eral, an alog component s operate in the transistor's act ive reg ion a nd are very sensit ive t o
disturba nces in its supply volta g e. Thus, a low noise ana log po w er-supply netw ork is a stringe nt
requirement fo r the proper operat ion o f the se component s. Noise due t o variat ions in the po w er supply
voltag e can be coupled in to the a nalog po rt ion o f the chip and may become a mplif ied a long w ith the
desired sign a l. This ca n result in processing errors and a ffe ct th e f unctiona lity o f t he syste m. This
applicat ion note discusses some o f th e issues related to noise conta mination o f th e a nalog component s in
a mixed signal environment and provides useful suggest ions for designing a clean analog supply to
minimize its eff ects. All sugg estions in this documen t a re ap plicable t o b ot h Flash and Axcelera to r devices
w ith the except ion o f “ Techniqu e 1: Use o f Pow er Supply Filters” . The a pplicatio n fo r Axcelerat or a nd
Flash de vices in “ Techniqu e 1: Use o f Pow er Supply Filters” are slightly different an d a re described below .
Sources of Power-Supply NoiseDigita l CMOS circuits consume dyna mic switching po w er. The dyn a mic current d raw n from t he po w er
supply leads to frequency-dependent IR (voltage) drops in the VDD and VSS traces of the printed circuit
bo a rd (PCB). This phen om eno n is called g round bo unce on the VSS side . The g round bo unce is relat ed t o
the parasit ic inductance of the package pins of the integrated circuit (IC), device ground, and system
ground . The dyna mic current can tran sform into no ise by contributing a n am ount o f voltag e eq ual to
EQ 1
betw een the system g round and device ground (Fig u re 1 on p a g e 2).Since various compo nents ma y share the VDD an d VSS plane s or busses as a source of p ow er, an y la rge
volta ge fluctua t ions on the PCB may violate the volta ge noise rat ing of these component s. Such noise, if
not reduced, can produce logical errors and othe r undesirab le effects. The problem is more pronounced if
the noise is coupled to the analog port ion of a mixed-signal integrated circuit as it can lead to jit ter,
distort ion, and reduced performance of the analog components. I t is important to properly separate the
dig ita l a nd a na log po w ers supplies to m inimize th e noise levels a s much as possible in a m ixed -sig na l
environment.
Techniques to Reduce Analog Power-Supply Noise
Technique 1: Use of Power Supply Filters
For Flash d evices, a noise f il ter betw een the pow er supply and the device po w er pins, a s show n in Figure 2o n pa g e 2, can b e used to f ilter out low an d/or high freque ncy differential no ise b etw een AVCC an d
ground tha t might couple into t he de vice from the digita l pow er pin. This can be implemente d b y using
an inductor, L1, and a large polarized capa citor C3 in pa rallel w ith a set o f t w o small ceramic high-
freq uency capa citors C1 and C2.The impeda nce of inductor L1 is selected to be much grea ter th an tha t o f
the ana log component in order to iso la te the a nalog do main f rom the dig it a l doma in a t low, medium and
high freq uencies. This is because L1 w ill be seen a s an o pen circuit a t t hese freq uencies. The t w o sma ll
ceram ic capacitors need to be placed nea r the device pow er pins (less than one inch f rom PLL pow er an d
g round pins). The purpo se of th e smaller ca pa cito rs is to filter the h igh f req uency sw itching noise, w hile
the p urpose of t he larg er capa cito r is to f ilter ou t low freq uency supply ripple no ise. This techniq ue can b e
V Ldi
dt----!
Application Note AC204
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Designing Clean Analog PLL Pow er Supply in a Mixed-Signal Environme nt
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combined w ith “ Techniq ue 3: Use Wide Traces for Analog Pow er” on pa ge 3. Plea se refer to “ Appendix”
o n pa g e 6 fo r a sample implement at ion of such a f i lter.
The a na log pow er supply for Axcelerat or devices uses a " f loa t ing g round" approa ch to eliminate no ise.
Theref ore th e sugg ested f ilter in this section is implement ed d ifferen tly. Please refer to figu re 2-3 on pa g e
20 of t he Axcelerat or da ta sheet fo r the recomme nded implement at ion.
Samp le Filt erFigure 1 Sources of Parasitic Inductance Causing Ground Bounce
Figure 2 • Sample Filter
Packag e Bon d Wire
Pa cka g e Tra ce Packag e Pin
System Ground
Device Grou nd
Current Source d uring a '0-1'Tra nsit io n
Current Sink d uring a '1-0' Tra nsitionCont ributing to GND Bounce
(di/d t )
(di/d t )Output Pad
VCC
DeviceFilterVCC
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Designing Clean Analog PLL Power Supply in a Mixed-Signal Environment
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Con t ent s of th e Fil ter
Technique 2: Separation of Digital and Analog Supplies with Regulators
Separa te supply output s should be implement ed to supply pow er to the digita l an d a na log pow er pins of
the device. One can benefit from the inherent higher noise reject ion characterist ics of the voltage
regulato rs, but it should b e verif ied w hethe r the selected regulato rs do provide sufficient reject ion.
Addit iona lly, the insert ion of volta ge regulato rs bef ore the f ilter can provide isolat ion o f pow er betw een
the analog and digital supplies (Fig u re 2 o n p a g e 2). This minimizes the switching noise prod uced b y the
digita l electronics from interfering w ith the a nalog component s.
Technique 3: Use Wide Traces for Analog Power
The u se of separa te plane s on t he PCB should b e implemen ted fo r DVCC, DGND, AVCC, a nd AGND. For t he
optimum solution, the AGND and the DGND planes should be connected together at the power supply
source. This ensures that bot h planes are a t th e same pot ential , w hile the transfer of n oise from the d igital
to t he ana log do ma in is minimized.
This pow er an d g round plan es approach a llow s the use of vias to direct ly connect t he compone nt pins to
the G ND or VCC planes instead of using traces. As traces become longer, parasitic capacitance, inductance,
and coupling noise betw een neigh boring tra ces increase.
Add ing extra layers on t he PCB ma y not alw ays be possible due t o cost and oth er design constraints. For
example if the number of analog components is small compared to digital components, i t may not be
reasona ble to ded icate an ent ire pow er and g round plane just fo r the ana log components. Instead , a w ide
trace can be implement ed on a sign al plan e to serve as the an alog supply for the a na log pa rts (Figure 5 on
pa ge 4). This trace is made ma ny t imes w ider tha n reg ular signa l traces to minimize t he a mount of
Figure 3 • Power Supply Filter and Possible Implementation
Figure 4 • Separation of AVCC and DVCC by Means of Power Regulators
Digita l pow er pins
(DVCC)
To t he d evice a na log
po w er pin (AVCC)
L1
C1 C2 C3
Pow er SupplyRegulator
(Analog)
Regulator
(Digital)
AVCC
DVCC
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Designing Clean Analog PLL Pow er Supply in a Mixed-Signal Environme nt
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resista nce and to h ave it larg e enoug h to b e considered a " plane." The sam e concept can be a pplied to
the analog ground. Another wide trace or island of conducting material posit ioned close to the analog
device in ano ther signa l layer can provide the g round " plane." The AGND " plane" should be connected to
DGND at th e pow er source to m inimize no ise tra nsfer. This ap proa ch still a llow s the use of vias to conne ct
surface-mount ed compon ents to the supply and ground .
Technique 4: Shorten the Current Loops as Much as Possible
In high-speed circuits , the path of the signal current going to ground is always along the path of least
inducta nce. The low inducta nce pat h is locat ed d irectly under the signa l's cond uctor (the PCB trace). La rge
current loo ps can increase the signa l rise t ime due to increased pa rasit ic capa cita nce an d contribute to
crossta lk or coupling be tw een t w o cond uctors.
Adding bypass or decoupling capacitors can shorten the return path from analog and digital VCC t o
ground an d therefo re reduce the noise a ssociat ed w ith I/O switching. Capacitors w ith low intrinsic
inductance and resistance should be chosen. Place them as close as possible to each of the analog and
digital VCC pins to minimize pat h inductance bet w een t he pin a nd t he capa citor. These bypass capacitors
provide local e nergy stora ge and supply the d ynamic current req uired by t he sw itching circuits. Bypass
capacitors must be larg e eno ugh to supply the required current fo r a few na nosecond s (ns).
The a mount of current t he capa citor nee ds to source depe nds on the load tha t th e device out put is driving
and the voltage dips that can be tolerated. EQ2 shows how to calculate the capacitance required for a
de vice opera ting a t a n I/O voltag e of 3.3V w ith 12 out puts. Ea ch output is driving a 70 " load that is
assumed t o be m uch greate r than t he output resista nce of the d river.
Tot a l current n eed ed to source is
EQ 2
Assume that , as a requirement of the design, the voltage on the VCC bus can not drop mo re tha n 50 mV,
an d t he capa citor is needed to source this current fo r 2 ns.
Define current across a capacitor
EQ 3
Figure 5 • Example of Using Wide Traces Instead of an Entire Plane
Wide Trace
12 3.3V
70"
-----------# 566mA!
IC
CdV
dT-------!
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Designing Clean Analog PLL Power Supply in a Mixed-Signal Environment
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Where
Solving for Capacitance
EQ 4
Substitut ing t he required values into the eq uat ion
EQ 5
Actel also recommend s using a mix of de coupling capa citors of different sizes to provide go od decoupling
a cross a w ide freq uency rang e. For exam ple 0.1 µF, 0.01 µF, 1000 pF a nd 100 pF ceramic cap a cito rs can b e
scat te red throug hout to ma ximize the filtering effe cts.
ConclusionDigita l systems w ill cont inue to run a t f aster an d f aster clock speeds and pose a challeng e to the system-
bo ard designe rs. Extreme care must be ta ken in bo ard layouts and filtering circuits to ensure tha t d igital
logic do n ot couple sw itching no ise into the an alog dom ain. The g uidelines described in this do cument
out l ine some of the areas that board designers need to be aware o f in designing a more robust and
reliable system, incorporat ing bo th a na log a nd digital circuits.
List of Changes
IC = Value o f current being sourced by the capac itor (Amperes)
dT = Amount o f t ime t he current is sourced fo r (seconds)
d V = M a xim u m a llo w a b le vo lt a g e d ro p (Vo lt s)
C = Ca pa cit a nce ne ed ed (Fa ra d s)
Previous version Changes in current version 51900071-1 Page
51900071-0* “ Technique 1: Use of Power Supply Filters” was updated to highlight the
differences between Flash and Axcelerator
page 1
Note : * This is the part number located on t he last page of t he document.
C IC
dT
dV-------!
C 566 10-3
s#$ % 2 10
-9s#
50 10-3
V#--------------------------- 22.64&F 0.023&F! ! !
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Designing Clean Analog PLL Pow er Supply in a Mixed-Signal Environme nt
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AppendixThe sam ple schem e presente d h ere uses a 6.8 µH ind uctor, 10 µF g eneric electrolytic ca pa cito r, 10 nF an d
0.1 µF ceramic high -freq uency ca pa cito rs to d ecouple the sw itching noise. No g round filter is req uired,
since the de scribed LC filter ensures tha t t he vo ltag e d ifference V(diff) bet w een V(Ana log ) a nd V(GND) is
consta nt a t an y frequency, therefore a ct ing a s a f i lter for bot h pow er and g round. In this example, up to
three PLLs can be connected to the f il tered analog supply as long as the distance of high frequency
capacitors can be kept below one inch from ea ch ana log supply and g round pin of the d evice.
Example of Capacitor and Inductor Selection
Selectio n f or 100 nF Capacito r
Prod ucer BC comp on ent s, Type X7R, 100 nF, 16V
BC compon ent s pa rt numb er: 0603B104K160BT
Digikey Pa rt num be r (qu a nt ity <10): BC1254CT-ND
Digikey P a rt num be r (qu a nt ity >10): BC1254TR-ND
Selectio n f or 10 nF Capacito r
Surface mo unt ceram ic capacitor
Prod ucer BC comp on ent s, Type X7R, 10 nF, 50V
BC compon ent s pa rt numb er: 0603B103K500BT
Digikey Pa rt num be r (qu a nt ity <10): BC1252CT-ND
Digikey P a rt num be r (qu a nt ity >10): BC1252TR-ND
Select ion f or 6.8 &H Inductor Unshielded surface mo unt inductor
Producer Delevan, Q= 7.9 at 30 MHz, maximum current
Delevan com pon ent s part n umb er: 1210-682J
Digikey Pa rt num be r (q ua nt ity <500): DN10682JCT-ND
Digikey Pa rt num be r (qu a nt ity >500): DN10682JTR-ND
Figure 6 • Sample Implementation of the Power Supply Filter
Digital pow er pins To t he d evice a na log
pow er pin
6.8 µH
10 nF 0.1 nF 10 µF
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51900071-1/05.04
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