Partition-Driven Standard Cell Thermal Placement
Guoqiang ChenSynopsys Inc.
Sachin SapatnekarUniv of Minnesota
For ISPD 2003
Outline
IntroductionThermal Placement
Simplified Thermal Model for Partitioning Partition-Driven Thermal Placement
Experimental ResultsConclusion
Thermal problem is projected to be a major bottleneck for the next-generation circuits
Placement is the natural starting point in the design process where we take thermal problem into consideration
Why Thermal Placement?
Courtesy Intel
Typical Heat Conduction Environment of the Wafer
xz
y
heat sources
...
ambient temperature...
wafer... ...
+~
+~
Thermal Equation
Partial differential equation We will consider the steady state version:
Poison Equation
Applying finite difference method and eliminating internal mesh nodes yields
G T = P G is the thermal conductance matrix T and P are the temperature and power density vector
over mesh nodes on the top surface of the wafer
Thermal Placement
Minimize max. temperature variationProblem formulation:
Find permutation of Pi: {1, …,n} {1,…n}
such that δT = max|Ti-Ti,neighbor| is minimized(No wire-length/timing considerations)
This is a NP-hard problem alreadyPrevious work
Chu and Wong, TCAD98: matrix synthesis Tsai and Kang, TCAD00: simulated annealing
based
Partition-Driven Thermal Placement
Partition based placement methods are powerful methods to solve the placement problems
Could we easily extend Tsai and Kang’s work for partition driven placement?
Two Obvious Approaches
Use equation G T=P directly at each partitioning step During the early partitioning stages, we do not
know where the cells will be eventually located Too expensive to compute
Compute the desired power distribution, and try to match the power distribution during partition stages Difficult to get an exact budget for the power
distribution We are not optimizing the temperature directly
Outline
IntroductionThermal Placement
Simplified Thermal Model for Partitioning Partition-Driven Thermal Placement
Experimental ResultsConclusion
Simplified Thermal Model for Partitioning
It is known that Poisson equation can be solved with Multigrid method effectively
Our model is motivated by one interpretation of the mutligrid methods
Multigrid Solver for Poisson Equation
The multi-grid method solves different spatial frequency components at different levels of mesh. Low-frequency components: coarse mesh High-frequency components: fine mesh
The temperature distribution across the chip can be considered as a superposition of low spatial frequency components and high spatial frequency components
Top-down Partition Process
Thermal grids
Standard cell
This process can be considered as series of operations on a gradually refined meshes
Basic Ideas
At each partition level, we are only concerned about the spatial distribution of the temperature corresponding to the current coarse grids
In the early stage of partitioning, we are mainly concerned about the low frequency components
As the mesh is refined, higher frequency terms, corresponding to local variation of temperature, will be considered
At each partition level, we are only interested in controlling the temperature differences between the current coarse grids.
Simplified Thermal Model
We will assume that the temperature within each grid is same.
The First Step in Top-down Partitioning
Original Equation:GT=P T, P are N2 x 1 vector,
and G is a N2 x N2
matrix
1 N1
N
TL TR
irighti
ilefti
R
L
jirightjrighti
jileftjrighti
jirightjlefti
jileftjlefti
P
P
T
TGG
GG
,,
,,
Now the equation is simplified to:
This process can be extended to general case where we partition the chip into k regions
Resulting G matrix is a k x k matrix and it is positive definite
Extension to General Case
Outline
IntroductionThermal Placement
Simplified Thermal Model for Partitioning Partition-Driven Thermal Placement
Experimental ResultsConclusion
Before Partitioning a New Level
Compute the simplified thermal conductivity matrix G
Prepare the matrix for incremental update
Before Partitioning of a Block
Generate multiple initial solutions and compute δT
Set the thermal budget for the current partition to be (1-α) δTmin +
α δTmax
Pick the initial partition with lowest δT as the initial solution for partitioner
When We Move One Cell
Compute power changes induced by the cell movement
Compute temperature changes for blocks that are affected by the move.
Compute δT for the current move, and check against the budget to see if we will accept the move or not
Outline
IntroductionThermal Placement
Simplified Thermal Model for Partitioning Partition-Driven Thermal Placement
Experimental ResultsConclusion
Experimental Results
BenchmarkName Cells Wirelength Tmax Tave δT Wirelength Tmax Tave δT
struct 1952 0.0476 15.3 13.2 0.67 0.0501(105%) 15.6 13.1 0.5(75%)primary1 833 0.048 11.7 9.74 0.56 0.496(103%) 11.9 9.75 0.54(96%)primary2 3014 0.184 40.3 34.6 1.95 0.192(104%) 39.9 34.4 1.52(78%)biomed 6514 0.258 85.8 44.4 13.4 0.260(101%) 64 45.2 5.64(42%)industry212637 1.04 55.6 44.1 4.6 1.04(100%) 57.5 44.1 3.92(85%)industry315433 0.986 57.3 44 2.5 1.03(104%) 56.6 43.7 1.80(72%)avqsmall21918 0.637 138.5 37.6 40.9 0.667(105%) 111.5 37.8 34(83%)avqlarge 25178 0.701 158.2 36.4 45.4 0.746(106%) 102 35.7 27.6(61%)
Without thermal constraints With thermal constraints
Maximum On-Chip Temperature Variation
0%
20%
40%
60%
80%
100%
120%
without thermalconstraintwith thermalconstraint
Maximum Temperature
0
20
40
60
80
100
120
140
160
without thermalconstraintwith thermalconstraint
Conclusion
We presented an simplified thermal model to take temperature directly as partition constraints.
The basic idea is we want to control different spatial frequency of the temperature variation at different partition level
We proposed a top-down partition-driven placement scheme to use the simplified model
EndEnd
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