Journal of
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Journal of Semiconductor Devices and Circuits
Journal of Semiconductor Devices and Circuits
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Rupendra Kumar SharmaMicroelectronics Department, Faculty of Electrical Engineering, Czech Technical University in Prague, Czech Republic.
Servin RathiSchool of Electronics and Electrical
Engineering,Sungkyunkwan University, Republic Of Korea.
I take the privilege to present the print version for the Volume 1 Issue (2) of Journal of Semiconductor
Devices and Circuits. The intension of JoSDC is to create an atmosphere that stimulates
creativeness, research and growth in the area of semiconductor devices, circuits and allied
applications.
The development and growth of the mankind is the consequence of brilliant Research done by
eminent Scientists and Engineers in every field. JoSDC provides an outlet for Research findings and
reviews in areas of found to be relevant for national and international recent developments &
research initiative.
The aim and scope of the Journal is to provide an academic medium and an important reference for
the advancement and dissemination of Research results that support high level learning, teaching and
research in the domain of semiconductor devices, circuits and allied applications.
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I hope you will enjoy reading this issue and we welcome your feedback on any aspect of the Journal.
Dr. Archana Mehrotra
Director
STM Journals
Director's Desk
STM JOURNALS
1. 3D Simulation of Multi-Gate Mosfet Analysis for Analog Circuit Design Parameters Nirmal D., Chacko J. K., Thaya J. S., Manoj S., Lyndon B. G., Jebalin B. K. 1
ContentsJournal of Semiconductor Devices and Circuits
JoSDC (2014)© STM Journals 2014. All Rights Reserved
Journal of Semiconductor Devices and Circuits
Volume 1, Issue 2
www.stmjournals.com
3D Simulation of Multi-Gate Mosfet Analysis for Analog
Circuit Design Parameters
Nirmal D.*, Chacko J. K., Thaya J. S., Manoj S., Lyndon B. G., Jebalin B. K.
Department of Electronics and Communication Engineering, Karunya University, Coimbatore
641114, Tamilnadu, India
Abstract Chip density and performance improvements of semiconductor devices have been driven by their aggressive scaling. The performance of multi-gate FET for analog applications is
explored in this paper. Analog operation of CMOS devices and its parameters are very
important for future cutting edge technologies. The multi-gate technology shows excellent scalability and better immunity to short channel effects in MOSFETs. They are being
easily assessed for CMOS applications beyond the 45 nm of the SIA roadmap 2010.
Moreover, the optimization of the tri-gate device is done by varying the length of the three gates. The scalability of nanoscale device is done and the comparison of the threshold
voltage, Ion current, Ioff current, Ion/Ioff ratio, and transconductance for different multi-gate FET structures are analyzed.
Keywords: tri-gate FET, threshold voltage, Ion current, Ioff current, Ion/Ioff ratio,
transconductance.
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