Ibrahim Hazmi | CENG 450 LAB
Introduction to VHDL Registers File & ALU
Ibrahim Hazmi - 2018
LAB 2
Ibrahim Hazmi | CENG 450 LAB
VHDL overview
CENG 450 - iHaz - 2018
Ibrahim Hazmi | CENG 450 LAB
Entity
ENTITY mux IS PORT ( a, b, c, d : IN STD_LOGIC; s : IN STD_LOGIC_VECTOR (1 DOWNTO 0); x : OUT STD_LOGIC ); END mux;
Architecture
ARCHITECTURE dataflow OF mux IS BEGIN x <= a WHEN (s = "00") ELSE
b WHEN (s = “01") ELSE c WHEN (s = “10”) ELSE d;
END dataflow;
VHDL Terms
Symbols are Labels, constants, and variables (Conditions of symbol's name)
Ibrahim Hazmi | CENG 450 LAB
Entity
ENTITY register IS PORT ( clock, reset, enable : IN STD_LOGIC; D : IN STD_LOGIC; Q : OUT STD_LOGIC ); END register;
Architecture With Process
ARCHITECTURE behaviour OF mux IS BEGIN PROCESS (clock, reset, En)
BEGIN IF (reset = '1') THEN
Q <= '0'; ELSIF (rising_edge(clock)) THEN
IF (enable ='1') THEN Q <= D;
END IF; END IF;
END PROCESS; END behaviour;
VHDL Terms
Ibrahim Hazmi | CENG 450 LAB
Configuration Describes which behaviour to use for each entity
Package Collection of data types and subprograms in a design
Driver This is a source on a signal
Bus A kind of signal that may have its drivers turned off
Attribute Predefined data about VHDL objects
Generic Parameter that passes information to an entity
Other VHDL Terms
Ibrahim Hazmi | CENG 450 LAB
VLSI Design Levels
Ibrahim Hazmi | CENG 450 LAB
XC6SLX25
Xilinx FPGA
Ibrahim Hazmi | CENG 450 LAB
CENG450 Project Registers File ( RF)
and ALUIbrahim Hazmi - 2018
Ibrahim Hazmi | CENG 450 LAB
Register File & ALU8 16-bit registers: r0, r1, r2, r3, r4, r5, r6, r7
Read operation: the register file gets rd_index1 and rd_index2 to deliver the corresponding rd_data1 and rd_data2.
Write operation: the register file writes the value on wr_data to the register determined by wr_index, when wr_en is one.
alu_mode ALU operation0 Nop1 Add2 SUB - Subtract3 MUL- Multiply4 NAND5 SHL - Shift Left Logical6 SHR - Shift Right Logical7 TEST
Ibrahim Hazmi | CENG 450 LAB
Register File
Ibrahim Hazmi | CENG 450 LAB
ALU
Ibrahim Hazmi | CENG 450 LAB
Some notes about ALU➡ ALU components can be built behaviourally or
structurally. ➡ Signed data type is recommended for (+/-/*)
operations, using “ieee.std_logic_arith.all”. ➡ Multiplication (*) results in 32-bit output. The
decision on the higher 16-bit should be made. ➡ SHL & SHR can be performed using Barrel
Shifter or by a simple LOOP of a single shift, e.g, for i in 1 to 16 loop if i <=conv_integer(in2) then temp := temp(6 downto 0) & ‘0'; end if; end loop;
➡ TEST is the only instruction that generates Flags
Ibrahim Hazmi | CENG 450 LAB
More notes about ALU
➡ You need to decide how to deal with the higher 16-bit of the output in Multiplication (*).
➡ It it suggested that you have another output port in order to accommodate the higher and lower 16-bit result2: out std_logic_vector(15 downto 0); : : signal r32: std_logic_vector(31 downto 0); : : r32<= std_logic_vector(unsigned(in1) * unsigned(in2)); result <= r32(15 downto 0); result2<= r32(31 downto 16);
Ibrahim Hazmi | CENG 450 LAB
References
https://en.wikipedia.org/wiki/Control_unit
https://voer.edu.vn/file/7173
http://people.uncw.edu/tagliarinig/Courses/242/RegisterTransfer/BasicControlUnit.gif
http://www.slideshare.net/mekind/basic-computer-organization-and-design-30538899
http://www.vlsiencyclopedia.com/2011/12/finite-state-machine-coding-in-vhdl.html
http://faculty.weber.edu/snaik/ECE3610/09Lec9.pdf
ece.citadel.edu/hayne/elec418/418_05.ppt