Interrupts, Thermistors, Opto-isolators and
PhototransistorsFall 2009
Kipp SchoenwaldStephen Hunte
Joseph Storey
Outline
Interrupts ◦ Vectors and Vector Table◦ Flow Chart◦ Applications
Example 1 Example 2
Thermistors◦ Theory◦ Applications
Opto-isolators◦ Theory◦ Applications
Phototransistors◦ Theory◦ Applications
Interrupts
Q: What are interrupts good for?A: Interrupts provide a means to temporarily suspending current instruction for more
important tasks.
Q: How are interrupts initiated?A: Interrupts are initiated by one of the following:
Hardware interrupts◦ Peripherals such as a printer or fax machine◦ Computer Operator via keyboard, mouse or power on reset button◦ Another computer
Software interrupts◦ Timer resets◦ Timer interrupts◦ Traps◦ Request for input or output◦ Arithmetic overflow error
Q: What is the alternative to interrupt and how does it work?A: Polling – Polling is an loop that continuously looks at all of the inputs.
Kipp Schoenwald
Interrupts
EXAMPLES:1. Problem:
Power Fails (someone kicks the power cord out of your laptop)
Solution: R/C circuit senses impending power loss and runs an interrupt routine that can select the battery as the power supply
2. Problem: Car engine overheats
Solution: Thermal couple senses temperature. Runs a interrupt routine that turns on warning light
Kipp Schoenwald
Interrupts: Vectors
Definitions:1. Interrupt Service Routine (interrupt
handler): This is a “more important” instruction code that interrupts your main program code. The routine is specific to the type of interrupt called.
2. Interrupt Vector: This is an address in memory where the ISR instruction code is located. It is the starting address of the code. (Like a pointer)
3. Interrupt Vector Table: This is a table indicating the interrupt vector
Kipp Schoenwald
ISR CodeBlah blah blahBlah blah blahBlah blah blahBlah blah blah
RTI
$FFF6
Main ProgramBlah blah blahBlah blah blahBlah blah blahBlah blah blah
Interrupts: Vector Table
The interrupt vector table is located:◦ Pg 61 of Reference Manual (thick book)◦ Pg 56 of Device User Guide (medium thick book)◦ Pg 2 of the Reference Guide (thin book).
Kipp Schoenwald
Interrupts: MON12 Vector Table
MON12 interrupt vectors are used. ($0F00-$0FFF )
Kipp Schoenwald
The microcontroller calls ISR’s specified in the $FFxx range.
MON12’s calls ISR’s specified by the user in the $0Fxx range
Interrupts: MON12 Vector Table
The MON12 Interrupt Table shows both the actual Vector Table addresses, and the Ram Vector Table addresses
Kipp Schoenwald
Interrupts: Flow
Back to Main Program
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X I
Software Interrupt (SWI)
Maskable
Wait For Interrupt (WAI)
Mask Set
Hardware Interrupt
Begin Interrupt Program (ISR)
Store MPU Registers to SP
Condition Code Register
Accumulator B
Accumulator A
Index Register (MS)
Index Register (LS)
Program Counter (MS)
Program Counter (LS)SP
SP -1
SP -2
SP -3
SP -4
SP -5
SP -6
Condition Code Register
Stack Pointer
Load Interrupt Vector into PC
CompleteCurrent
Instruction
CompleteCurrent
Instruction
0
1YES
NO
Set Mask (CCR4) (set to 1)
Interrupt VectorClear Mask (CCR4) (set to 0)
Maskable
Wait For Interrupt (WAI)Hardware Interrupt
Mask Set
NO
YES
01
YES
NO
ImportantSlide
Interrupts: Flow: IRQ Example 1
1. If I bit in CCR is not set (I=0) and IRQ goes low for at least φ2 cycle, the IRQ sequence is entered.
2. Internal registers stored to RAM (SP).
3. The IRQ mask bit set (I=1).4. Data at FFF2 gets loaded into
PCH5. Data at FFF3 gets loaded into
PCL6. PC contents go out on address
bus during φ1.7. Contents of the location
addressed enter instruction register and are decoded as first instruction of interrupt routine.
8. If it is a more than 1-byte instruction, additional bytes enter MPU for execution. If not, go to next step
9. After execution, step 7 is repeated for subsequent instructions. This is repeated until “RTI” is executed.
RTI tells the MPU that service is complete and that it may reload the registers and continue the main program from where it left off.
Back to Main Program
Kipp Schoenwald
Software Interrupt (SWI)
Maskable
Wait For Interrupt (WAI)
Mask Set
Hardware Interrupt
Begin Interrupt Program (ISR)
Store MPU Registers to SP
Load Interrupt Vector into PC
CompleteCurrent
Instruction
CompleteCurrent
Instruction
0
1YES
NO
Set Mask (CCR4) (set to 1)
Clear Mask (CCR4) (set to 0)
Maskable
Wait For Interrupt (WAI)Hardware Interrupt
Mask Set
NO
YES
01
YES
NO
Interrupts: Applications: Example 2
Write a routine to interrupt the MCU after 5ms of elapsed time, assuming prescaler is 1. Use output compare (OC) five.
TFLG1 EQU $004E /*OC5 flag*/TIE EQU $004C /*OC5 enable*/TCTL1 EQU $0048 /*OC5 condition*/SECONDAD EQU $FFE4 /*OC reference location*/TCNT EQU $0044 /*counter*/TC5EQU $005A /*OC5*/TIOS EQU $0040 /*timer input capture or output compare select*/
ORG $1000 /*begin routine at a chosen address*/SEI /*set the I bit of the condition code register*/LDAA %0010 0000STAA TIOS /*configures port 5 as output compare (default is 0)*/STAA TFLG1 /*clear previously set OC5 flag*/STAA TIE /*enable OC5 Interrupt*/
configure ports as input or outputLDAB %0000 1100STAB TCTL1 /*OC condition: PA5 = high (for a successful compare)*/LDX #$2000 /*$2000 is the address where you chose to put your ISR*/STX SECONDAD /*stores this address “pointer” to the address that OC refers to.
High byte (20) $FFE4, and Low byte (00) FFE5*/LDD TCNT /*Loads current value of counter*/ADDD #$9C40 /*adds 40,000cycles (5ms) to the current time (this equals the
time when the ISR is to be run)*/STD TC5 /*stores this value to be compared*/CLI /*clear the I bit of the condition code register*/
Kipp Schoenwald
ImportantSlide
Outline
Interrupts ◦ Vectors and Vector Table◦ Flow Chart◦ Applications
Example 1 Example 2
◦ Priorities◦ Interrupt Stack
Thermistors◦ Theory◦ Applications
Opto-isolators◦ Theory◦ Applications
Phototransistors◦ Theory◦ Applications
Interrupts: Stack
• The Stack Pointer Register holds the location of the top of the stack at all times.
• When the CPU detects an interrupt the contents of the register are pushed on the stack.
• After completion of the interrupt the saved registers are retrieved from the stack. The first register pushed onto the stack will be the last register pulled from the stack.
CCR
ACC B
ACC A
X HI
X LO
Y HI
Y LO
RTN HI
RTN LO• RTN – address of next instruction in Main Program, upon return from interrupt.
• X LO and Y LO are the low bytes of X and Y registers.
• X HI and Y HI are the high bytes of X and Y registers.
• ACC A and ACC B are the accumulators.
• CCR is the Code Condition Register
Interrupts: StackInterrupts: StackJoseph Storey
Interrupts: StackInterrupts: Stack
CCR
ACC B
ACC A
X HI
X LO
Y HI
Y LO
RTN HI
RTN LOFirst Pushed In
Last Pulled Off
Last Pushed In
First Pulled Off
Higher Address
Lower Address
Stack Pointer before Interrupt
Stack Pointer after Interrupt
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Interrupts: Priorities
Interrupt Types
Presents
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Interrupts: Priorities
Non-Maskable Interrupts• 6 Non-Maskable Interrupts
• Always interrupts program execution
• Priority over Maskable Interrupts.
• Not subject to global masking
• Sets the X and I bit of the CCR when serviced
Joseph Storey
Interrupts: Priorities
Non-Maskable Interrupts
Priority of Non-Maskable Interrupts
1.POR of RESET pin2.Clock monitor reset3.COP watchdog reset4.XIRQ interrupt5.Unimplemented instruction trap6.Software interrupt (SWI)
Joseph Storey
Interrupts: Priorities
ResetForces MCU to:
◦Assume set of initial conditions◦Begin executing instructions at an assigned
starting addressLike interrupts, resets have a vector to
define the starting address of code to be runUnlike interrupts, they do not return to
original code locationResets have different vectors to allow
execution of individualized code
Joseph Storey
Interrupts: Priorities
When a reset is triggered:The address from the vector is loaded into
the program counterS, X, and I bits are set in the CCRMCU hardware is initialized to reset stateCheck for any interrupts that have
occurred
Joseph Storey
Interrupts: Priorities
Clock Monitor ResetProtects against clock failureSet by CME control bit If enabled, system resets if no clock edges are
detected within a set period.
Computer operating Properly (COP) ResetProtects against software failures (infinite loops, etc)When enabled (NOCOP bit in CONFIG register), resets
if free-running watchdog timer rolls over $FFFFTimer rate is set in the OPTION register. System E-
clock is divided by 215 and further scaled by 1, 2, or 4
Joseph Storey
Interrupts: Priorities
XIRQExternally triggeredPE0 pin low = XIRQ interruptSets X and I bitsRTI returns the X and I bits to original
states prior to execution
Joseph Storey
Interrupts: Priorities
Opcode Trap and SWI
Very low priorityAny enabled interrupt source pending
prior to the initialization of Trap or SWI will take precedence.
Once process has begun neither can be interrupted.
Joseph Storey
Interrupts: Priorities
Maskable Interrupts• 27 Maskable Interrupts
• Sets I bit in CCR when serviced
• Automatically cleared by RTI interrupt
• Follows default priority, but any one Maskable Interrupt can be elevated using HIPRO (Higher Priority)
Joseph Storey
Interrupts: Priorities
Maskable Interrupts
Priority of Maskable Interrupts1. IRQ2. Real-Time Interrupt3. Standard Timer Channel 04. Standard Timer Channel 15. Standard Timer Channel 26. Standard Timer Channel 37. Standard Timer Channel 48. Standard Timer Channel 59. Standard Timer Channel 610.Standard Timer Channel 711.Standard Timer Overflow12.Pulse Accumulator A
Overflow13.Pulse Accumulator Input
Edge14.SPI transfer Complete
15.SCI system16.ATD17.Port J18.CRG PLL Lock19.CRG Self Clock Mode20.Flash21.CAN Wakeup22.CAN Errors23.CAN Receive24.CAN Transmit25.Port P26.PWM Emergency
Shutdown27.VREG LVI
Discussed in Timer Lecture
Joseph Storey
Interrupts: Priorities
IRQOnly external maskable interrupt signalIRQE bit on IRQCR Register
◦IRQE=1: Falling Edge Sensitive◦IRQE=0: Low Level-Sensitive
Peripheral Subsystems (all other Maskable Interrupts)Flag bit and interrupt enable bitATD, Timers, PWM, serial communications,
etc.
Joseph Storey
Interrupts: Priorities
Highest Priority Interrupt (HPRIO)HPRIO register moves one maskable
interrupt to top of priority listCannot change priority of non-maskable
interruptsProcedure to increase priority of
maskable interrupt:◦ Set I bit to disable maskable interrupts◦ Write low byte of interrupt vector to HPRIO◦ Clear I bit to re-enable maskable interrupts
Joseph Storey
Address: $001F
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 1 0 1 1 1 1
PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 -
PSEL[7:1] – Priority Select Bits (HPRIO)◦ Selects one interrupts source to be elevated◦ Can only be written while I-bit in the CCR is set and
maskable interrupts turned off◦ Write the low byte of the maskable interrupt vector to
HPRIO to elevate that maskable interrupt to the highest priority
◦ Ex: writing $DE to HPRIO elevates the Standard Timer Overflow to highest priority (Standard Timer Overflow vector = $FFDE)
Interrupts: PrioritiesJoseph Storey
Outline
Interrupts ◦ Vectors and Vector Table◦ Flow Chart◦ Applications
Example 1 Example 2
◦ Priorities◦ Interrupt Stack
Thermistors◦ Theory◦ Applications
Opto-isolators◦ Theory◦ Applications
Phototransistors◦ Theory◦ Applications
Thermistor
Thermistor - Temperature sensitive resistorTheir change in electrical resistance is very large and precise when subjected to a change in temperature.Thermistors exhibit larger parameter change with temperature than thermocouples and RTD’s.
Thermistor - sensitiveThermocouple - versatileRTD – stable
Generally composed of semiconductor materials.Very fragile and are susceptible to permanent decalibration.
Stephen Hunte
Thermistor Probe
One of many available probe assemblies
TEFLON INSULATION
TEFLON TUBE
2” MIN.
.095” DIA. MAX.
.11 DIA. MAX.
#32 TINNED COPPER WIRE 3” LONG
Stephen Hunte
Thermistor Characteristics
Most thermistors have a negative temperature coefficient (NTC); that is, their resistance decreases with increasing temperature.
Positive temperature coefficient (PTC) thermistors also exist with directly proportional R vs. T.
Extremely non-linear devices (high sensitivity)Common temperature ranges are –100 oF (~-75
oC) to +300 oF (~150 oC)Some can reach up to 600 oF
Stephen Hunte
• An individual thermistor curve can be very closely approximated by using the Steinhart-Hart equation:
A B ln R( ) C ln R( )31
T=
T = Degrees Kelvin
R = Resistance ofthe thermistor
A,B,C = Curve-fitting constants• Typical Graph
Thermistor (sensitive)
RTD (stable)
Thermocouple (versatile)T
V o
r R
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Thermistor R-T Curve
Temperature Measurement
“Wheatstone bridge” with selector switch to measure temperature at several locations
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Thermistor Applications
•Resistor is set to a desired temperature (bridge unbalance occurs)
•Unbalance is fed into an amplifier, which actuates a relay to provide a source of heat or cold.
•When the thermistor senses the desired temperature, the bridge is balanced, opening the relay and turning off the heat or cold.
Temperature Control
high gain amplifier
relay
thermistor
variable resistor for setting desired temperature
Thermistor Applications
• Operation similar to traditional transistors• Have a collector, emitter, and base• Phototransistor base is a light-sensitive
collector-base junction• Small collector to emitter leakage current
when transistor is switched off, called collector dark current
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Phototransistor Background
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Phototransistor Package Types
Phototransistor Construction
• A light sensitive collector base p-n junction controls current flow between the emitter and collector
• As light intensity increases, resistance decreases, creating more emitter-base current
• The small base current controls the larger emitter-collector current
• Collector current depends on the light intensity and the DC current gain of the phototransistor.
Phototransistor Operation
The phototransistor must be properly biased
Basic Phototranstor Circuit
Obstacle Avoidance Example
• Adjust baffle length to obtain a specific detection range
• Use infrared components that won’t be affected by visible light
• Use ~ 220 ohm resistors for LED’s• Use multiple sensors in a row to
detect narrow obstacles
Phtotransistor Summary
• They must be properly biased• They are sensitive to temperature changes• They must be protected against moisture• Hermetic packages are more tolerant of severe
environments than plastic ones• Plastic packages are less expensive than
hermetic packages
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Phtotransistor SUmmary
Optoisolator Background
• Operation similar to relays• Used to control high voltage devices• Excellent noise isolation because switching
circuits are electrically isolated• Coupling of two systems with transmission of
photons eliminates the need for a common ground
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Optoisolator Background
Glass dielectric sandwich separates input from output
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Optoisolator Construction
• Input Stage = infrared emitting diode (IRED)• Output Stage = silicon NPN phototransistor
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Optoisolator Schematic
Contact Info Kipp Schoenwald [email protected] Stephen Hunte [email protected] Joseph Storey [email protected]
References1. Wikipedia.org2. Bishop R., Basic Microprocessors and the 6800