Intel® Stratix® 10 DX FPGADevelopment Kit User Guide
SubscribeSend Feedback
UG-20255 | 2019.12.09Latest document on the web: PDF | HTML
Contents
1. Getting Started............................................................................................................... 41.1. About this Document..............................................................................................41.2. Installing the Intel Quartus® Prime Pro Edition Software............................................. 4
1.2.1. Activating Your License...............................................................................41.3. Downloading the Board Package.............................................................................. 41.4. Installing the Driver for Intel FPGA Download Cable II................................................ 5
2. Development Kit Overview..............................................................................................62.1. Supported Features............................................................................................... 72.2. Recommended Operating Conditions........................................................................ 72.3. Handling the Board................................................................................................ 8
3. Power Up the Development Kit....................................................................................... 93.1. Default Switch Settings.......................................................................................... 93.2. Connectors and LEDs............................................................................................123.3. Performing Board Restore through Board Test System (BTS) .....................................133.4. Controlling On-board Clock....................................................................................14
4. Board Test System (BTS).............................................................................................. 154.1. Preparing the Development Kit.............................................................................. 164.2. Running the Board Test System............................................................................. 164.3. Using the Board Test System................................................................................. 17
4.3.1. Configure Menu....................................................................................... 174.3.2. Sys Info Tab............................................................................................184.3.3. GPIO Tab................................................................................................ 194.3.4. QSFP Tab................................................................................................ 204.3.5. Component DDR4 CH0 Tab........................................................................234.3.6. Component DDR4 CH1 Tab........................................................................244.3.7. DDR4 DIMM CH0 Tab................................................................................264.3.8. DDR4 DIMM CH1 Tab................................................................................274.3.9. Power Monitor......................................................................................... 294.3.10. Clock Controller..................................................................................... 30
4.4. Smart VID Setting............................................................................................... 32
5. Development Kit Hardware and Configuration.............................................................. 335.1. FPGA Configuration.............................................................................................. 335.2. Programming the FPGA Over Intel FPGA Download Cable.......................................... 335.3. Configuration Modes.............................................................................................34
5.3.1. Avalon Streaming Interface x8 Mode.......................................................... 345.3.2. JTAG Mode..............................................................................................37
6. Document Revision History for Intel Stratix 10 DX FPGA Development Kit User Guide..39
A. Development Kit Components.......................................................................................40A.1. Components Overview..........................................................................................41A.2. Power, Thermal, and Mechanical Considerations....................................................... 44
A.2.1. Power Guidelines..................................................................................... 44A.2.2. Thermal Requirements............................................................................. 50A.2.3. Mechanical Requirements..........................................................................51
Contents
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
2
A.3. Clock Circuits...................................................................................................... 53A.4. Memory Interface................................................................................................ 55A.5. PCIe Interface.....................................................................................................56A.6. UPI Interface...................................................................................................... 56A.7. Transceiver Signals: PCIe and UPI Interface............................................................ 57A.8. SlimSAS Connector.............................................................................................. 60A.9. QSFP Network Interface........................................................................................61
A.9.1. Dual Port Controller .................................................................................62A.10. I2C Interface..................................................................................................... 63A.11. QSPI Flash Memory............................................................................................64
A.11.1. Configuration QSPI Flash Memory.............................................................64A.11.2. NIOS QSPI Flash Memory........................................................................64
B. Safety and Regulatory Information...............................................................................66B.1. Safety Warnings.................................................................................................. 66B.2. Safety Cautions................................................................................................... 68
C. Compliance and Conformity Information...................................................................... 70
Contents
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
3
1. Getting Started
1.1. About this Document
This document provides comprehensive guidelines for designing with Intel® Stratix®
10 DX FPGA Development Kit. It covers information about the software installation,board components, and configuration.
Table 1. Ordering Information
Product Ordering Code Device Part Number
Intel Stratix 10 DX FPGA Development Kit(Engineering sample version) DK-DEV-1SDX-P-0ES 1SD280PT2F55E2VGS1
Intel Stratix 10 DX FPGA Development Kit(Production version) DK-DEV-1SDX-P-A 1SD280PT2F55E1VG
1.2. Installing the Intel Quartus® Prime Pro Edition Software
The Intel Quartus® Prime Pro Edition software includes everything you need to designfor Intel Stratix 10 FPGA from design entry and synthesis to optimization, verification,and simulation. For more information about downloading the Intel Quartus Prime ProEdition software, refer to the Download Center for Intel FPGAs.
1.2.1. Activating Your License
Before using the Intel Quartus Prime Pro Edition software, you must activate yourlicense. If you already have a licensed version installed, you can use that license filewith this development kit. Otherwise, follow these steps:
1. Log into your My Intel account.
2. Click on the Intel FPGA Self Service Licensing Center.
3. Locate the serial number printed on the side of the development kit box below thebottom bar code. The number consists of alphanumeric characters and does notcontain hyphens.
4. On the Intel FPGA Self Service Licensing Center page, click the Find it withyour License Activation Code link.
5. In the Find/Activate Products dialog box, enter your development kit serialnumber and click Search.
1.3. Downloading the Board Package
Download the appropriate board package for your Intel Stratix 10 DX FPGADevelopment Kit from the Intel FPGA Development Kits webpage. Unzip the package.
UG-20255 | 2019.12.09
Send Feedback
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
Figure 1. Directory Structure
<package rootdir>
board_design_files
demos
documents
examples
factory_recovery
Table 2. Directory Description
Directory Content Description
board_design_filesContains schematic, layout, assembly, and bill of material board design files. Usethese files as a starting point for a new prototype board design.
demos Contains demonstration applications when available.
documents Contains documentation.
examples Contains sample design files for this development kit.
factory_recoveryContains the original data programmed onto the board before shipment. Use thisdata to restore the board to its original factory settings.
1.4. Installing the Driver for Intel FPGA Download Cable II
The development board includes integrated Intel FPGA Download Cable circuits forFPGA programming. However, for the host computer and board to communicate, youmust install the Intel FPGA Download Cable II driver on the host computer.
Installation instructions for the Intel FPGA Download Cable II driver for your operatingsystem are available on the Cable and Adapter Drivers Information webpage.
1. Getting Started
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
5
2. Development Kit OverviewThe Intel Stratix 10 DX FPGA Development Kit allows you to evaluate theperformance, features, and operation of the Intel Stratix 10 DX device in the F2912BGA package. It features P-tile transceivers with PCIe Gen4 x16 and Intel Ultra PathInterconnect (UPI) interfaces and E-tile transceivers with 25Gx4 or 56Gx2 quad smallform-factor pluggable (QSFP) interfaces. It also supports 4xDDR4 x72 channels withtwo channels supporting the Intel Optane® DC Persistent memory module.
The UPI functionality is enabled by a combination of the appropriate P-Tile settingsand UPI protocol IP core. The FPGA interface to Intel Optane DC Persistent memorymodule requires an Intel memory controller IP core. Both IP cores are available inIntel Quartus Prime Pro Edition software (additional licensing and enablement mayapply).
Figure 2. Intel Stratix 10 DX FPGA Development Kit Block Diagram
3D
UPI_1TX
x4QSFP-2
QSFP-1
25G x4 or 56G x2
x4
25G x4 or 56G x2x20
TX
x20
TX
x20
RX
x20
RX
SlimSAS x2UPI/PCle EP/RP
UPI_1RX
UPI_2TX
UPI_2RX
SlimSAS x2UPI/PCle EP/RP
X72
X72
X72 QSPI2Gb Flash
USBPHY USB
JTAG HDR
CurrentSense
JTAGJTAG
AVST x8QSPI x4
Config
GPIO
TempSense
PWR inCTRL
Aux_212V
VoltageRegulators &
Discharge CKT
NIOSFLASH
Clock
I2C
Pwr Seq CTRL
I2C
Current Sense Inputs
Temp Diodes
All Clocks
+12V
+12V from PCleGold Finger
Voltage SenseInputs
AllVoltages
IntelMAX 10SystemControl
DDR4512Mx16 X5
DDR4_CH1
DDR4512Mx16 X5
DDR4_CH0
X72
2K
2L
2M
2N
2J
2I
3I
3D
E-Tile9A
3C
3B
3A
2A
RX
AVSTx8
TX
x16 x16RX TX
x20 x20
2B
2C
2F
3J
3K
3L
3H
P-Tile11B
P-Tile11C
P-Tile10A
P-Tile10B
UPI_0RX
UPI/PCIe EP/RP SlimSAS x2
UPI_0TX
Intel Stratix 10 DX FPGA Development Kit
DIMM_CH0 DDR4/DDR-T
DIMM_CH1 DDR4/DDR-T
PCIe Gen4 X16 Edge Conn
SDM
UG-20255 | 2019.12.09
Send Feedback
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
2.1. Supported Features
Table 3. Supported Features
Category Features
Intel Stratix 10 DX FPGA• 0.85-0.89V/VID-adjustable VCC core, 2912 pin BGA package• P-Tile transceivers supporting PCIe Gen4 or UPI• E-Tile transceivers supporting 28Gbps NRZ and 56Gbps PAM4
FPGA configuration
• Partial reconfiguration support• CVP configuration support• 2Gb QSPI Flash• Storage for one configuration image in flash• JTAG header for device programming• Built-in Intel FPGA Download Cable for device programming
Programmable clock sources
• 312.53125 Mhz and 156.25 MHz Differential LVDS for QSFP• 100 Mhz Differential LVDS for PCIe• 133 Mhz Differential LVDS for Memory• 125 Mhz Configuration clock• 100 Mhz Differential LVDS for IO banks
Transceiver interfaces
• PCIe x16 interface supporting Gen4 End-Point mode connected to a x16 PCIe edgeconnector (gold edge fingers)
• 2x standard QSFP56 optical module interfaces connected to the E-tile transceivers• 3x UPI or PCIe interface supporting UPI x20 at 11.2Gbps or PCIe x16 at 16Gbps via
SlimSAS connectors (cables shipped separately)
Memory interfaces
• Two on-board independent single rank DDR4 x72 (ECC) channels operating at 1200 MHz(DDR4-2400)
• Two DIMM sockets supporting DDR4 DIMM or Intel’s Optane DC Persistent memorymodule
Communication ports
• 2xQSFP28 optical interface port• JTAG header• USB (Micro USB) on-board Intel FPGA Download Cable II• System I2C header
Buttons, Switches, and LEDs
• System Reset Push button• CPU Reset Push button• PCIe Reset Push button• Four dedicated User LEDs• Link LED of each QSFP28 port to indicate the link and data transceiver• Two dedicated configuration status LEDs
Heatsink and Fan• Air-cooled heatsink assembly• Red Over-Temperature Warning LED Indicator
Power
• PCIe input power including required 2x4 AUX power connector• Blue Power-On LED• On/Off Slide Power Switch for benchtop operation• On board power and temperature measurement circuitry
Mechanical• PCIe standard height form factor• 4.376” x 10.0” board size• 2 Slots height with heatsink
2.2. Recommended Operating Conditions
Follow these operating range or limit for different physical parameters:
2. Development Kit Overview
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
7
• Ambient operating temperature range: 0°C to 35°C
• Maximum ICC load current: 192 A
• Maximum ICC load transient percentage: 30%
• FPGA maximum power supported by the supplied heatsink/fan: 192 W
2.3. Handling the Board
When handling the board, it is important to observe static discharge precautions.
Caution: Without proper anti-static handling, the board can be damaged. Therefore, use anti-static handling precautions when touching the board.
Important: This development kit should not be operated in a vibrating environment.
2. Development Kit Overview
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
8
3. Power Up the Development KitThe Intel Stratix 10 DX FPGA development kit is designed to operate in two modes:
• As a PCIe* add-in card
• Bench-top mode
When operating the card as a PCIe system, insert the card into an available PCIe slotand connect a 2x4 pin PCIe power cable from the system to power connectors at J42of the board.
Note: When operating as a PCIe add-in card, the board does not power on unless power issupplied to J42.
In Bench-top mode, you must supply the board with 240 W of power supply connectedto the power connector J42.
This development kit ships with its switches preconfigured to support the designexamples in the kit. If you suspect that your board may not be correctly configuredwith the default settings, refer to the Default Switch and Jumper Settings section ofthis chapter.
Follow these instructions:
1. Connect the supplied power supply to an outlet and the DC Power Jack (J42) onthe FPGA board.
Note: Use only the supplied power supply. Power regulation circuits on the boardcan be damaged by power supplies with greater voltage.
2. Set the power switch (SW31) to the ON position.
When the board powers up, the blue LED illuminates and the board is ready for use.The Orange LED (D56) should also illuminate indicating that all the power rails on theboard are good. If the POWER GOOD LED (D56) is not illuminated, it indicates that thepower supply is malfunctioned and the board will not power up.
Note: The standby powers are always present as soon as the AUX power is applied to J42.Use power switch SW31 to start the board.
3.1. Default Switch Settings
This development kit ships with its switches preconfigured to support the designexamples in the kit. If you suspect that your board may not be correctly configuredwith the default settings, refer to the following table to return to its factory settingsbefore proceeding.
UG-20255 | 2019.12.09
Send Feedback
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
Table 4. Default Switch Settings
Switch Default Position Description
SW1[1:4] ON/OFF/OFF/X
Configuration mode setting bits:
Mode MSEL0 MSEL1 MSEL2 QSPI_AVST_SEL
JTAG OFF OFF OFF X
Avalon-ST ON OFF OFF X
SW33[1:4] OFF/X/ON/ON
JTAG, MAX10, UPI controls:
SW33 ON OFF
1 - JTAG Debug JTAG Header (J2)dedicated for Max10 Normal JTAG (Default)
2 - JTAG SOURCE Not used Not used
3 - UPI Mode 2 Sockets 4 Sockets
4 – M10 JTAG EN M10 JTAG Enabled M10 JTAG Disabled
SW2[1:4] ON/ON/ON/ON
PCIe PRSNT X1/x4/x8/x16 settings:
PCIe PRSNT X1 PCIe PRSNT X4 PCIe PRSNT X8 PCIe PRSNTX16
ON ON ON ON
SW28 ONPCIe Edge connector PERSTn selection:• ON: Endpoint (Default)• OFF: Root Port
SW27 ONIntel Stratix 10 DX PERSTn selection:• ON: Endpoint (Default)• OFF: Root Port
SW16 ONUPI0 PERSTn selection - UPI0 connector side:• ON: PERSTn from PCIe Edge connector to FPGA• OFF: PERSTn from FPFA to CPU (Default)
SW24 ONUPI0 PERSTn selection - FPGA side:• ON: PERSTn from FPGA to CPU (Default)• OFF: PERSTn from PCIe Edge connector to FPGA
SW17 ONUPI1 PERSTn selection - UPI1 connector side:• ON: PERSTn from PCIe Edge connector to FPGA• OFF: PERSTn from FPFA to CPU (Default)
SW25 ONUPI1 PERSTn selection - FPGA side:• ON: PERSTn from FPGA to CPU (Default)• OFF: PERSTn from PCIe Edge connector to FPGA
SW18 ONUPI2 PERSTn selection - UPI2 connector side:• ON: PERSTn from PCIe Edge connector to FPGA• OFF: PERSTn from FPFA to CPU (Default)
SW26 ON UPI2 PERSTn selection - FPGA side:
continued...
3. Power Up the Development Kit
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
10
Switch Default Position Description
• ON: PERSTn from FPGA to CPU (Default)• OFF: PERSTn from PCIe Edge connector to FPGA
SW14 OFFPCIe REFCLK source selection:• ON: 100MHz REFCLK internal generated• OFF: 100MHz REFCLK from PCIe Edge Connector (Default)
SW31 ON or OFFPower switch:• ON: Turn on power (set to this position for use in PCIe slot)• OFF: Turn off power
Figure 3. Location of Switches and Push Buttons
Table 5. Push Buttons
Push Buttons Descriptions
S1 PCIe Reset Push to reset PCIe bus
S2 MAX10 Reset Push to reset Max10
S3 CPU Reset Push to reset FPGA
S4 USER Push Button Push button for user assigned function
3. Power Up the Development Kit
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
11
3.2. Connectors and LEDs
Figure 4. Location of Connectors and LEDs
Table 6. Connectors
Connector Description
J2 External JTAG connector For use with Intel FPGA Download Cable
J42 AUX Power connector For external 12V AUX power supply or power adapter
J97 I2C/PMBus connector For accessing the core power controller
J17 I2C connector To access I2C bus
J15 QSFP 1 connectorFor using the QSFP interface
J18 QSFP 2 connector
CN1 USB connector For programming FPGA using on-board Intel FPGADownload Cable
J73 DIMM 0 connector For DDR4/DDR-T memory channel 0
J74 DIMM 1 connector For DDR4/DDR-T memory channel 1
J9 PCIe x16 Gold Finger For using the PCIe interface
J38 UPI 1 Transmit For UPI Link 1 connection from FPGA to CPU
J40 UPI 1 Receive For UPI Link 1 connection from CPU to FPGA
J39 UPI 2 Transmit For UPI Link 2 connection from FPGA to CPU
J41 UPI 2 Receive For UPI Link 2 connection from CPU to FPGA
J55 UPI 0 Transmit For UPI Link 0 connection from FPGA to CPU
J65 UPI 0 Receive For UPI Link 0 connection from CPU to FPGA
J24 Fan connector For connecting to the heatsink cooling fan
Table 7. LEDs
LEDs Description
D18 QSFP 1 Link LED for 25G Green LED:
continued...
3. Power Up the Development Kit
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
12
LEDs Description
• ON: link• Blinks: Activities
D20 QSFP 1 Link LED for 10GYellow LED:• ON: link• Blinks: Activities
D22 QSFP 2 Link LED for 25GGreen LED:• ON: link• Blinks: Activities
D21 QSFP 2 Link LED for 10GYellow LED:• ON: link• Blinks: Activities
D9 USER LED 0 Green LED for USER LED 0
D10 USER LED 1 Green LED for USER LED 1
D14 USER LED 2 Green LED for USER LED 2
D15 USER LED 3 Green LED for USER LED 3
D56 POWER GOOD LEDYellow LED:• ON: All power is good• OFF: Power failure
D57 CONFIG DONE LEDGreen LED:• ON: FPGA configuration successful• OFF: FPGA configuration failed
D13 MAX10 CONFIG DONE LEDGreen LED:• ON: MAX10 configuration successful• OFF: MAX10 configuration failed
D40 Over Temp LEDRed LED:• ON:• OFF:
D53 POWER LEDBlue LED:• ON: Devkit power is on• OFF: Devkit power is off
3.3. Performing Board Restore through Board Test System (BTS)
The development kit ships with FPGA design examples stored in the QSPI flash deviceand pre-programmed Intel MAX® 10 system. If you want to restore the board QSPIflash with the default factory image, follow these steps:
1. Connect USB cable between CN1 USB connector and your computer.
2. Open Intel Quartus Prime Pro Edition Programmer.
3. Detect JTAG chain and attach factory default image on system Intel MAX 10device.
4. Select programming options and click Program button.
3. Power Up the Development Kit
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
13
3.4. Controlling On-board Clock
The clock controller application can change the on-board Si53XX programmableoscillators to any customized frequency between 0.2 MHz and 800 MHz.
The clock control application (ClockControl.exe) runs as a stand-alone applicationand resides in the location <package dir>\examples\board_test_system.The clock control application communicates with the system Intel MAX 10 devicethrough either USB port CN1 or 10pin JTAG header J2. The system Intel MAX 10device controls these programmable clock parts through a two-wire serial bus.
3. Power Up the Development Kit
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
14
4. Board Test System (BTS)The Intel Stratix 10 DX FPGA Development Kit includes an application called BoardTest System (BTS) to test the functionality of this board. The BTS provides an easy-to-use Graphical User Interface (GUI) to alter functional settings and observe results. Youcan use the BTS to test board components, modify functional parameters, observeperformance, and measure power usage.
The BTS communicates over the JTAG bus to a test design running in the Intel Stratix10 DX FPGA device. You can use the BTS to reconfigure the FPGA with test designsspecific to the functionality that you are testing.
The BTS is also useful as a reference for designing systems.
Figure 5. BTS GUI Home
UG-20255 | 2019.12.09
Send Feedback
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
Figure 6. About BTS
4.1. Preparing the Development Kit
Several designs are provided to test the major board features. Each design providesdata for one or more tabs in the application. The Configure Menu identifies theappropriate design to download to the FPGA for each tab.
After successful FPGA configuration, an appropriate tab appears that allows you toexercise the related board features. Highlights appear in the board picture around thecorresponding components.
The BTS communicates over the JTAG bus to a test design running in the FPGA. TheBTS and Power Monitor share the JTAG bus with other applications like the Nios® IIdebugger and the Signal Tap II Embedded Logic Analyzer. Because the BTS is designedbased on the Intel Quartus Prime software, be sure to close other applications beforeyou use the BTS.
The BTS relies on the Intel Quartus Prime software's specific library. Before runningthe BTS, open the Intel Quartus Prime software to automatically set the environmentvariable $QUARTUS_ROOTDIR. The BTS uses this environment variable to locate theIntel Quartus Prime library. The version of Intel Quartus Prime software set in theQUARTUS_ROOTDIR environment variable should be newer than version 14.1. Forexample, the Development Kit Installer version 15.1 requires that the Intel QuartusPrime software 14.1 or later version is installed.
Additionaly, to ensure that the FPGA is configured successfully, you should install thelatest Intel Quartus Prime software that can support the silicon on the developmentkit. For this board, Intel recommends installing the Intel Quartus Prime version 19.3b222.
Refer to the README.txt file under \examples\board_test_system directory.
4.2. Running the Board Test System
With the power to the board turned off, follow these steps:
4. Board Test System (BTS)
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
16
1. Connect the USB cable to your PC and the board.
2. Check whether the board switches and jumpers are set according to yourpreferences.
3. Turn on the power to the board.
To ensure operating stability, keep the USB cable connected and the board powered onwhen running the demonstration application. The BTS cannot run correctly unless theUSB cable is attached and the board is powered on.
To run the BTS, navigate to the <package dir>\examples\board_test_systemdirectory and run the BoardTestSystem.exe application. A GUI appears, displayingthe application tab corresponding to the design running in the FPGA. If the designloaded in the FPGA is not supported by the BTS GUI, you will receive a messageprompting you to configure your board with a valid BTS design. Refer to the ConfigureMenu on page 17 for configuring your board.
If some design is running in the FPGA, the BTS GUI loads the design file (.sof) inthe image folder to check the current running design in the FPGA. Therefore, thedesign running in the FPGA must be the same as the design file in the image folder.
4.3. Using the Board Test System
This section describes each tab in the BTS.
4.3.1. Configure Menu
Use the Configure menu to select the design you want to use. Each design exampletests different board features. Select a design from this menu and the correspondingtabs become active for testing.
Figure 7. Configure Menu
To configure the FPGA with a test system design, perform the following steps:
4. Board Test System (BTS)
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
17
1. On the Configure menu, click the configure command that corresponds to thefunctionality you want to test.
2. In the dialog box that appears, click Configure to download the correspondingdesign to the FPGA.
When configuration finishes, close the Intel Quartus Prime software GUI if it's alreadyopen. The design begins running in the FPGA. The corresponding GUI application tabsthat interface with the design are now enabled.
Note: If you use the Intel Quartus Prime Programmer for configuration rather than the BTSGUI, you may need to restart the GUI.
4.3.2. Sys Info Tab
The Sys Info tab shows the board's current configuration. The tab displays thecontents of the Intel MAX 10 registers, the JTAG chain, the Ethernet port numbers,and other details stored on the board.
Figure 8. Sys Info Tab
The following sections describe the controls of the Sys Info tab.
Board Information
Displays static information about your board:
4. Board Test System (BTS)
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
18
• Board Name: Indicates the official name of the board given by the BTS.
• Board P/N: Indicates the part number of the board.
• Serial Number: Indicates the serial number of the board.
• Board Revision: Indicates the revision of the board.
• MAX Version: Indicates the version of Intel MAX 10 code currently running onthe board.
JTAG Chain
Shows devices which are currently in the JTAG chain.
4.3.3. GPIO Tab
The GPIO tab allows you to interact with all the genral purpose user I/O componentson your board. You can turn LEDs on or off.
Figure 9. GPIO Tab
The following sections describe the controls on the GPIO tab:
User LEDs
Displays the current state of user LEDs. Toggle the LED buttons to turn the board LEDson and off.
4. Board Test System (BTS)
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
19
Qsys Memory Map
Shows the memory map of the GPIO or FLASH Platform Designer system on yourboard.
4.3.4. QSFP Tab
This tab allows you to perform loopback tests on the QSFP ports.
Figure 10. QSFP Tab
The following sections describe the controls on the QSFP tab:
Status
Displays the following status information during a loopback test:
4. Board Test System (BTS)
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
20
• PLL Lock: Shows the PLL locked or unlocked state.
• Pattern sync: Shows the pattern synced or not synced state. The pattern isconsidered synced when the start of the data sequence is detected.
• Details: Shows the PLL lock and pattern sync status:
Figure 11. PLL and Pattern Status
Port
Allows you to specify which interface to test. The following port tests are available:
• QSFP x8
PMA Setting
Allows you to make changes to the PMA parameters that affect the active transceiverinterface. The following settings are available for analysis:
• Serial Loopback: Routes signals between the transmitter and the receiver.
• VOD: Specifies the voltage output differential of the transmitter buffer.
• Pre-emphasis tap:
— Pre-tap 1: Specifies the amount of pre-emphasis on the first pre-tap of thetransmitter buffer.
— Pre-tap 2: Specifies the amount of pre-emphasis on the second pre-tap ofthe transmitter buffer.
— Pre-tap 3: Specifies the amount of pre-emphasis on the third pre-tap of thetransmitter buffer.
— Post-tap 1: Specifies the amount of pre-emphasis on the post-tap of thetransmitter buffer.
• Equalizer: Specifies the RX tuning mode for receiver equalizer.
4. Board Test System (BTS)
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
21
Figure 12. PMA Setting
Data Type
Specifies the type of data contained in the transactions. The following data types areavailable for analysis:
• PRBS 7: Selects pseudo-random 7-bit sequences.
• PRBS 15: Selects pseudo-random 15-bit sequences.
• PRBS 23: Selects pseudo-random 23-bit sequences.
• PRBS 31: Selects pseudo-random 31-bit sequences.
• HF: Selects highest frequency divide-by-2 data pattern 10101010.
• LF: Selects lowest frequency divide-by-33 data pattern.
Error Control
Displays data errors detected during analysis and allows you to insert errors:
• Detected errors: Displays the number of data errors detected in the hardware.
• Inserted errors: Displays the number of errors inserted into the transmit datastream.
• Insert: Inserts a one-word error into the transmit data stream each time you clickthe button. Insert is only enabled during transaction performance analysis.
• Clear: Resets the detected errors and inserted errors counters to zero.
4. Board Test System (BTS)
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
22
Loopback
• Start: Initiates the selected ports transaction performance analysis. Always clickClear before Start.
• Stop: Terminates transaction performance analysis.
• TX and RX performance bars: Show the percentage of maximum theoreticaldata rate that the requested transactions are able to achieve.
4.3.5. Component DDR4 CH0 Tab
This tab allows you to read and write Component DDR4 CH0 memory on your board.
Figure 13. Component DDR4 CH0 Tab
The following sections describe the controls on the Component DDR4 CH0 tab:
Start
Initiates DDR4 memory transaction performance analysis.
Stop
Terminates transaction performance analysis.
Performance Indicator
These controls display current transaction performance analysis information collectedsince you last clicked Start:
4. Board Test System (BTS)
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
23
• Write, Read and Total performance bars: Shows the percentage of maximumtheoretical data rate that the requested transactions are able to achieve.
• Write (MBps), Read (MBps) and Total (MBps): Shows the number of bytesanalyzed per second.
• Data Bus: 72-bits (8-bits ECC) wide and the frequency is 1066 MHz double datarate. 2133 Mbps per pin. Equating to a theoretical maximum banwidth of 136,512Mbps or 17,064 MBps.
Error Control
This control displays data errors detected during analysis and allows you to inserterrors:
• Detected errors: Displays the number of data errors detected in the hardware.
• Inserted errors: Displays the number of errors inserted into the transactionstream.
• Insert: Inserts a one-word error into the transaction stream each time you clickthe button. Insert error is only enabled during transaction performance analysis.
• Clear: Resets the detected error and inserted error counters to zero.
Address Range
Determines the number of addresses to use in each iteration of reads and writes.
4.3.6. Component DDR4 CH1 Tab
This tab allows you to read and write Component DDR4 CH1 memory on your board.
4. Board Test System (BTS)
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
24
Figure 14. Component DDR4 CH1 Tab
The following sections describe the controls on the Component DDR4 CH1 tab.
Start
Initiates DDR4 memory transaction performance analysis.
Stop
Terminates transaction performance analysis.
Performance Indicators
These controls display current transaction performance analysis information collectedsince you last clicked Start:
• Write, Read and Total performance bars: Shows the percentage of maximumtheoretical data rate that the requested transactions are able to achieve.
• Write (MBps), Read (MBps) and Total (MBps): Shows the number of bytesanalyzed per second.
• Data Bus: 72-bits (8-bits ECC) wide and the frequency is 1066 MHz double datarate. 2133 Mbps per pin. Equating to a theoretical maximum banwidth of 136,512Mbps or 17,064 MBps.
Error Control
This control displays data errors detected during analysis and allows you to inserterrors:
4. Board Test System (BTS)
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
25
• Detected errors: Displays the number of data errors detected in the hardware.
• Inserted errors: Displays the number of errors inserted into the transactionstream.
• Insert: Inserts a one-word error into the transaction stream each time you clickthe button. Insert error is only enabled during transaction performance analysis.
• Clear: Resets the detected error and inserted error counters to zero.
Address Range
Determines the number of addresses to use in each iteration of reads and writes.
4.3.7. DDR4 DIMM CH0 Tab
This tab allows you to read and write Dual Inline Memory Module (DIMM) DDR4 CH0memory on your board.
Figure 15. DDR4 DIMM CH0 Tab
The following sections describe the controls on the DDR4 DIMM CH0 tab:
Start
Initiates DDR4 memory transaction performance analysis.
Stop
Terminates transaction performance analysis.
4. Board Test System (BTS)
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
26
Performance Indicators
These controls display current transaction performance analysis information collectedsince you last clicked Start:
• Write, Read and Total performance bars: Shows the percentage of maximumtheoretical data rate that the requested transactions are able to achieve.
• Write (MBps), Read (MBps) and Total (MBps): Shows the number of bytesanalyzed per second.
• Data Bus: 72-bits (8-bits ECC) wide and the frequency is 1066 MHz double datarate. 2133 Mbps per pin. Equating to a theoretical maximum banwidth of 136,512Mbps or 17,064 MBps.
Error Control
This control displays data errors detected during analysis and allows you to inserterrors:
• Detected errors: Displays the number of data errors detected in the hardware.
• Inserted errors: Displays the number of errors inserted into the transactionstream.
• Insert: Inserts a one-word error into the transaction stream each time you clickthe button. Insert error is only enabled during transaction performance analysis.
• Clear: Resets the detected error and inserted error counters to zero.
Address Range
Determines the number of addresses to use in each iteration of reads and writes.
4.3.8. DDR4 DIMM CH1 Tab
This tab allows you to read and write Dual Inline Memory Module (DIMM) DDR4 CH1memory on your board.
4. Board Test System (BTS)
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
27
Figure 16. DDR4 DIMM CH1 Tab
The following sections describe the controls on the DDR4 DIMM CH1 tab:
Start
Initiates DDR4 memory transaction performance analysis.
Stop
Terminates transaction performance analysis.
Performance Indicators
These controls display current transaction performance analysis information collectedsince you last clicked Start:
• Write, Read and Total performance bars: Shows the percentage of maximumtheoretical data rate that the requested transactions are able to achieve.
• Write (MBps), Read (MBps) and Total (MBps): Shows the number of bytesanalyzed per second.
• Data Bus: 72-bits (8-bits ECC) wide and the frequency is 1066 MHz double datarate. 2133 Mbps per pin. Equating to a theoretical maximum banwidth of 136,512Mbps or 17,064 MBps.
Error Control
This control displays data errors detected during analysis and allows you to inserterrors:
4. Board Test System (BTS)
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
28
• Detected errors: Displays the number of data errors detected in the hardware.
• Inserted errors: Displays the number of errors inserted into the transactionstream.
• Insert: Inserts a one-word error into the transaction stream each time you clickthe button. Insert error is only enabled during transaction performance analysis.
• Clear: Resets the detected error and inserted error counters to zero.
Address Range
Determines the number of addresses to use in each iteration of reads and writes.
4.3.9. Power Monitor
The Power Monitor measures and reports current power information andcommunicates with the Intel MAX 10 device on the board through the JTAG bus. Apower monitor circuit attached to the Intel MAX 10 device allows you to measure thepower that the Intel Stratix 10 DX FPGA is consuming.
To start the application, click the Power Monitor icon in the BTS. You can also runthe Power Monitor as a stand-alone application. The PowerMonitor.exe resides inthe <package dir>\examples\board_test_system directory.
Note: You cannot run the stand-alone power application and the BTS simultaneously. Also,you cannot run power and clock interface at the same time.
Figure 17. Power Monitor Interface
4. Board Test System (BTS)
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
29
4.3.10. Clock Controller
The Clock Controller application sets the Si5391 programmable oscillators to anyfrequency between 0.16 MHz and 710 MHz.
The Clock Controller application sets the Si5332 programmable oscillators to anyfrequency between 0.1 MHz and 712.5 MHz.
The Clock Control communicates with the Intel MAX 10 on the board through the JTAGbus. The programmable oscillator are connected to the Intel MAX 10 device through a2-wire serial bus.
Figure 18. Clock Controller - Si5391
4. Board Test System (BTS)
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
30
Figure 19. Clock Controller - Si5332
Si5391 tab and Si5332 tab display the same GUI controls for each clock generators.Each tab allows for separate control. The Si5391 is capable of synthesizing fourindependent user-programmable clock frequencies up to 710 MHz.
The controls of the clock controller are described below:
F_vco
Displays the generating signal value of the voltage-controlled oscillator.
Register
Display the current frequencies for each oscillator.
Frequency
Allows you to specify the frequency of the clock in MHz.
Read
Reads the current frequency setting for the oscillator associated with the active tab.
4. Board Test System (BTS)
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
31
Default
Sets the frequency for the oscillator associated with the active tab back to its defaultvalue. This can also be accomplished by power cycling the board.
Set
Sets the programmable oscillator frequency for the selected clock to the value in theCLK0 to CLK3 controls for the Si5391. Frequency changes might take severalmilliseconds to take effect. You might see glitches on the clock during this time. Intelrecommends resetting the FPGA logic after changing frequencies.
Import
Import register map file generated from Silicon Laboratories ClockBuilder Desktop.
4.4. Smart VID Setting
If you are creating your own design and want to generate programming .sof file, youmust add the correct Smart VID Setting into Intel Quartus Prime project for IntelStratix 10 DX FPGA Development Kit to make configuration successfully. Before youadd the following Smart VID setting into the .qsf file, you must change theconfiguration scheme to Avalon® streaming interface x8 for your project. You can alsoextract the Smart VID setting from the Golden Top file.
set_global_assignment -name USE_CONF_DONE SDM_IO16set_global_assignment -name USE_CVP_CONFDONE SDM_IO5set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"set_global_assignment -name USE_PWRMGT_SCL SDM_IO0set_global_assignment -name USE_PWRMGT_SDA SDM_IO12set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ"set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHERset_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 60set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "DIRECT FORMAT"set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 1set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 3set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTSset_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE OFF
4. Board Test System (BTS)
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
32
5. Development Kit Hardware and Configuration
5.1. FPGA Configuration
Prerequisites:
• Install the Intel Quartus Prime Pro Edition and Intel FPGA Download Cable II driveron the host computer.
• Connect the micro-USB cable to the Intel Stratix 10 DX FPGA Development Kit.
• Power-on the board. Ensure that no running application is using the JTAG chain.
Follow these steps to configure the FPGA with your SRAM Object File (.sof) using theIntel Quartus Prime Pro Edition Programmer:
1. Start the Intel Quartus Prime Pro Edition Programmer.
2. Click Auto Detect to display the devices in the JTAG chain.
3. Click Change File and select the path to the desired *.sof file.
4. Turn on the Program or Configure option for the added file.
5. Click Start to download the selected file to the FPGA. The configuration iscompleted successfully when the progress bar reaches 100%.
Using the Intel Quartus Prime Pro Edition Programmer to configure a device on theboard causes other JTAG- based applications such as the Board Test System and thePower Monitor to lose their connection to the board. Restart those applications afterthe configuration is complete.
Note: While using the Intel Quartus Prime Pro Edition software version 19.3, you mayobserve occasional crash. Contact Intel support to access additional patch (0.01) forIntel Quartus Prime Pro Edition Programmer to mitigate this issue.
5.2. Programming the FPGA Over Intel FPGA Download Cable
The figure below shows the high-level conceptual block diagram for programming theIntel Stratix 10 DX FPGA over the embedded Intel FPGA Download Cable or externalIntel FPGA Download Cable.
UG-20255 | 2019.12.09
Send Feedback
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
Figure 20. Programming Concept Block Diagram
USB PHY Intel MAX 10 Intel Stratix 10DX FPGA
USBConnection
JTAGConnection
USB DataJTAG
5.3. Configuration Modes
The Intel Stratix 10 DX FPGA Development Kit supports two configuration modes:
• Avalon Streaming Interface x8 - using the 2Gb QSPI Flash device (U66)
• JTAG - using either the embedded Intel FPGA Download Cable or external IntelFPGA Download Cable.
5.3.1. Avalon Streaming Interface x8 Mode
The SDM block in the Intel Stratix 10 DX FPGA device controls the configurationprocess and interface. The Intel MAX 10 System Controller (U11) interfaces to IntelStratix 10 DX FPGA in Avalon Streaming Interface X8 mode.
For Avalon Streaming Interface x8 mode, the MSEL[2:0] configuration pin strapping(SW1) must be set to [110] (which means SW1.1: ON (Close), SW1.2: OFF (Open),SW1.3: OFF (Open)).
5.3.1.1. Avalon Streaming Interface x8 Configuration Guideline
Ensure the following conditions are met before you proceed:
• The Intel Quartus Prime Programmer and the Intel FPGA Download Cable II driverare installed on the host computer.
• If you are using an external JTAG programmer, ensure the Intel FPGA DownloadCable II is connected to the board through the 10-pin female connector. Verfiythat the Intel FPGA Download Cable II LED for proper connection to the hostcomputer through a micro-USB cable.
• Power to the board is on, and no other applications that use the JTAG chain arerunning.
• The design running in the FPGA does not drive the FM bus.
The avstx8.cof and avstx8.cdf are included in the factory_recovery folder ofinstaller package.
Avalon Streaming Interface x8 Programmer Object File (.pof) Generation
Note: If you already have the Programmer Object File (.pof), you can skip this section.
1. Open avstx8.cof using the text editor.
2. Change the .pof file name and directory based on your local output file name anddirectory, the location is marked as 1 in the figure below.
5. Development Kit Hardware and Configuration
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
34
3. Change the .sof file name and directory based on your local input file name anddirectory, the location is marked as 2 in the figure below.
Figure 21. Step 2 and 3 Illustration
4. Save the change and close the avstx8.cof file.
5. Open the Intel Quartus Prime Pro Edition software 19.3 or later version, and clickon File > Convert Programming Files to launch Convert Programming Filetool.
6. Click on Open Conversion Setup Data to locate the recently saved avstx8.coffile and open it.
5. Development Kit Hardware and Configuration
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
35
Figure 22. Step 6 Illustration
7. Click Generate to generate the .pof file.
QSPI Flash Programming with Avalon Streaming Interface x8 Configuration Testing
1. Open avstx8.cdf using the text editor.
2. Change the .pof file name and directory based on your local output file name anddirectory, the location is marked as 1 in the figure below. Ensure to save the file.
Figure 23. Step 2 Illustration
3. Change switch SW33.1 to OFF (1'b0:far from board edge) position for normalJTAG mode.
4. Plug in the USB dongle to external JTAG header (J2) or plug in the USB cable intomicro USB port (CN1).
5. Plug ATX Power into J42, switch SW31 to turn OFF the Intel Stratix 10 FPGApower.
6. Open the Intel Quartus Prime Pro Edition software 19.3 or later version, and openavstx8.cdf file.
5. Development Kit Hardware and Configuration
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
36
Figure 24. Step 6 Illustration
7. Click on Hardware Setup in the Intel Quartus Prime Programmer to changeHardware frequency to 16 MHz.
Use the following command to change TCK frequency to 16 MHz:
jtagconfig --setparam <cable_number> JtagClock 16M
8. Click on Start to start QSPI Flash programming.
9. After programming is successful, change switch SW31 to power OFF, and unplugthe ATX power from J42 to completely power down the development kit. Changethe MSEL(SW1) to 110 (AVSTx8, SW1.1: ON (Close), SW1.2: OFF (Open),SW1.3: OFF (Open))
Note: If the development kit is installed in the server, you must power off theserver and power it on to completely power cycle the development kit.
10. Plug ATX Power into J42 and change switch SW31 to power ON the developmentkit. Observe whether the D57 is ON (ON means the AVST x8 configuration issuccessful).
5.3.2. JTAG Mode
The JTAG Switch implemented in the Intel MAX 10 System Control (U11) allows theselection of the device(s) to be included in the JTAG chain. It is done by the settings ofthe DIP switch SW33. The embedded Intel FPGA Download Cable (or external IntelFPGA Download Cable) or PCIe JTAG can be selected as the source for programmingthe device(s) on the chain. The embedded Intel FPGA Download Cable is the defaultsetting for this configuration mode.
5. Development Kit Hardware and Configuration
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
37
Figure 25. JTAG Chain
MT25QLO2G2Gb
QSPI FLASHU66
W25Q648MB
NIOS FLASHU41
GPIOsGPIOs
DCII
USB_MAX_ JTAGEXT_UBII_ JTAG
Micro-USB ConnCN1
USB
PD[3:0]U49
Data/Ctrl
QSPI_M10_DATA 0-3
USB_MAX_JTAGSEL
SW33_1
USB_DISABLEn
BMC_JTAG
3.3V 1.8V
JTAG_INPUT SOURCE
1.8V
1.8V
SPI_D0-3
Configuration 1.8V
1.8VS10_1V8_JTAG
SW33_2
PCIE_PRSNT x1,x4, x8, x16 / WAKEn /CLKREQn
0:PCIe BMC1: ON-Board DCII (Default)
USB_MAX_JTAGSEL 0:Normal Mode (Default) 1: External Intel FPGA Download Cable II (DCII)
GPIOs
GPIOs
MAX 10 U11
USB PHYCY7C6801
U26
EXT. JTAG10-Pin Hrd
J2
nCONFIGnSTATUS
INIT_DONECONFIG_DONE
JTAG
Intel Stratix 10 DX
Bank 2J
PCIE EDGE CONNECTOR J9
MAX3378Level ShifterU204, U212
Schmit Trig Buffers
U64, U68
JTAG CONTROL
The on-board Intel FPGA Download Cable is implemented in a Intel MAX 10 device. Amicro-USB connector connecting to a CY7C68013A USB2 PHY provides the data toIntel MAX 10 device. This allows you to configure the FPGA using a USB cable, whichis directly connected to a host PC running Intel Quartus Prime Pro Edition softwarewithout requiring the external Intel FPGA Download Cable.
You can also use the external Intel FPGA Download Cable on J2 to configure the FPGA.
5. Development Kit Hardware and Configuration
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
38
6. Document Revision History for Intel Stratix 10 DX FPGADevelopment Kit User Guide
DocumentVersion
Changes
2019.12.09 Initial release.
UG-20255 | 2019.12.09
Send Feedback
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
A. Development Kit ComponentsThis appendix provides detailed information about the Intel Stratix 10 DX FPGADevelopment Kit components.
Figure 26. Development Kit Front
Figure 27. Development Kit Back
UG-20255 | 2019.12.09
Send Feedback
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
A.1. Components Overview
Table 8. Intel Stratix 10 DX FPGA Development Kit Components
Board Reference Component Description
Featured Devices
U1 Intel Stratix 10 DX FPGA
• Logic elements: 2.8M• DSP blocks: 5760• M20K memory blocks: 11721• Package type: 2912 BGA• Transceiver count: 84
— 4x P-Tile supporting PCIe X16 Gen4 (16 Gb/s) or UPI X20 (1up to 11.2 GT/s)
— 1x E-Tile transceiver supporting 2x 56Gbps PAM4 or 4x25Gbps NRZ
U11 Intel MAX 10• Logic elements: 50K• Package type: 256 FBGA• 1.8V VCCINT
Clock Circuits
X4 Intel MAX 10 Reference ClockThe crystal oscillator provides the reference clock for IntelMAX 10 device:• Out= 125.00 MHz
U7 Programmable Clock GeneratorSi5332A
Default frequencies:• Out0 = 100.00 MHz
• Out1 = 125.00 MHz
• Out2 = 133.333MHz
• Out3 = 133.333MHz
• Out4 = 133.333 MHz
• Out5 = 133.333MHz
• Out6 = 100.00 MHz
• Out7 = 100.00MHz
U9 Programmable Clock GeneratorSi5391A
Default frequencies:• CLK0 = 156.25MHz
• CLK0A = 156.25 MHz
• CLK1 = 312.50 MHz
• CLK2 = 312.50 MHz
• CLK3 = 312.50 MHz
• CLK4 = Not used
• CLK5 = Not used
• CLK6 = 100.00 MHz
• CLK7 = 100.00 MHz
• CLK8 = 100.00 MHz
• CLK9 = 100.00 MHz
• CLK9A = 100.00 MHz
Transceiver Interfaces
J9 PCIe x16 gold fingers PCIe TX/RX x16 interface from FPGA P-tile 10A
J38 PCIe x16 or UPI x20, Link 1 PCIe/UPI Transmit interface from FPGA P-tile 11B
J40 PCIe x16 or UPI x20, Link 1 PCIe/UPI Receive interface from FPGA P-tile 11B
J39 PCIe x16 or UPI x20, Link 2 PCIe/UPI Transmit interface from FPGA P-tile 11C
continued...
A. Development Kit Components
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
41
Board Reference Component Description
J41 PCIe x16 or UPI x20, Link 2 PCIe/UPI Receive interface from FPGA P-tile 11C
J55 PCIe x16 or UPI x20, Link 0 PCIe/UPI Transmit interface from FPGA P-tile 10B
J65 PCIe x16 or UPI x20, Link 0 PCIe/UPI Receive interface from FPGA P-tile 10B
J15 QSFP 1 connector Four TX/RX channels from FPGA Bank 4F
J18 QSFP 2 connector Four TX/RX channels from FPGA Bank 4F
General User Input/Output
D9, D10, D14, D15 User defined LEDs Four green-color user LEDs. Illuminates when driven low
Memory
J73 DDR4 x72 DIMM connector
One X72 memory interface supporting DDR4 (x72) or IntelOptane DC Persistent memory module:• DDR4 memory (x72) 1333 MHz• Intel Optane DC Persistent memory (requires memory
controller IP core)
J74 DDR4 x72 DIMM connector
One X72 memory interface supporting DDR4 (x72) or IntelOptane DC Persistent memory module:• DDR4 memory (x72) 1333 MHz• Intel Optane DC Persistent memory (requires memory
controller IP core)
U142, U143, U144,U145, U146
On-board DDR4 x72 Memoryinterface
This on-board DDR4 x72 memory supports 8 GB at up to 1200MHz
U152, U153, U154,U155, U156
On-board DDR4 x72 Memoryinterface
This on-board DDR4 x72 memory supports 8 GB at up to 1200MHz
U41 NIOS Flash 64K-bit This on-board Flash is for Intel MAX 10
U66 QSPI 2 Gbit NOR Flash This on-board Flash is for image storage for FPGA
Communication Ports
J9 PCI Express x16 edge connector Gold-plated edge fingers for up to x16 signaling in eitherGen1, Gen2, Gen3, or Gen4 mode
J15 QSFP 1 Interface Provides four transceiver channels for a 100G QSFP module
J18 QSFP 2 Interface Provides four transceiver channels for a 100G QSFP module
J97 I2C/PMBus connector For accessing core power controller
J17 I2C connector For cccessing the I2C1 bus
J2 External JTAG Port
This port allows the use of Intel FPGA Download Cable IIdongle to access the JTAG links on the board. Connection tothis port automatically disables the internal Intel FPGADownload Cable II JTAG.
CN1 Micro-USB connector Embedded Intel Intel FPGA Download Cable II JTAG forprogramming the FPGA via USB cable.
Power Supply
J9 PCI Express edge connector Interfaces to a PCI Express root port such as an appropriatePC motherboard for 12V power source
J42 DC input jack Accepts a 12 V DC power supply when powering the boardfrom the provided power brick for lab bench operation.
continued...
A. Development Kit Components
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
42
Board Reference Component Description
When operating from the PCIe slot, this input must also beconnected to the 8-pin Aux PCIe power connector provided bythe PC system along with J42, or else the board will not poweron.
SW31 Power switch Switch to power ON or OFF the board when supplied from theDC input jack
U217 12V Hot Swap Controller Provide protection for AUX power input (J42)
U96 12V Hot Swap Controller Provide protection for PCIe slot power input (J9)
U93 Controlled power FET Perform power bridging function between AUX2 and PCIe slotwhen the board is not used in PCIe system
U101 3.3V Voltage regulator Provides 3.3V to power system
U99 5V Voltage regulator Provides 5V to power system
U104, U105, U106,U107, U108
5-phase VCC Core Voltageregulator Provides power to VCC core of Intel Stratix 10 FPGA
U230 0.9V Voltage regulator Provides power to all power rails in Group 1
U113 1.8V Voltage regulator Provides power to VCCPT and other rails in Group 2
U186 1.8V Voltage regulator Provides power to VCCH and VCCCLK for P-tiles
U184 1.1V Voltage regulator Provides power to VCCH for E-tile
U78 2.5V Voltage regulator Provides power to VCCCLK for E-tile
U76 2.4V Voltage regulator Provides power to VCCFUSEWR_SDM of Intel Stratix 10 FPGA
U188 1.8V Voltage regulator Provides power to VCCIO of Intel Stratix 10 FPGA
U116 1.2V and 2.5V Voltage regulator Provides power to Intel MAX 10 core and other rails
U79 1.8V Voltage regulator Provides power to VCCIO of Intel MAX 10
U163 2.5V Voltage regulator Provides power to DDR4 Channel 0
U164 0.6V Voltage regulator Provides power to DDR4 VTT Channel 0
U159 1.2V Voltage regulator Provides power to DDR4 Channel 0
U165 2.5V Voltage regulator Provides power to DDR4 Channel 1
U166 0.6V Voltage regulator Provides power to DDR4 VTT Channel 1
U157 1.2V Voltage regulator Provides power to DDR4 Channel 1
U192, U193 0.6V Precision voltage reference Provides reference voltage to DDR4 Channel 0 and Channel 1
U136 Controlled power FET Control power to all memory voltage regulators
U51 Power protector Provides power protection to QSFP 1 (J16)
U52 Power protector Provides power protection to QSFP 2 (J18)
A. Development Kit Components
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
43
A.2. Power, Thermal, and Mechanical Considerations
A.2.1. Power Guidelines
This section describes the power supply for Intel Stratix 10 DX FPGA Development Kit.
A laptop-style DC power supply is provided with the development kit. Use only thesupplied power supply. The power supply has an auto-sensing input voltage of100-240 V AC power and will output 12 V DC power at 20 A to the developmentboard. The 12 V DC input power is then stepped down to various power rails used bythe board components.
An on-board multi-channel analog-to-digital converter (ADC) measures both thevoltage and current for several specific board rails. The power utilization is displayedon a graphical user interface (GUI) that can graph power consumption versus time.
The Intel Stratix 10 DX FPGA Development Kit has two modes of operation:
• Standard PCIe compliant system
In this mode, plug the board into an available PCI Express slot and connect thestandard 2x4 power cords available from the PC's ATX power supply to J11 on theboard. The PCIe slot together with the auxiliary PCIe power cords are required topower the entire board. If you do not connect the 2x4 auxiliary power connection,the board does not power on. The power switch SW3 is ignored when the board isused in the PCIe system.
Figure 28. Setup Example
A. Development Kit Components
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
44
• Standalone evaluation board powered by included power supply
In this mode, plug the included power supply into the 2x4 pin connector (J42) andthe AC power cord of the power supply into a power outlet. This power supplyprovides the entire power to the board without the need to obtain power from thePCIe slot. The power switch SW31 controls powering of the board.
Figure 29. Setup Example
A. Development Kit Components
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
45
A.2.1.1. Power Distribution
The power distribution system on the Intel Stratix 10 DX FPGA Development Kit isshown below.
Figure 30. Power Tree Diagram
J4212V_AUX2
12V_AUX2_IN
12VATX 2x4(150W)12.5A
240W PowerAdapter 20A
12V_PCle_Slot
5VO
DDR4_CH11_EN
DDR4_CH00_EN
0V6_DDR4_VREF_CH00_EN
2.9A
0.2A
0v6_DDR4_VREF_CH11_EN
2.5V_DDR4_CH11_EN
2V5_DDR4_CH11
0.08A
U163
EV1320QI0.6V@2A
U164
EN63A01.2V@12A
U159
3.3V_ZQSFP1
HSCMAX16550
U96
LTC4359U93
VCCH_GXP_EN
0.87A
VC??_GXE_EN0.8A
VCCCLK_GXE_EN0.36A
VCCFUSE_EN
3.2A
VCCID_1V?EN
0.7A
iSL68137 + 5XiSL99227
4.5A0.9V@54A
7.8A [email protected]
VCC_EN
IN
OUT 1.8V_IN
2.5V@1A
S10_G2_1.8V_FLT
0.17A
2.7A
4A
0.5A
0p9V
VCC, VCCP
7.6A
0.01A
0.01A
41.79A
0.17A
0.46A
2.45A
19.6A
1.8V@18A
VCCERAM_EN
S10_G2_1.8V
11.3A
3.3V
1A5V
12V_DDRT_DIMM01
3.3V_REG_INST
3.3V_REG_INST
12V_PCIE_IN
LTC4357Ideal Diode
Ctlr
U97
8.3A
518_VCCH_GXP_LOW
M10_3.3V
MAX10_VCCIO_2.5V
MAX10_VCCIO_1.2V
1.2V@1A
1.8V 6A
MAX10_VCCIO_1.8V
S10 (U1) S10_VCCPLL_SDM, S10_VCCADC, S10_VCCA_PLL
S10 (U1) S10_VCCPT, VCCBAT
S10 (U1) VCCCLK_GXP
S10 (U1) VCCH_GXP
S10 (U1) VCC, VCCP
S10 (U1) VCCRTPLL_GXE
S10 (U1) VCCRT_GXE
S10 (U1) VCCRAM
S10 (U1) S10_VCCPLLDIG_SDM
S10 (U1) S10_VCCFUSE_GXP
S10 (U1) VCCS10_VCCFUSE_GXP
S10_(U1) VCCPFUSEWR_SDM
1.8V
S10 (U1)S10_VCCIO_SDM, S10_VCCBAT, S10_VCCOO_2I, S10_VCCOO_2J,S10_VCCIO_2N, S10_VCCIO_3L, S10_VCCIO_3H
2v5_DDR4_CH11
0V6_DDR4_VTT_CH11
S10_IV2OUT_CH11
0V6_DDR4_VREF_CH11
12V_DORT_DIMM00
[email protected] [email protected]
3.3V_REG
3.3V_REG_EN
U13610.2A
0.6V@1A
1.2V@8A
2V5_DDR4_CH00
0.6V@1A
1.2V@?A
U203
TPS2557 (U51) QSFP1 (116)
QSFP2 (1??)TPS2557 (U52)
U79
S10 (U1) VCCH_GXE
S10 (U1) VCCCLK_GXE
S10_VCCCLK_GXE_LOW 2.5V
Power on
Group 1
Power-up Sequence
Power-down Sequence
Monitored Power Rails
Group 2
Group 3
Group 3
Group 2
Group 1
VCC/VCCP
VCCPT (U113)
0.9V (U230)
3.3V (U101)
12V_AUX2
12V_PCIE_IN
..........
..........
..........
..........
..........
..........
..........
..........
..........
LC
U78
EN6382QI1.8V@8A
U188
U76
[email protected]@0.3A
U116
EN63821.1V@8A
U184
EN63A01.8V@12A
U186
MAX10_VCC_1.2V
M10_VCCINT
M10_3.3V
MAX10_VCCID_1.8V
M10_1V2_VCCDPLL
MAX10_VCCA_2.5V
MAX10_VCCA_ADC_2.5V
..........
LC
F
..........
LC
EM22600.9V@60A
U230
EM2130H3.3V@30A
U101
EM2130H1.8V@30A
U113
NCP45560
U165
EV1320QI0.6V@2A
U166
EN63A01.2V@12A
U157
HSCMAX16550
U217
0V6_DDR4_VTT_CH00
S10_IV2OUT_CH00
2v5_DDR4_CH00
0V6_DDR4_VREF_CH00
ER2120QI5.0V@2A
U99SV0
12VPCle Slot
(75W)5.5A
A. Development Kit Components
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
46
Table 9. Power Supply List
Source Name Power NameMaximum
Output Current(A)
Description
iSL68137 (U104) 0.89VVCC
160Core logic power
VCCP Periphery power
EN2260 (U230) 0.9V
S10_VCCERAM
53
Embedded memory and digitaltransceiver power
VCCPLLDIG_SDM Digital PLL power for SDM
S10_VCCFUSE_GXP Fuse power for P-Tile
S10_VCCRT_GXP Analog power for high speedcircuits P-Tile
S10_VCCRT_GXE Analog power for high speedcircuits E-Tile
S10_VCCRTPLL_GXE PLL power for E-Tile
EN2130H (U113) 1.8V
S10_VCCPLL_SDM
18
SDM PLL power
S10_VCCADC ADC power
S10_VCCA_PLL Analog power for PLL
S10_VCCPT
S10_VCCBAT
EN63A0 (U186) 1.8VS10_VCCH_GXP
12Analog power for P-Tile
S10_VCCCLK_GXP Clock power for P-Tile
EN63A0 (U184) 1.1V S10_VCCH_GXE 8 Analog power for E-Tile
EP53F8QI (U78) 2.5VS10_VCCCLK_GXE
1.5Clock power for E-Tile
2.5V 2.5V for others on board
EP53F8QI (U76) 2.4V S10_VCCFUSEWR_SDM 0.5 Fuse power for SDM
EN6382QII (U188) 1.8V S10_VCCIO 6 Power for IO banks of Intel Stratix10
EZ6303QI (U116) 1.2VM10_VCC_1.2V
1Core power for Intel MAX 10
M10_VCCDPLL PLL power for Intel MAX 10
EZ6303QI (U116) 2.5V M10_VCCA/VCC_ADC 0.2 Power for Intel MAX 10 ADCcircuits
FP53F8QI (U79) 1.8V M10_VCCIO 1 Power for 1.8V IOs of Intel MAX10
EM2130H(U101) 3.3V 3.3V_REG_INST 30 System 3.3V rail
EV1320QI (U164) 0.6V 0p6V_DDR4_VTT_CH00 0.02 Termination power for on-boardDDR4
EP53F8QI (U163) 2.5V 2V5_DDR4_CH00 0.1 2.5V rail for DDR4
EN63A0 (U159) 1.2V S10_1v2OUT_CH00 12 Memory IO power for Ch00
EV1320QI (U166) 0.6V 0p6V_DDR4_VTT_CH11 0.02 Termination power for on-boardDDR4
EP53F8QI (U165) 2.5V 2V5_DDR4_CH11 0.1 2.5V rail for DDR4
continued...
A. Development Kit Components
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
47
Source Name Power NameMaximum
Output Current(A)
Description
EN63A0 (U157) 1.2V S10_1v2OUT_CH11 12 Memory IO power for Ch00
MAX16550 (U217) 12V 12V_AUX2_IN 20 12V rail from AUX Powerconnector
MAX16550 (U96) 12V 12V_PCIe_SLOT 5.5 12V rail from PCIe EdgeConnector
A.2.1.2. Power Sequence
The Intel Stratix 10 DX FPGA device requires proper power up and power downsequences.
Table 10. Power Sequencing Groups
Group 1 Group 2 Group 3
VCCL/VCC (0.89)VCCERAM (0.9)VCCPLLDIG_SDM (0.9)VCCRT_GXP (0.9)VCCRT_GXE (0.9)VCCRTPLL_GXE (0.9)VCCFUSE_GXP (0.9)
VCCH_GXE (1.1)VCCH_GXP (1.8)VCCADC (1.8)VCCPLL_SDM (1.8)VCCAPLL (1.8)VCCIO (2.5)VCCIO (1.8)
VCCIO (1.2, 1.25, 1.35, 1.5, 1.8)VCCFUSEWR_SDM (2.4)VCCN_SDM (1.8)VCCIO3 (1.5, 1.8, 2.5, 3.0)
• Required power up sequence: Group 1 > Group 2 > Group 3
• Required power down sequence: Group 3 > Group 2 > Group 1
• I/O pins are tri-stated during power-up or down sequence when the proper powersequence is followed. I/O pins should not be driven externally during this time orexcess I/O pin current can result.
• Power supplies in each group can be ramped up in any order.
• The total power supply ramp-down time must not exceed 100 ms.
• Ramp-up the last power supply of Group 1 to 90% (0.72) before ramping up theGroup 2 supplies. Ramp up the last power supply of Group 2 to 90% (1.62V)before ramping up the Group 3 supplies.
• VCCBAT_SDM can be powered up anytime.
• To use CvP/autonomous hard IP, the total time must be within 10 ms, from thefirst power supply ramp-up to the last power supply ramp-up.
Note: The POR delay time in Intel Stratix 10 DX FPGA is always within 2ms.
• VCCL and VCC should be tied together at customer board.
• VCCPLL_HPS and VCCPLL_SDM should be tied together at customer board.
• VCCPLLDIG_SDM and VCCERAM should be tied together at customer board with a filter.
• VCCADC and VCCA should be tied together at customer board with or without a filter.
• VCCERT, VCCERT_PLL and VCCERAM should be tied together at customer board with orwithout a filter and should ramp up together for better current control.
— Noise mask specifications must be met.
— Use of an LC Filter is proposed to enable sourcing VCCERT, VCCERT_PLL fromVCCERAM.
A. Development Kit Components
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
48
• VCCN_SDM has to stay in Group 3. It cannot be moved to Group 2 or merged withany Group 2 regulator.
• VCCFUSE_GXP is always connected to VCCERAM on customer board. For only internaltesting purposes, VCCFUSE_GXP is connected to VCCR.
• All power rails must ramp up monotonically.
• All power rails must ramp up to full rail in Tramp specified in the Intel Stratix 10Device Datasheet.
• Ensure (VCCIO - VCCPT) is less than 1.92 to avoid damage to the device
• Hot socket is not supported in Intel Stratix 10 DX FPGA.
Figure 31. Power Sequence Flow Diagram
12V_PCIE_IN AUX2_HSC_MAX10_PGPCIE_HSC_MAX10_PG
3.3V_REG_INST_PG
VCC_ENVCCERAM_EN
1.8V_ENVCCH_GXP_ENVCCH_GXE_ENVCCCLK_GXE_EN3.3_REG_EN
VCCFUSE_ENVCCIO_1V8_EN2.5V_DDR4_CH00_EN0V6_DDR4_VREF_CH00_ENDDR4_CHH00_EN2.5V_DDR4_CH11_EN0V6_DDR4_VREF_CH11_ENDDR4_CH11_EN
Group1_PG
Group2_PG
12V_AUX2_IN
AUX2_HSC_MAX10_PG
PCIE_HSC_MAX10_PG
MAX10_PG_ON
3.3V_REG_INST_PG
VCC_PG
VCCERAM_PG
1.8V_PGVCCH_GXP_PG
VCCH_GXE_PG
Group3_Power
Group2_Power
Group1_Power
POWER SEQUENCE
12V_PCIe Slot12V_AUX2
5V03.3V_REG_INST
MAX10_1.8VVCCIO_1.8V (1.8V)
MAX10_VCCIO_2.5VMAX10_VCC_1.2V
M10_3.3V
S10_VCCVCCERAM
VCCRT_GXP, VCCRT_GXES10_VCCPLLDIG_SDM
VCCRTPLL_GXE
S10_VCCPT, VCCBATS10_VCCPLL_SDM
S10_VCCA_PLLS10_VCCADC
S10_VCCH_GXPS10_VCCCLK_GXP
S10_VCCH_GXES10_VCCCLK_GXE
2.5V3.3 REG
S10_VCCIO_SDM1.8V
2V5_DDR4_CH00/CH01S10_1V2OUT_CH00/CH01
0V6_DDR4_VTT_CH00/CH010V6_DDR4_VREF_CH00/CH01
3.3V_ZQSFP1/2
A.2.1.3. Power Measurement
Power measurements are provided for six FPGA power rails by using an ADC andsense resistors. The sense resistors are connected in series to the power regulatoroutput. The I2C interface of the ADC or the regulators are used to sense the voltages.The I2C are connected to the Intel MAX 10 device for reading the voltage. The current
A. Development Kit Components
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
49
(A) reading is achieved by a PAC1931 (U233) reading the voltage drop across thesense resistor and software converts the voltage readings to current for eachmeasured rail. The following power rails are monitored:
• VCC, VCCP (Power sensing by I2C on iLS68137
• 0.9V (Power sensing by I2C on EN2260, U230)
• 1.8V (Power sensing by I2C on EN2310, U113)
• 3.3V (Power sensing by I2C on EN2310, U101)
• VCCRT_GXE (Sense resistor R6685, monitoring via PAC1931, U233)
• VCCRT_GXP (Sense resistor R6688, monitoring via PAC1931, U233)
• 12V PCIe slot (Power sensing by I2C on MAX16550, U217)
• 12V AUX2 (Power sensing by I2C on MAX16550, U96)
A.2.2. Thermal Requirements
The thermal solution is an active cooling system designed to cool up to 250W totalpower of the board. The heatsink is designed to meet the height constraints of a 2-slotPCIe card form-factor as defined by the PCIe CEM specification revision 3.0.
The heatsink is securely mounted to the board using screws for easy assembly andremoval. The thermal material used between FPGA and heatsink also ensures goodthermal contact.
Figure 32. Air-cooled Heatsink Setup
A.2.2.1. Operating Conditions
The Intel Stratix 10 DX FPGA Development Kit is designed to operate within thefollowing conditions while keeping the FPGA die temperature within its recommendedoperating Tj as defined in the Intel Stratix 10 DX FPGA data sheet (usually 100°C):
• Maximum power dissipation — 250 W
• Maximum ambient temperature — 0°C - 35°C
• FPGA Junction Temperature — 85°C
A. Development Kit Components
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
50
A.2.2.2. Temperature Monitoring
A temperature sensing device (MAX6581) monitors the temperature of the IntelStratix 10 DX FPGA device. The Intel Stratix 10 DX FPGA device has seven dietemperature diodes. The MAX6581 device senses these diodes and convert the signalsto a digital form for the Intel MAX 10 device that can be read via a I2C bus.
Additionally, the OVERTEMPn and ALERTn signals from the MAX6581 allow Intel MAX10 device to immediately sense a temperature fault condition. The Intel MAX 10device controls the over temperature warning LED (D40, red-colored) to indicate anover temperature fault condition. Temperature fault set points can be programmedinto the MAX6581 device.
Figure 33. MAX6581 Temperature Sensor Circuit
20 S10_TEMPDIODE0_P20 S10_TEMPDIODE0_N20 S10_TEMPDIODE1_P20 S10_TEMPDIODE1_N20 S10_TEMPDIODE2_P20 S10_TEMPDIODE2_N20 S10_TEMPDIODE4_P20 S10_TEMPDIODE4_N20 S10_TEMPDIODE5_P20 S10_TEMPDIODE5_N20 S10_TEMPDIODE6_P20 S10_TEMPDIODE6_N
17 DIODEH17 DIODEL
7,23 I2C3_SCL I2C3_SCLI2C3_SDA
7,23 I2C3_SDAMAX6581
DXP1DXN1DXP2DXN2DXP3DXN3DXP4DXN4DXP5DXN5DXP6DXN6DXP7DXN7
SMBCLKSMBDATA
EP
STBY
I.C.VCC
NC1NC2
GND
I2C ADDR = 9A
ALERTOVERT 16
186
3.3V_REG_INST
OVERTEMPnTSENSE_ALERTn
22
1715
2521
14 R729 10.0K
C3960.1uF
OVERTEMPn RESn_LED_FAN R321 69.8
3.3V_REG_INST
RED_LEDD40
U32
2324
12345789
11101312
1920
OVERTEMPn 23TSENSE_ALERTn 23, 68
R667
3R6
672
10.0K
10.0K
3.3V_REG_INST
100pf
C3219 100pf
100pf
C709 100pf
C395 100pf100pfC711
100pfC710
C3217
C3218
A.2.3. Mechanical Requirements
The Intel Stratix 10 DX FPGA Development Kit has a PCIe standard-height (4.376 intall), 10.8” long, dual-slot (1.37 in high above the top surface of the PCB) form factoras defined by the PCIe CEM specification Revision 3.0. Additionally, this developmentkit includes the feature for retaining a high-mass card in the PCIe slot.
A. Development Kit Components
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
51
Figure 34. Sectional Profile
Figure 35. Top and Side Profile
A. Development Kit Components
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
52
A.3. Clock Circuits
All clocks are supplied by two on-board low-jitter programmable clock generatorcircuits. The following figure depicts the clock connection to the Intel Stratix 10 DXFPGA:
Figure 36. Clock Connection
E-Tile9A
P-Tile11B
P-Tile11C
3A
SDM
3B
3C
3D
2A
2B
2C
2F
P-Tile10A
P-Tile10B
2N
2M
2L
2K
2I
2J
3H
3K
3J
3I
3L
156.2
5 MHz
156.2
5 MHz
312.5
0 MHz
312.5
0 MHz
312.5
0 MHz
100 M
Hz
100 M
Hz
100 M
Hz
100 M
Hz
100 M
Hz
100 M
Hz
100 M
Hz
100 M
Hz
133.33 MHz
133.33 MHz
133.33 MHz
125 MHz
Intel Stratix 10 DXFPGA
133.33 MHz
100 MHz
100 MHz
100 MHz
100 MHz100 MHz
Table 11. On-board Oscillators
Signal Name Frequency(MHz) I/O Standard Application
Source: U7 (Si5332A)
CLK_100M_FPGA_3H_P100
LVDS FPGA Fabric ClockBank 3HCLK_100M_FPGA_3H_N LVDS
CLK_125M_LVC1_CONFIG 125 LVCMOS FPGA Config Clock
CLK_133M_DDR4_0_P133.33
LVDS FPGA Fabric ClockBank 3JCLK_133M_DDR4_0_N LVDS
continued...
A. Development Kit Components
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
53
Signal Name Frequency(MHz) I/O Standard Application
CLK_133M_DDR4_1_P133.33
LVDS FPGA Fabric ClockBank 2LCLK_133M_DDR4_1_N LVDS
CLK_133M_DIMM_1_P133.33
LVDS FPGA Fabric ClockBank 3BCLK_133M_DIMM_1_N LVDS
CLK_133M_DIMM_0_P133.33
LVDS FPGA Fabric ClockBank 2CCLK_133M_DIMM_0_N LVDS
CLK_100M_FPGA_3L_0_P100
LVDS FPGA Fabric ClockBank 3LCLK_100M_FPGA_3L_0_N LVDS
CLK_100M_TEST_P100
HCSLClock for bench test
CLK_100M_TEST_N HCSL
Source: U9 (Si5391A)
CLk_156M.25M_QSFP1_P156.25
LVPECLReference Clock for Transceivers 9A
CLk_156M.25M_QSFP1_N LVPECL
CLk_156M.25M_QSFP0_P156.25
LVPECLReference Clock for Transceivers 9A
CLk_156.25M_QSFP0_N LVPECL
CLk_312M.50M_QSFP0_P312.50
LVPECLReference Clock for Transceivers 9A
CLk_312M.50M_QSFP0_N LVPECL
CLk_312M.50M_QSFP1_P312.50
LVPECLReference Clock for Transceivers 9A
CLk_312M.50M_QSFP1_N LVPECL
CLk_312M.50M_QSFP2_P312.50
LVPECLReference Clock for Transceivers 9A
CLk_312M.50M_QSFP2_N LVPECL
CLK_100M_FPGA_2I_P100
LVDS FPGA Fabric ClockBank 2ICLK_100M_FPGA_2I_N LVDS
CLK_100M_FPGA_2J_1_P100
LVDS FPGA Fabric ClockBank 2JCLK_100M_FPGA_2J_1_N LVDS
CLK_100M_FPGA_2J_0_P100
LVDS FPGA Fabric ClockBank 2JCLK_100M_FPGA_2J_0_N LVDS
CLK_100M_Si5391_P100
LVDS Clock to U7Input 2CLK_100M_Si5391_N LVDS
The default clock frequencies are as listed in the table. All the clock frequencies can bechanged by using the Clock GUI.
A. Development Kit Components
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
54
A.4. Memory Interface
The Intel Stratix 10 DX FPGA device supports four independent memory interfaces:
• Two independent on-board DDR4
• Two DIMM sockets for DDR4 or Intel Optane DC Persistent memory modules
Figure 37. Memory Interface
3A
2A
8 GB
8 GB
x72
Supporting DDR4 or Intel Optane DC Persistent memory modules
MEM COMPONENT CH0
MEM COMPONENT CH1
DIMM CH0
2B
2C
3B
3C
3DIntel Stratix 10 DX
FPGA
2K
2L
2M
2N
3I
3J
3K
DDR416 Gb x5
DDR416 Gb x5
DIMM
x72
x72
DIMM CH1DIMMx72
Supporting DDR4 or Intel Optane DC Persistent memory modules
The on-board DDR4 uses five 16Gb DDR4 single rank devices connecting to bank 2K,2L, 2M for memory component channel 1 and bank 3I, 3J, 3K for memory componentchannel 0. The total memory size of each channel is 8 GB running at 1200 MHz.
A. Development Kit Components
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
55
The 288-pin DIMM socket interfaces to bank 3I, 3J, 3K, 3L for DIMM channel 0 and tobank 2K, 2L, 2M, 2N for DIMM channel 1. This socket accepts DDR4 or Intel OptaneDC Persistent memory module (requires Intel memory controller IP core). It supportsdual rank at frequency 1067 MHz, 16 GB per channel. It also supports single rank atfrequency 1200 MHz, 8 GB per channel.
A.5. PCIe Interface
The Intel Stratix 10 DX FPGA Development Kit supports four PCIe Gen4 x16 interfacesusing the four P-Tile of the Intel Stratix 10 DX FPGA device.
• One P-Tile (10A) supports PCIe x16 connecting to the devkit’s PCIe edgeconnector. This interface supports PCIe x1, x4, x8, and x16 PCIe End point.
• Three P-Tile (11B, 11C, 10B) each connecting to their corresponding SlimSASconnector can be used as UPI (x20) or PCIe x16 interface in Endpoint or Root Portmode.
The PCIe Edge Connector has PCIe Wake signal (pin B11) and PCIe Clockrequest (pin B12) routed to the GPIO of the Intel Stratix 10 FPGA device.
A.6. UPI Interface
The Intel Stratix 10 DX FPGA Development Kit supports three individual UPIinterfaces. The UPI functionality is enabled by a combination of the appropriate P-Tilesettings and UPI protocol IP core available in Intel Quartus Prime Pro Edition software(additional licensing and enablement may apply). Each interface consists of twoSlimSAS connectors, one for transmit signals and one for receive signals. Each UPIinterface provides node ID for the host CPU to identify. Node ID can be set bystrapping resistors on the board.
The Slim SAS connectors also carry SMBus/I2C, clock, GPIO, and PCIe signals.
A. Development Kit Components
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
56
A.7. Transceiver Signals: PCIe and UPI Interface
Figure 38. PCIe X16 End point - PCIe Slot Interface
55 PCIE_EP_TX0_N55 PCIE_EP_TX0_P
55 PCIE_EP_TX7_N55 PCIE_EP_TX7_P
55 PCIE_EP_TX6_N55 PCIE_EP_TX6_P
55 PCIE_EP_TX5_N55 PCIE_EP_TX5_P
55 PCIE_EP_TX4_N55 PCIE_EP_TX4_P
55 PCIE_EP_TX3_N55 PCIE_EP_TX3_P
55 PCIE_EP_TX2_N55 PCIE_EP_TX2_P
55 PCIE_EP_TX1_N55 PCIE_EP_TX1_P
PCIE_EP_RX0_N 55PCIE_EP_RX0_P 55
PCIE_EP_RX7_N 55PCIE_EP_RX7_P 55
PCIE_EP_RX6_N 55PCIE_EP_RX6_P 55
PCIE_EP_RX5_N 55PCIE_EP_RX5_P 55
PCIE_EP_RX4_N 55PCIE_EP_RX4_P 55
PCIE_EP_RX3_N 55PCIE_EP_RX3_P 55
PCIE_EP_RX2_N 55PCIE_EP_RX2_P 55
PCIE_EP_RX1_N 55PCIE_EP_RX1_P 55
GXPL10A_RX_CH0NGXPL10A_RX_CH0PGXPL10A_RX_CH1NGXPL10A_RX_CH1PGXPL10A_RX_CH2NGXPL10A_RX_CH2PGXPL10A_RX_CH3NGXPL10A_RX_CH3PGXPL10A_RX_CH4NGXPL10A_RX_CH4PGXPL10A_RX_CH5NGXPL10A_RX_CH5PGXPL10A_RX_CH6NGXPL10A_RX_CH6PGXPL10A_RX_CH7NGXPL10A_RX_CH7PGXPL10A_RX_CH8NGXPL10A_RX_CH8PGXPL10A_RX_CH9NGXPL10A_RX_CH9PGXPL10A_RX_CH10NGXPL10A_RX_CH10PGXPL10A_RX_CH11NGXPL10A_RX_CH11PGXPL10A_RX_CH12NGXPL10A_RX_CH12PGXPL10A_RX_CH13NGXPL10A_RX_CH13PGXPL10A_RX_CH14NGXPL10A_RX_CH14PGXPL10A_RX_CH15NGXPL10A_RX_CH15P
GXPL10A_TX_CH0NGXPL10A_TX_CH0PGXPL10A_TX_CH1NGXPL10A_TX_CH1PGXPL10A_TX_CH2NGXPL10A_TX_CH2PGXPL10A_TX_CH3NGXPL10A_TX_CH3PGXER9A_TX_CH4NGXER9A_TX_CH4PGXER9A_TX_CH5NGXER9A_TX_CH5PGXER9A_TX_CH6NGXER9A_TX_CH6PGXER9A_TX_CH7NGXER9A_TX_CH7P
GXPL10A_TX_CH8NGXPL10A_TX_CH8PGXPL10A_TX_CH9NGXPL10A_TX_CH9P
GXPL10A_TX_CH10NGXPL10A_TX_CH10PGXPL10A_TX_CH11NGXPL10A_TX_CH11PGXER9A_TX_CH12NGXER9A_TX_CH12PGXER9A_TX_CH13NGXER9A_TX_CH13PGXER9A_TX_CH14NGXER9A_TX_CH14PGXER9A_TX_CH15NGXER9A_TX_CH15P
BJ51BJ52
BH53BH54
BG51BG52
BF53BF54
BE51BE52
BD53BD54
BC51BC52
BB53BB54
BJ47BJ48
BH49BH50
BG47BG48
BF49BF50
BE47BE48
BD49BD50
BC47BC48
BB49BB50
55 PCIE_EP_TX14_N55 PCIE_EP_TX14_P
55 PCIE_EP_TX13_N55 PCIE_EP_TX13_P
55 PCIE_EP_TX12_N55 PCIE_EP_TX12_P
55 PCIE_EP_TX11_N55 PCIE_EP_TX11_P
55 PCIE_EP_TX10_N55 PCIE_EP_TX10_P
55 PCIE_EP_TX9_N55 PCIE_EP_TX9_P
55 PCIE_EP_TX8_N55 PCIE_EP_TX8_P
BA51BA52
AY53AY54
AW51AW52
AV53AV54
AU51AU52
AT53AT54
AR51AR52
55 PCIE_EP_TX15_N55 PCIE_EP_TX15_P
AP53AP54
PCIE_EP_RX13_N 55PCIE_EP_RX13_P 55
PCIE_EP_RX12_N 55PCIE_EP_RX12_P 55
PCIE_EP_RX11_N 55PCIE_EP_RX11_P 55
PCIE_EP_RX10_N 55PCIE_EP_RX10_P 55
PCIE_EP_RX9_N 55PCIE_EP_RX9_P 55
PCIE_EP_RX8_N 55PCIE_EP_RX8_P 55
BA47BA48
AY49AY50
AW47AW48
AV49AV50
AU47AU48
AT49AT50
PCIE_EP_RX15_N 55PCIE_EP_RX15_P 55
PCIE_EP_RX14_N 55PCIE_EP_RX14_P 55
AR47AR48
AP49AP50
XCVR BANK 10A
17 PCIE_EP_85332_REFCLK0_N17 PCIE_EP_85332_REFCLK0_P17 PCIE_EP_85332_REFCLK1_N17 PCIE_EP_85332_REFCLK1_P
U10_P_IO_RE8REF_0REFCLK_GXPL10A_CH0NREFCLK_GXPL10A_CH0PREFCLK_GXPL10A_CH2NREFCLK_GXPL10A_CH2P
AN41PCIE_EP_IO_RE8REFAT44
R214
R215
AT45
AP44AP45
DNI
DNI
A. Development Kit Components
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
57
Figure 39. UPI 0 Link or PCIe Interface
29 PCIE2_UP12_FPGA_RX0_N29 PCIE2_UP12_FPGA_RX0_P
29 PCIE2_UP12_FPGA_RX8_N29 PCIE2_UP12_FPGA_RX8_P29 PCIE2_UP12_FPGA_RX9_N29 PCIE2_UP12_FPGA_RX9_P29 PCIE2_UP12_FPGA_RX10_N29 PCIE2_UP12_FPGA_RX10_P29 PCIE2_UP12_FPGA_RX11_N29 PCIE2_UP12_FPGA_RX11_P
29 PCIE2_UP12_FPGA_RX12_N29 PCIE2_UP12_FPGA_RX12_P29 PCIE2_UP12_FPGA_RX13_N29 PCIE2_UP12_FPGA_RX13_P
29 PCIE2_UP12_FPGA_RX14_N29 PCIE2_UP12_FPGA_RX14_P29 PCIE2_UP12_FPGA_RX15_N29 PCIE2_UP12_FPGA_RX15_P29 PCIE2_UP12_FPGA_RX16_N29 PCIE2_UP12_FPGA_RX16_P29 PCIE2_UP12_FPGA_RX17_N29 PCIE2_UP12_FPGA_RX17_P29 PCIE2_UP12_FPGA_RX18_N29 PCIE2_UP12_FPGA_RX18_P
29 PCIE2_UP12_FPGA_RX19_N29 PCIE2_UP12_FPGA_RX19_P
29 PCIE2_UP12_FPGA_RX7_N29 PCIE2_UP12_FPGA_RX7_P
29 PCIE2_UP12_FPGA_RX6_N29 PCIE2_UP12_FPGA_RX6_P
29 PCIE2_UP12_FPGA_RX5_N29 PCIE2_UP12_FPGA_RX5_P
29 PCIE2_UP12_FPGA_RX4_N29 PCIE2_UP12_FPGA_RX4_P
29 PCIE2_UP12_FPGA_RX3_N29 PCIE2_UP12_FPGA_RX3_P
29 PCIE2_UP12_FPGA_RX2_N29 PCIE2_UP12_FPGA_RX2_P
29 PCIE2_UP12_FPGA_RX1_N29 PCIE2_UP12_FPGA_RX1_P
PCIE2_UP12_FPGA_TX0_N 29PCIE2_UP12_FPGA_TX0_P 29
PCIE2_UP12_FPGA_TX8_N 29PCIE2_UP12_FPGA_TX8_P 29PCIE2_UP12_FPGA_TX9_N 29PCIE2_UP12_FPGA_TX9_P 29PCIE2_UP12_FPGA_TX10_N 29PCIE2_UP12_FPGA_TX10_P 29PCIE2_UP12_FPGA_TX11_N 29PCIE2_UP12_FPGA_TX11_P 29
PCIE2_UP12_FPGA_TX12_N 29PCIE2_UP12_FPGA_TX12_P 29PCIE2_UP12_FPGA_TX13_N 29PCIE2_UP12_FPGA_TX13_P 29
PCIE2_UP12_FPGA_TX14_N 29PCIE2_UP12_FPGA_TX14_P 29PCIE2_UP12_FPGA_TX15_N 29PCIE2_UP12_FPGA_TX15_P 29PCIE2_UP12_FPGA_TX16_N 29PCIE2_UP12_FPGA_TX16_P 29PCIE2_UP12_FPGA_TX17_N 29PCIE2_UP12_FPGA_TX17_P 29PCIE2_UP12_FPGA_TX18_N 29PCIE2_UP12_FPGA_TX18_P 29
PCIE2_UP12_FPGA_TX19_N 29PCIE2_UP12_FPGA_TX19_P 29
PCIE2_UP12_FPGA_TX7_N 29PCIE2_UP12_FPGA_TX7_P 29
PCIE2_UP12_FPGA_TX6_N 29PCIE2_UP12_FPGA_TX6_P 29
PCIE2_UP12_FPGA_TX5_N 29PCIE2_UP12_FPGA_TX5_P 29
PCIE2_UP12_FPGA_TX4_N 29PCIE2_UP12_FPGA_TX4_P 29
PCIE2_UP12_FPGA_TX3_N 29PCIE2_UP12_FPGA_TX3_P 29
PCIE2_UP12_FPGA_TX2_N 29PCIE2_UP12_FPGA_TX2_P 29
PCIE2_UP12_FPGA_TX1_N 29PCIE2_UP12_FPGA_TX1_P 29
GXPL 10B_RX_CH0NGXPL 10B_RX_CH0PGXPL 10B_RX_CH1NGXPL 10B_RX_CH1PGXPL 10B_RX_CH2NGXPL 10B_RX_CH2PGXPL 10B_RX_CH3NGXPL 10B_RX_CH3PGXPL 10B_RX_CH4NGXPL 10B_RX_CH4PGXPL 10B_RX_CH5NGXPL 10B_RX_CH5PGXPL 10B_RX_CH6NGXPL 10B_RX_CH6PGXPL 10B_RX_CH7NGXPL 10B_RX_CH7PGXPL 10B_RX_CH8NGXPL 10B_RX_CH8PGXPL 10B_RX_CH9NGXPL 10B_RX_CH9PGXPL 10B_RX_CH10NGXPL 10B_RX_CH10PGXPL 10B_RX_CH11NGXPL 10B_RX_CH11PGXPL 10B_RX_CH12NGXPL 10B_RX_CH12PGXPL 10B_RX_CH13NGXPL 10B_RX_CH13PGXPL 10B_RX_CH14NGXPL 10B_RX_CH14PGXPL 10B_RX_CH15NGXPL 10B_RX_CH15PGXPL 10B_RX_CH16NGXPL 10B_RX_CH16PGXPL 10B_RX_CH17NGXPL 10B_RX_CH17PGXPL 10B_RX_CH18NGXPL 10B_RX_CH18PGXPL 10B_RX_CH19NGXPL 10B_RX_CH19P
GXPL 10B_TX_CH0NGXPL 10B_TX_CH0PGXPL 10B_TX_CH1NGXPL 10B_TX_CH1PGXPL 10B_TX_CH2NGXPL 10B_TX_CH2PGXPL 10B_TX_CH3NGXPL 10B_TX_CH3PGXPL 10B_TX_CH4NGXPL 10B_TX_CH4PGXPL 10B_TX_CH5NGXPL 10B_TX_CH5PGXPL 10B_TX_CH6NGXPL 10B_TX_CH6PGXPL 10B_TX_CH7NGXPL 10B_TX_CH7PGXPL 10B_TX_CH8NGXPL 10B_TX_CH8PGXPL 10B_TX_CH9NGXPL 10B_TX_CH9P
GXPL 10B_TX_CH10NGXPL 10B_TX_CH10PGXPL 10B_TX_CH11NGXPL 10B_TX_CH11PGXPL 10B_TX_CH12NGXPL 10B_TX_CH12PGXPL 10B_TX_CH13NGXPL 10B_TX_CH13PGXPL 10B_TX_CH14NGXPL 10B_TX_CH14PGXPL 10B_TX_CH15NGXPL 10B_TX_CH15PGXPL 10B_TX_CH16NGXPL 10B_TX_CH16PGXPL 10B_TX_CH17NGXPL 10B_TX_CH17PGXPL 10B_TX_CH18NGXPL 10B_TX_CH18PGXPL 10B_TX_CH19NGXPL 10B_TX_CH19P
XCVR BANK 10B
AN51AN52
AM53AM54
AL51AL52
AK53AK54
AJ51AJ52
AH53AH54
AG51AG52
AF53AF54
AE51AE52
AD53AD54
AC51AC52
AB53AB54
AA51AA52
Y53Y54
W51W52
V53V54
T53T54
R51R52
P53P54
U51U52
AN47AN48
AM49AM50
AL47AL48
AK49AK50
AJ47AJ48
AH49AH50
AG47AG48
AF49AF50
AE47AE48
AD49AD50
AC47AC48
AB49AB50
AA47AA48
Y49Y50
W47W48
V49V50
T49T50
R47R48
P49P50
U47U48
17 PCIE2_UP12_REFCLK0_N17 PCIE2_UP12_REFCLK0_P17 PCIE2_UP12_REFCLK2_N17 PCIE2_UP12_REFCLK2_P
U11_P_IO_RE8REF_0REFCLK_GXPL 10B_CH0NREFCLK_GXPL 10B_CH0PREFCLK_GXPL 10B_CH2NREFCLK_GXPL 10B_CH2P
AC41PCIE2_UP12_IO_RE8REFAJ44
R216
R217 DNI
AJ45AG44AG45
DNI
A. Development Kit Components
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
58
Figure 40. UPI 1 Link or PCIe Interface
27 PCIE0_UP10_FPGA_RX0_N27 PCIE0_UP10_FPGA_RX0_P
27 PCIE0_UP10_FPGA_RX8_N27 PCIE0_UP10_FPGA_RX8_P27 PCIE0_UP10_FPGA_RX9_N27 PCIE0_UP10_FPGA_RX9_P27 PCIE0_UP10_FPGA_RX10_N27 PCIE0_UP10_FPGA_RX10_P27 PCIE0_UP10_FPGA_RX11_N27 PCIE0_UP10_FPGA_RX11_P
27 PCIE0_UP10_FPGA_RX12_N27 PCIE0_UP10_FPGA_RX12_P27 PCIE0_UP10_FPGA_RX13_N27 PCIE0_UP10_FPGA_RX13_P
27 PCIE0_UP10_FPGA_RX14_N27 PCIE0_UP10_FPGA_RX14_P27 PCIE0_UP10_FPGA_RX15_N27 PCIE0_UP10_FPGA_RX15_P27 PCIE0_UP10_FPGA_RX16_N27 PCIE0_UP10_FPGA_RX16_P27 PCIE0_UP10_FPGA_RX17_N27 PCIE0_UP10_FPGA_RX17_P27 PCIE0_UP10_FPGA_RX18_N27 PCIE0_UP10_FPGA_RX18_P
27 PCIE0_UP10_FPGA_RX19_N27 PCIE0_UP10_FPGA_RX19_P
27 PCIE0_UP10_FPGA_RX7_N27 PCIE0_UP10_FPGA_RX7_P
27 PCIE0_UP10_FPGA_RX6_N27 PCIE0_UP10_FPGA_RX6_P
27 PCIE0_UP10_FPGA_RX5_N27 PCIE0_UP10_FPGA_RX5_P
27 PCIE0_UP10_FPGA_RX4_N27 PCIE0_UP10_FPGA_RX4_P
27 PCIE0_UP10_FPGA_RX3_N27 PCIE0_UP10_FPGA_RX3_P
27 PCIE0_UP10_FPGA_RX2_N27 PCIE0_UP10_FPGA_RX2_P
27 PCIE0_UP10_FPGA_RX1_N27 PCIE0_UP10_FPGA_RX1_P
PCIE0_UP10_FPGA_TX0_N 27PCIE0_UP10_FPGA_TX0_P 27
PCIE0_UP10_FPGA_TX8_N 27PCIE0_UP10_FPGA_TX8_P 27PCIE0_UP10_FPGA_TX9_N 27PCIE0_UP10_FPGA_TX9_P 27PCIE0_UP10_FPGA_TX10_N 27PCIE0_UP10_FPGA_TX10_P 27PCIE0_UP10_FPGA_TX11_N 27PCIE0_UP10_FPGA_TX11_P 27
PCIE0_UP10_FPGA_TX12_N 27PCIE0_UP10_FPGA_TX12_P 27PCIE0_UP10_FPGA_TX13_N 27PCIE0_UP10_FPGA_TX13_P 27
PCIE0_UP10_FPGA_TX14_N 27PCIE0_UP10_FPGA_TX14_P 27PCIE0_UP10_FPGA_TX15_N 27PCIE0_UP10_FPGA_TX15_P 27PCIE0_UP10_FPGA_TX16_N 27PCIE0_UP10_FPGA_TX16_P 27PCIE0_UP10_FPGA_TX17_N 27PCIE0_UP10_FPGA_TX17_P 27PCIE0_UP10_FPGA_TX18_N 27PCIE0_UP10_FPGA_TX18_P 27
PCIE0_UP10_FPGA_TX19_N 27PCIE0_UP10_FPGA_TX19_P 27
PCIE0_UP10_FPGA_TX7_N 27PCIE0_UP10_FPGA_TX7_P 27
PCIE0_UP10_FPGA_TX6_N 27PCIE0_UP10_FPGA_TX6_P 27
PCIE0_UP10_FPGA_TX5_N 27PCIE0_UP10_FPGA_TX5_P 27
PCIE0_UP10_FPGA_TX4_N 27PCIE0_UP10_FPGA_TX4_P 27
PCIE0_UP10_FPGA_TX3_N 27PCIE0_UP10_FPGA_TX3_P 27
PCIE0_UP10_FPGA_TX2_N 27PCIE0_UP10_FPGA_TX2_P 27
PCIE0_UP10_FPGA_TX1_N 27PCIE0_UP10_FPGA_TX1_P 27
GXPR11B_RX_CH0NGXPR11B_RX_CH0PGXPR11B_RX_CH1NGXPR11B_RX_CH1PGXPR11B_RX_CH2NGXPR11B_RX_CH2PGXPR11B_RX_CH3NGXPR11B_RX_CH3PGXPR11B_RX_CH4NGXPR11B_RX_CH4PGXPR11B_RX_CH5NGXPR11B_RX_CH5PGXPR11B_RX_CH6NGXPR11B_RX_CH6PGXPR11B_RX_CH7NGXPR11B_RX_CH7PGXPR11B_RX_CH8NGXPR11B_RX_CH8PGXPR11B_RX_CH9NGXPR11B_RX_CH9PGXPR11B_RX_CH10NGXPR11B_RX_CH10PGXPR11B_RX_CH11NGXPR11B_RX_CH11PGXPR11B_RX_CH12NGXPR11B_RX_CH12PGXPR11B_RX_CH13NGXPR11B_RX_CH13PGXPR11B_RX_CH14NGXPR11B_RX_CH14PGXPR11B_RX_CH15NGXPR11B_RX_CH15PGXPR11B_RX_CH16NGXPR11B_RX_CH16PGXPR11B_RX_CH17NGXPR11B_RX_CH17PGXPR11B_RX_CH18NGXPR11B_RX_CH18PGXPR11B_RX_CH19NGXPR11B_RX_CH19P
GXPR11B_TX_CH0NGXPR11B_TX_CH0PGXPR11B_TX_CH1NGXPR11B_TX_CH1PGXPR11B_TX_CH2NGXPR11B_TX_CH2PGXPR11B_TX_CH3NGXPR11B_TX_CH3PGXPR11B_TX_CH4NGXPR11B_TX_CH4PGXPR11B_TX_CH5NGXPR11B_TX_CH5PGXPR11B_TX_CH6NGXPR11B_TX_CH6PGXPR11B_TX_CH7NGXPR11B_TX_CH7PGXPR11B_TX_CH8NGXPR11B_TX_CH8PGXPR11B_TX_CH9NGXPR11B_TX_CH9P
GXPR11B_TX_CH10NGXPR11B_TX_CH10PGXPR11B_TX_CH11NGXPR11B_TX_CH11PGXPR11B_TX_CH12NGXPR11B_TX_CH12PGXPR11B_TX_CH13NGXPR11B_TX_CH13PGXPR11B_TX_CH14NGXPR11B_TX_CH14PGXPR11B_TX_CH15NGXPR11B_TX_CH15PGXPR11B_TX_CH16NGXPR11B_TX_CH16PGXPR11B_TX_CH17NGXPR11B_TX_CH17PGXPR11B_TX_CH18NGXPR11B_TX_CH18PGXPR11B_TX_CH19NGXPR11B_TX_CH19P
XCVR BANK 11B
BB2BB1
BA4BA3
AY2AY1
AW4AW3
AV2AV1
AU4AU3
AT2AT1
AR4AR3
AP2AP1
AN4AN3
AM2AM1
AL4AL3
AK2AK1
AJ4AJ3
AH2AH1
AG4AG3
AE4AE3
AD2AD1
AC4AC3
AF2AF1
BA8BA7
AY6AY5
AW8AW7
AV6AV5
AU8AU7
AT6AT5
AR8AR7
AP6AP5
AN8AN7
AM6AM5
AL8AL7
AK6AK5
AJ8AJ7
AH6AH5
AG8AG7
AF6AF5
AD6AD5
AC8AC7
AB6AB5
AE8AE7
17 PCIE0_UP10_REFCLK0_N17 PCIE0_UP10_REFCLK0_P17 PCIE0_UP10_REFCLK2_N17 PCIE0_UP10_REFCLK2_P
U21_P_IO_RE8REF_0REFCLK_GXPR11B_CH0NREFCLK_GXPR11B_CH0PREFCLK_GXPR11B_CH2NREFCLK_GXPR11B_CH2P
AL14PCIE0_UP10_IO_RE8REFAH11
R265
R266 DNI
AH10AF11AF10
DNI
A. Development Kit Components
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
59
Figure 41. UPI 2 Link or PCIe Interface
28 PCIE1_UP11_FPGA_RX0_N28 PCIE1_UP11_FPGA_RX0_P
28 PCIE1_UP11_FPGA_RX8_N28 PCIE1_UP11_FPGA_RX8_P28 PCIE1_UP11_FPGA_RX9_N28 PCIE1_UP11_FPGA_RX9_P28 PCIE1_UP11_FPGA_RX10_N28 PCIE1_UP11_FPGA_RX10_P28 PCIE1_UP11_FPGA_RX11_N28 PCIE1_UP11_FPGA_RX11_P
28 PCIE1_UP11_FPGA_RX12_N28 PCIE1_UP11_FPGA_RX12_P28 PCIE1_UP11_FPGA_RX13_N28 PCIE1_UP11_FPGA_RX13_P
28 PCIE1_UP11_FPGA_RX14_N28 PCIE1_UP11_FPGA_RX14_P28 PCIE1_UP11_FPGA_RX15_N28 PCIE1_UP11_FPGA_RX15_P28 PCIE1_UP11_FPGA_RX16_N28 PCIE1_UP11_FPGA_RX16_P28 PCIE1_UP11_FPGA_RX17_N28 PCIE1_UP11_FPGA_RX17_P28 PCIE1_UP11_FPGA_RX18_N28 PCIE1_UP11_FPGA_RX18_P
28 PCIE1_UP11_FPGA_RX19_N28 PCIE1_UP11_FPGA_RX19_P
28 PCIE1_UP11_FPGA_RX7_N28 PCIE1_UP11_FPGA_RX7_P
28 PCIE1_UP11_FPGA_RX6_N28 PCIE1_UP11_FPGA_RX6_P
28 PCIE1_UP11_FPGA_RX5_N28 PCIE1_UP11_FPGA_RX5_P
28 PCIE1_UP11_FPGA_RX4_N28 PCIE1_UP11_FPGA_RX4_P
28 PCIE1_UP11_FPGA_RX3_N28 PCIE1_UP11_FPGA_RX3_P
28 PCIE1_UP11_FPGA_RX2_N28 PCIE1_UP11_FPGA_RX2_P
28 PCIE1_UP11_FPGA_RX1_N28 PCIE1_UP11_FPGA_RX1_P
PCIE1_UP11_FPGA_TX0_N 28PCIE1_UP11_FPGA_TX0_P 28
PCIE1_UP11_FPGA_TX8_N 28PCIE1_UP11_FPGA_TX8_P 28PCIE1_UP11_FPGA_TX9_N 28PCIE1_UP11_FPGA_TX9_P 28PCIE1_UP11_FPGA_TX10_N 28PCIE1_UP11_FPGA_TX10_P 28PCIE1_UP11_FPGA_TX11_N 28PCIE1_UP11_FPGA_TX11_P 28
PCIE1_UP11_FPGA_TX12_N 28PCIE1_UP11_FPGA_TX12_P 28PCIE1_UP11_FPGA_TX13_N 28PCIE1_UP11_FPGA_TX13_P 28
PCIE1_UP11_FPGA_TX14_N 28PCIE1_UP11_FPGA_TX14_P 28PCIE1_UP11_FPGA_TX15_N 28PCIE1_UP11_FPGA_TX15_P 28PCIE1_UP11_FPGA_TX16_N 28PCIE1_UP11_FPGA_TX16_P 28PCIE1_UP11_FPGA_TX17_N 28PCIE1_UP11_FPGA_TX17_P 28PCIE1_UP11_FPGA_TX18_N 28PCIE1_UP11_FPGA_TX18_P 28
PCIE1_UP11_FPGA_TX19_N 28PCIE1_UP11_FPGA_TX19_P 28
PCIE1_UP11_FPGA_TX7_N 28PCIE1_UP11_FPGA_TX7_P 28
PCIE1_UP11_FPGA_TX6_N 28PCIE1_UP11_FPGA_TX6_P 28
PCIE1_UP11_FPGA_TX5_N 28PCIE1_UP11_FPGA_TX5_P 28
PCIE1_UP11_FPGA_TX4_N 28PCIE1_UP11_FPGA_TX4_P 28
PCIE1_UP11_FPGA_TX3_N 28PCIE1_UP11_FPGA_TX3_P 28
PCIE1_UP11_FPGA_TX2_N 28PCIE1_UP11_FPGA_TX2_P 28
PCIE1_UP11_FPGA_TX1_N 28PCIE1_UP11_FPGA_TX1_P 28
GXPR11C_RX_CH0NGXPR11C_RX_CH0PGXPR11C_RX_CH1NGXPR11C_RX_CH1PGXPR11C_RX_CH2NGXPR11C_RX_CH2PGXPR11C_RX_CH3NGXPR11C_RX_CH3PGXPR11C_RX_CH4NGXPR11C_RX_CH4PGXPR11C_RX_CH5NGXPR11C_RX_CH5PGXPR11C_RX_CH6NGXPR11C_RX_CH6PGXPR11C_RX_CH7NGXPR11C_RX_CH7PGXPR11C_RX_CH8NGXPR11C_RX_CH8PGXPR11C_RX_CH9NGXPR11C_RX_CH9PGXPR11C_RX_CH10NGXPR11C_RX_CH10PGXPR11C_RX_CH11NGXPR11C_RX_CH11PGXPR11C_RX_CH12NGXPR11C_RX_CH12PGXPR11C_RX_CH13NGXPR11C_RX_CH13PGXPR11C_RX_CH14NGXPR11C_RX_CH14PGXPR11C_RX_CH15NGXPR11C_RX_CH15PGXPR11C_RX_CH16NGXPR11C_RX_CH16PGXPR11C_RX_CH17NGXPR11C_RX_CH17PGXPR11C_RX_CH18NGXPR11C_RX_CH18PGXPR11C_RX_CH19NGXPR11C_RX_CH19P
GXPR11C_TX_CH0NGXPR11C_TX_CH0PGXPR11C_TX_CH1NGXPR11C_TX_CH1PGXPR11C_TX_CH2NGXPR11C_TX_CH2PGXPR11C_TX_CH3NGXPR11C_TX_CH3PGXPR11C_TX_CH4NGXPR11C_TX_CH4PGXPR11C_TX_CH5NGXPR11C_TX_CH5PGXPR11C_TX_CH6NGXPR11C_TX_CH6PGXPR11C_TX_CH7NGXPR11C_TX_CH7PGXPR11C_TX_CH8NGXPR11C_TX_CH8PGXPR11C_TX_CH9NGXPR11C_TX_CH9P
GXPR11C_TX_CH10NGXPR11C_TX_CH10PGXPR11C_TX_CH11NGXPR11C_TX_CH11PGXPR11C_TX_CH12NGXPR11C_TX_CH12PGXPR11C_TX_CH13NGXPR11C_TX_CH13PGXPR11C_TX_CH14NGXPR11C_TX_CH14PGXPR11C_TX_CH15NGXPR11C_TX_CH15PGXPR11C_TX_CH16NGXPR11C_TX_CH16PGXPR11C_TX_CH17NGXPR11C_TX_CH17PGXPR11C_TX_CH18NGXPR11C_TX_CH18PGXPR11C_TX_CH19NGXPR11C_TX_CH19P
XCVR BANK 11C
AB2AB1
AA4AA3
Y2Y1
W4W3
V2V1
U4U3
T2T1
R4R3
P2P1
N4N3
M2M1
L4L3
K2K1
J4J3
H2H1
G4G3
E4E3
D2D1
C4C3
F2F1
AA8AA7
Y6Y5
W8W7
V6V5
U8U7
T6T5
R8R7
P6P5
N8N7
M6M5
L8L7
K6K5
J8J7
H6H5
G8G7
F6F5
D6D5
C8C7
B6B5
E8E7
17 PCIE1_UP11_REFCLK0_N17 PCIE1_UP11_REFCLK0_P17 PCIE1_UP11_REFCLK2_N17 PCIE1_UP11_REFCLK2_P
U22_P_IO_RE8REF_0REFCLK_GXPR11C_CH0NREFCLK_GXPR11C_CH0PREFCLK_GXPR11C_CH2NREFCLK_GXPR11C_CH2P
AB12PCIE1_UP11_IO_RE8REFV11
R257
R253 DNI
V10T11T10
DNI
A.8. SlimSAS Connector
Each PCIe or UPI interface connects to two slim SAS connectors, one for transmitsignals and one for receive signals. Cables are used to connect the UPI or PCIe linksfrom the devkit to the host board.
For UPI interface:
• UPI 0 Link, P-tile (10B) is routed to J55(FPGA-to-CPU) and J65(CPU-to-FPGA)
• UPI 1 Link, P-tile (11B) is routed to J38(FPGA-to-CPU) and J40(CPU-to-FPGA)
• UPI 2 Link, P-tile (11C) is routed to J39(FPGA-to-CPU) and J41(CPU-to-FPGA)
A. Development Kit Components
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
60
Figure 42. SlimSAS Connector Pinout
37363534333231302928272625242322212019181716151413121110987654321
37363534333231302928272625242322212019181716151413121110987654321
37363534333231302928272625242322212019181716151413121110987654321
37363534333231302928272625242322212019181716151413121110987654321GND
GND
TX_18_DNTX_18_DP
TX_16_DNTX_16_DP
GNDTX_14_DNTX_14_DP
GNDTX_12_DNTX_12_DP
GNDTX_10_DNTX_10_DP
GNDTX_8_DNTX_8_DP
GNDTX_6_DNTX_6_DP
GNDTX_4_DNTX_4_DP
GNDTX_2_DNTX_2_DP
GNDTX_0_DNTX_0_DP
GND
GND
GND
BCLK_OUT_DNBCLK_OUT_DP
TX_MISC_2TX_MISC_1
A
TX Fixed Connector Pinout
RX Fixed Connector PinoutGND
GND
TX_19_DNTX_19_DP
TX_17_DNTX_17_DP
GNDTX_15_DNTX_15_DP
GNDTX_13_DNTX_13_DP
GNDTX_11_DNTX_11_DP
GNDTX_9_DNTX_9_DP
GNDTX_7_DNTX_7_DP
GNDTX_5_DNTX_5_DP
GNDTX_3_DNTX_3_DP
GNDTX_1_DNTX_1_DP
GND
GND
GND
TX_MISC_6TX_MISC_5
TX_MISC_4TX_MISC_3
BLatchSide
GND
GND
RX_19_DNRX_19_DP
RX_17_DNRX_17_DP
GNDRX_15_DNRX_15_DP
GNDRX_13_DNRX_13_DP
GNDRX_11_DNRX_11_DP
GNDRX_9_DNRX_9_DP
GNDRX_7_DNRX_7_DP
GNDRX_5_DNRX_5_DP
GNDRX_3_DNRX_3_DP
GNDRX_1_DNRX_1_DP
GND
GND
GND
RX_MISC_6RX_MISC_5
RX_MISC_4RX_MISC_3
A
GND
GND
RX_18_DNRX_18_DP
RX_16_DNRX_16_DP
GNDRX_14_DNRX_14_DP
GNDRX_12_DNRX_12_DP
GNDRX_10_DNRX_10_DP
GNDRX_8_DNRX_8_DP
GNDRX_6_DNRX_6_DP
GNDRX_4_DNRX_4_DP
GNDRX_2_DNRX_2_DP
GNDRX_0_DNRX_0_DP
GND
GND
GND
RX_MISC_2RX_MISC_1
BCLK_IN_DNBCLK_IN_DP
BLatchSide
A.9. QSFP Network Interface
The Intel Stratix 10 DX FPGA Development Kit supports two QSFP28 connectors eachconnecting to the E-Tile (9A) transceivers. Each port can operate at 2x50G or 4x25G.These two ports support ZQSFP56 SR Optical modules as well as 3M DAC electricalcables.
The FPC202 dual port controller (from Texas Instruments) serves as the low speedsignal aggregator that makes up the Dual 100Gpbs Ethernet interfaces. The FPC202aggregates all low speed and I2C signals across two ports and presents it as a single
A. Development Kit Components
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
61
management interface to the host. The current limiters TP2557 (from TexasInstruments) also limit the current, in case if there is a short in the DAC electricalcables or Optical modules.
Figure 43. Transceiver QSFP-56 Two Ports of 25GbE
57 ZQSFP0_FPGA_RX0_P57 ZQSFP0_FPGA_RX0_N
58 ZQSFP1_FPGA_RX3_P58 ZQSFP1_FPGA_RX3_N
58 ZQSFP1_FPGA_RX2_P58 ZQSFP1_FPGA_RX2_N
58 ZQSFP1_FPGA_RX1_P58 ZQSFP1_FPGA_RX1_N
58 ZQSFP1_FPGA_RX0_P58 ZQSFP1_FPGA_RX0_N
57 ZQSFP0_FPGA_RX3_P57 ZQSFP0_FPGA_RX3_N
57 ZQSFP0_FPGA_RX2_P57 ZQSFP0_FPGA_RX2_N
57 ZQSFP0_FPGA_RX1_P57 ZQSFP0_FPGA_RX1_N
FPGA_ZQSFP0_TX0_P 57FPGA_ZQSFP0_TX0_N 57
FPGA_ZQSFP1_TX3_P 58FPGA_ZQSFP1_TX3_N 58
FPGA_ZQSFP1_TX2_P 58FPGA_ZQSFP1_TX2_N 58
FPGA_ZQSFP1_TX1_P 58FPGA_ZQSFP1_TX1_N 58
FPGA_ZQSFP1_TX0_P 58FPGA_ZQSFP1_TX0_N 58
FPGA_ZQSFP0_TX3_P 57FPGA_ZQSFP0_TX3_N 57
FPGA_ZQSFP0_TX2_P 57FPGA_ZQSFP0_TX2_N 57
FPGA_ZQSFP0_TX1_P 57FPGA_ZQSFP0_TX1_N 57
GXER9A_RX_CH0NGXER9A_RX_CH0PGXER9A_RX_CH1NGXER9A_RX_CH1PGXER9A_RX_CH2NGXER9A_RX_CH2PGXER9A_RX_CH3NGXER9A_RX_CH3PGXER9A_RX_CH12NGXER9A_RX_CH12PGXER9A_RX_CH13NGXER9A_RX_CH13PGXER9A_RX_CH14NGXER9A_RX_CH14PGXER9A_RX_CH15NGXER9A_RX_CH15P
GXER9A_TX_CH0NGXER9A_TX_CH0PGXER9A_TX_CH1NGXER9A_TX_CH1PGXER9A_TX_CH2NGXER9A_TX_CH2PGXER9A_TX_CH3NGXER9A_TX_CH3P
GXER9A_TX_CH12NGXER9A_TX_CH12PGXER9A_TX_CH13NGXER9A_TX_CH13PGXER9A_TX_CH14NGXER9A_TX_CH14PGXER9A_TX_CH15NGXER9A_TX_CH15P
XCVR BANK 9A
BN8BN7
BL8BL7
BJ8BJ7
GG8GG7
BF5BF4
BE8BE7
BC5BC4
BC8BC7
BP5BP4
BM5BM4
BL2BL1
BK5BK4
BJ2BJ1
BH5BH4
BG2BG1
BE2BE1
16 CLK_156.25M_QSFP0_N16 CLK_156.25M_QSFP0_P16 CLK_156.25M_QSFP1_N16 CLK_156.25M_QSFP1_P
16 CLK_312.5M_QSFP0_N16 CLK_312.5M_QSFP0_P16 CLK_312.5M_QSFP1_N16 CLK_312.5M_QSFP1_P
R218 DNAU11AT11
AY11AW11
AW10AVT10
R219 DN
AU10AT10
R220 DN
R221 DN
BC10BC11
REFCLK_GXER9A_CH0NREFCLK_GXER9A_CH0PREFCLK_GXER9A_CH1NREFCLK_GXER9A_CH1PREFCLK_GXER9A_CH2NREFCLK_GXER9A_CH2PREFCLK_GXER9A_CH3NREFCLK_GXER9A_CH3P
REFCLK_GXER9A_CH8NREFCLK_GXER9A_CH8P
FPGA to ZQSFP0
FPGA to ZQSFP1
ZQSFP0 to FPGA
ZQSFP1 to FPGA
The E-tile (9A) of the Intel Stratix 10 DX FPGA provides eight transceiver channels,channel 0-3 are routed to QSFP0 and channel 12-15 are routed to QSFP1. Thetransceiver bank requires 156.25 MHz clocks for 28 Gbps NRZ and 325.50 MHz clocksfor 56 Gbps PAM4. These clocks must have RPM jitter< 250 fs.
Figure 44. QSFP Connector
A.9.1. Dual Port Controller
The FPC202 dual port controller (from Texas Instruments) serves as the low speedsignal aggregator for the two QSFP ports.
A. Development Kit Components
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
62
Figure 45. Dual Port Controller
7.70 I2C2_IV8_SCL7.70 I2C2_IV8_SDA
7 ZQSFP_1V8_PORT_INT_N
7 ZQSFP_1V8_PORT_EN
29 ZQSFP1_PWR_EN
ZQSFP1_3V3_SDA 29ZQSFP1_3V3_SCL 29
ZQSFP2_3V3_SDA 30ZQSFP2_3V3_SCL 30
ZQSFP1_3V3_RESET_L 29
ZQSFP1_3V3_INT_L 29ZQSFP1_3V3_MODPRS_L 29
ZQSFP1_3V3_LPMODE 29
29 ZQSFP1_FAULT_N3D ZQSFP2_PWR_EN3D ZQSFP2_FAULT_N
I2C 8-bit Addr = 0x1E
2757
55256
4849
47
4445
50
5152
34
3536
373941
3840
33
46
32
29
22
30
85342
25
31
21282423
2620
5443
9
U50
C5201uF
040225VX5R
C5190.1uF040225VX7R
C8231uF
040225VX5R
C8260.1uF040225VX7R
Place a 1uF and 0.1uF per VDD2 pin
??? Limit = 1.452A / 1.742A / 1.???A
Place a 1uF and 0.1uF per VDD1 pin1.8V 3.3V_REG
C8290.1uF040225VX5R
3.3V_REG
R31910.0K04021%
R33610.0K04021%
R33710.0K, DNI04021%
C5182.2uF0603
10VX5R
R3314.70K04021%
1.8V
1.8V
R327 0
0R328
R35023.2K04021%
R31823.2K04021%
R35110.0K04021%
C8480.1uF040225VX7R
C8560.1uF040225VX7R
C8491uF
040225VX5R
C8271uF
040225VX5R
C8280.1uF040225VX7R
R3164.70K04021%
R3824004021%
D20D18
R15324004021%
D21D22
R3324004021%
YELLOW_LED LED_0503GREEN_LED
LED_0603YELLOW LED for 10GON = LINKBLINK = ACTIVITY
R11824004021%
YELLOW_LED LED_0503
GREEN LED for 25GON = LINKBLINK = ACTIVITY
GREEN_LED LED_0603
ZQSFP1_25G_LINK_ACT_LEDnZQSFP1_10G_LINK_ACT_LEDn
ZQSFP2_25G_LINK_ACT_LEDn
ZQSFP2_10G_LINK_ACT_LEDn
R3174.70K04021%
3.3V_ZQSFP1
3.3V_ZQSFP1
3.3V_ZQSFP2
R3484.70K04021%
R3494.70K04021%
3.3V_ZQSFP2
ZQSFP2_3V3_MODPRS_L 30ZQSFP2_3V3_INT_L 30ZQSFP2_3V3_LPMODE 30ZQSFP2_3V3_RESET_L 30
VDD1_1VDD1_2
VDD2_1VDD2_2
CTRL_1CTRL_2CTRL_3CTRL_4
GPIO[0]GPIO[1]GPIO[2]GPIO[3]
SPI_LED_SY_NC
EN
TEST_N
CAPL
DAP (GND)GND
P1_S0_OUT_A
P0_S0_OUT_A
P0_AUX_SDA
P0_S1_IN_A
P0_S1_OUT_A
P0_S1_OUT_CP0_S1_OUT_D
P0_S0_OUT_CP0_S0_OUT_D
P0_MOD_SDA
P0_S0_IN_A
P0_S0_OUT_B
P0_S0_IN_BP0_S0_IN_C
P0_MOD_SCL
P0_S1_OUT_B
P0_S1_IN_BP0_S1_IN_C
P0_AUX_SCL
P1_S0_OUT_BP1_S0_IN_AP1_S0_IN_BP1_S0_IN_C
P1_MOD_SDAP1_MOD_SCL
P1_S0_OUT_CP1_S0_OUT_D
P1_S1_OUT_CP1_S1_OUT_D
P1_S1_OUT_AP1_S1_OUT_B
P1_AUX_SDAP1_AUX_SCL
P1_S1_IN_AP1_S1_IN_BP1_S1_IN_C
FPC202RHUR
PROTOCOL_SEL
HOST_INT_N
VDD1_3
15
14
16
1210
1311
1817
764531
19
GREEN LED for 25GON = LINKBLINK = ACTIVITY
YELLOW LED for 10GON = LINKBLINK = ACTIVITY
A.10. I2C Interface
I2C interface supports communication between integrated circuits on a board. It is asimple two-wire bus that consists of a serial data line (SDA) and a serial clock (SCL).The Intel MAX 10 and Intel Stratix 10 devices use the I2C interface for reading andwriting to various components on the board such as programmable clock generators,VID regulators, ADC, and temperature sensors.
Figure 46. I2C Chain
VcoreAVS I2C1
Master
40h 41h 42h
ATX PWR IN PCIE 12V IN
I2CSlave
I2C
I2C2Master
I2C3Master
Intel MAX 10
PCIE EDGE CONNJ9
PCIE_EDGE_SMB
FX2_I2C
ON-BOARD Intel FPGA Download Cable II
3.3V
3.3V
AUX1HSCU92
AUX2HSC
U217
PCIEHSCU96
9ZML1252EU117
I2C_DDR4T_0_2V52.5V
3.3V
3.3V
I2C2
3.3V
I2C3
3.3VI2C1
D8
UPI / PCIE Clocks
Si5332AU7
M2428SEEPROM
U94
6Ah
DDR4 clocks
Si5391AU9
74h
5Fh/0Bh
I2C2_1V8
FPC202RHURQSFP PORT CTRL
U50
02h/1Eh
ZQSFP1_3V3
E-Tile/ FPGA clocks
I/O expander for clock controls
PCA9534I/O EXPANDER
U232
zQSFP1 J15
MAX3378
UPI0_PCIEI2C Level Shifter
UPI1_PCIE
UPI2_PCIE
BMC_I2C2_DIS
U198,U199
ZQSFP1_3V3
27h (7 bit addr)4Eh (8 bit addr)
3.3V 3.3V
FXMA2101U84
I2C Level Shifter
3.3V 1.8V
ZQSFP2_3V3zQSFP2 J18
HDR
Enpirion DongleJ17
AVS_I2C
EM_I2CI2C Isolator
R342/R343Opconal Path
31h 44h
I2C1
60hI2C_LVC3
PWRMGT SDMVID
Bank 2I
Bank 2J
UPI0 I2C
Bank 2I
Bank 2I
Intel Stratix 10
DX FPGA
1.8V
1.8V
1.8V
I2C1_1V8
BMC_I2C1_DIS
I2C_DDR4T_0_S10
47h
DIMM1J74
DIMM0J73
VCC CoreVID
1.8V
1.8V
9Ah
MAX65818Ch
Temp SensorU32
BMC_I2C3_DIS
7Bh
PAC19324Ch Power
MonitorU233
ISL68137U104
EM21301.8VU113
MAX3378 2.5V3.3V U3
FXMA2101U34
I2C Level Shifter
3.3V 1.8V
MAX3378U2
I2C Level Shifter
2.5V 1.8V
UPI0J55
UPI1J55
UPI2J55
3.3V
EN
FXMA2101U861.8VBMC_I2C2_DIS
I2C Level Shi[er
FXMA2102U8 1.8V3.3V
OE
EM21400.9VU230
EM21303.3VU101
USB PHYCY7C6801
U26
USB ConnCN1
You can use the Intel MAX 10 or Intel Stratix 10 device as the I2C host to access thesedevices, change clock frequencies, or get status information of the board such asvoltage and temperature readings.
A. Development Kit Components
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
63
Table 12. I2C Device Address
Type Bus Address Device
Intel Stratix 10 / Intel MAX 10 I2CAddress
I2C1
0x31 EM2140 (U230)
0x44 EM2130 (U101)
0x47 EM2130 (U113)
I2C2
0xD8/0x6C 97ML1252E (U117)
0x6A Si5332A (U7)
0x74 Si5391A (U9)
0x4E/0x27 PCA9534 (U232)
0x57 M24128 (U94)
0x02 QSFP1 (U50)
0x1E QSFP2 (U50)
I2C3 0x4D/0x9A MAX6581 (U32)
PCIE_EP_3V3_I2C TBD PCIe End Point (J9)
Intel MAX 10 I2C Address AVS_I2C 0x60 ISL68137(U104)
A.11. QSPI Flash Memory
A.11.1. Configuration QSPI Flash Memory
The Intel Stratix 10 DX FPGA Development Kit has one 2-Gbit QSPI flash device fornon-volatile storage of the FPGA configuration data, board information, test applicationdata and user code space.
The flash device is implemented to achieve a 4-bit wide data bus. Only Intel MAX 10CPLD can access this flash device. The Intel MAX 10 CPLD accesses are for AVST x8configuration of the FPGA at power-on and board reset events. It uses the ParallelFlash Loader (PFL) II IP core.
Table 13. Memory Map of the QSPI 2G Flash
Block Access Size Address
Reserved RW 17,920 KB 0x510.0000 - FFF.FFFF
Factory image RW 81,920 KB 0x010.0000 - 50F.FFFF
PFL Option bits RW 960 KB 0x001.0000 - 00F.FFFF
Reserved RW 64 KB 0x000.0000 - 000.FFFF
A.11.2. NIOS QSPI Flash Memory
The Intel Stratix 10 DX FPGA development board has a 64 Mb QSPI flash for non-volatile storage of the NIOS application data, board information, test application data,and user code space.
The quad-serial flash provided has a ×4 data width, which can support an x1 accessmode and ×4 access mode. This memory provides non-volatile storage for Board TestSystem Scratch, Board Information, and other information.
A. Development Kit Components
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
64
Table 14. NIOS QSPI Flash Memory Map
Block Size (KB) Address Description
Board Test System Scratch 512 078.0000 - 07F.FFFF BTS System Testing
Board Information 64 077.0000 - 077.FFFF Board Information
Reserved 7616 000.0000 - 076.FFFF Reserved
Total 8192 - -
A. Development Kit Components
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
65
B. Safety and Regulatory InformationENGINEERING EVALUATION KIT - THIS DEVICE IS INTENDED FOREVALUATION ONLY! NOT FCC APPROVED FOR RESALE
This product has not been tested or approved by any agency or approval body forElectrical Safety, Electromagnetic Compatibility, Wired, or WirelessTelecommunications at the time of distribution.
Sales are limited to product developers, software developers, and system integrators;FCC NOTICE: This development kit is designed to allow:
• Product developers to evaluate electronic components, circuitry, or softwareassociated with the kit to determine whether to incorporate such items in afinished product.
• Software developers to write software applications for use with the end product.This kit is not a finished product and when assembled, may not be resold orotherwise marketed unless all required.
FCC equipment authorizations are first obtained. Operation is subject to the conditionthat this product does not cause harmful interference to licensed radio stations andthat this product does accept harmful interference. Unless the assembled kit isdesigned to operate under part 15, part 18, or part 95 of this chapter, the operator ofthe kit must operate under the authority of an FCC license holder or must secure anexperimental authorization under FCC Part 5 of CFR Title 47.
Safety Certifications that may be required for installation and operation in your regionhave not been obtained.
B.1. Safety Warnings
Power Supply Hazardous Voltage
AC mains voltages are present within the power supply assembly. No user serviceableparts inside the power supply.
UG-20255 | 2019.12.09
Send Feedback
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
Power Connect and Disconnect
The AC power supply cord is the primary disconnect device from mains (AC power)and used to remove all DC power from the board/system. The socket outlet shall beinstalled near the equipment and shall be readily accessible.
System Grounding (Earthing)
To avoid shock, ensure that the power cord is connected to a properly wired andgrounded receptacle. Ensure that any equipment to which this product is attached isalso connected to properly wired and grounded receptacles.
Power Cord Requirements
The connector that plugs into the wall outlet must be a grounding-type male plugwhich is designed for use in your region. It must have certification marks showingcertification by an agency in your region. The connector that plugs into the ACreceptacle on the power supply must be an IEC 320, sheet C13, female connector. Formore information, refer to the website. If the power cord supplied with the systemdoes not meet requirements for use in your region discard the cord, do not use withadapters.
Lightning or Electrical Storm
Do not connect or disconnect any cables or perform installation or maintenance of thisproduct during an electrical storm.
B. Safety and Regulatory Information
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
67
Risk of Fire
To reduce the risk of fire, keep all flammable materials at a safe distance from theboards and power supply and configure the development product on a flame-retardantsurface.
B.2. Safety Cautions
Thermal and Mechanical Injury
Certain components such as heat sinks, power regulators, and processors may be hot,heatsink fans are not guarded, and power supply fan may be accessible throughguard. Care should be taken to avoid contact with these components.
Cooling Requirements
Maintain a minimum clearance area of 5 centimeters (2 inches) around the side, front,and back of the development product for cooling purposes; do not block power supplyventilation holes and fan.
B. Safety and Regulatory Information
UG-20255 | 2019.12.09
Intel® Stratix® 10 DX FPGA Development Kit User Guide Send Feedback
68
Electro Magnetic Interference
This equipment has not been tested for compliance with emission limits of FCC andsimilar international regulations. Use of this equipment in a residential location isprohibited. This equipment generates, uses and can radiate radio frequency energy,which may result in harmful interference to radio communications. If this equipmentdoes cause harmful interference to radio or television reception, which can bedetermined by turning the equipment on and off, take measures to eliminate theinterference.
Telecommunications Port Restrictions
The wireline telecommunication ports (modem, xDSL, T1/E1) on this product must notbe connected to the Public Switched Telecommunication Network (PSTN) as it mightresult in disruption of the network. No formal telecommunication certification to FCC,R&TTE Directive, or other national requirements has been obtained.
Electrostatic Discharge Warning
A properly grounded ESD wrist strap must be worn during operation/installation of theboards, connection of cables, or during installation or removal of daughter cards.Failure to do so can damage components within the system.
Please return this product to Intel for proper disposition. If it is not returned,refer to the local environmental regulations for proper recycling; do notdispose this product in any unsorted municipal waste.
B. Safety and Regulatory Information
UG-20255 | 2019.12.09
Send Feedback Intel® Stratix® 10 DX FPGA Development Kit User Guide
69
C. Compliance and Conformity InformationCE EMI Conformity Caution
Hereby, Intel Corporation declares that the Intel Stratix 10 DX FPGA Development KitBoard is in compliance with Directives 2014/30/EU, 2014/35/EU and 2011/65/EU.Because of the nature of programmable logic devices, it is possible for the end user tomodify the development kit in such a way as to generate electromagnetic interference(EMI) that exceeds the limits established for this equipment. Any caused as a result ofmodifications to the delivered material is the responsibility of the user of thisdevelopment kit.
Att. Corp Quality, Intel Deutschland GmbH,
Am Campeon 10-12, Neubiberg, 85579 - Germany
For more information, refer to the EU declaration of conformity.
UG-20255 | 2019.12.09
Send Feedback
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered