Download pdf - DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

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PLB Double Data Rate (DDR2) Synchronous DRAM (SDRAM) Controller (v101a)

DS326 March 22 2006 0 0 Product Specification

IntroductionThe Xilinx Processor Local Bus DDR2 SDRAM (PLB DDR2 SDRAM) controller connects to the PLB and provides the control interface for DDR2 SDRAMs It is assumed that the reader is familiar with DDR2 SDRAMs and the IBM PowerPC

FeaturesThe Xilinx PLB DDR2 SDRAM controller is a soft IP core designed for Xilinx FPGAs and contains the following featuresbull Supports PLB interfacebull Performs device initialization sequence upon power-up and

reset conditions for ~200 usbull Performs auto-refresh cyclesbull Supports 32-bit and 64-bit of DDR2 SDRAM devicesbull Provides big-endian connections to memory devices bull Supports single-beat and burst transactions bull Supports target-word first cache-line transactions bull Supports indeterminate burst length transactions on the PLBbull Supports On Die Termination (ODT) selectable by a design

parameterbull Supports multiple (4 8) internal DDR2 SDRAM banksbull Supports multiple (up to 4) external DDR2 SDRAM banksbull Capable to separate DDR2 SDRAM clock frequency domain

from PLB clock frequency domain Following combinations of frequencies are tested- PLB clock = 100 MHz and DDR2 clock = 133 MHz- PLB clock = 100 MHz and DDR2 clock = 200 MHz- PLB clock = 100 MHz and DDR2 clock = 266 MHz

bull Supports CAS latencies of 3 4 and 5 bull Supports differential DQS capability for DDR2 SDRAM

devicesbull Supports DDR2 SDRAM burst size of 4bull Supports open row management capability selectable

by a design parameterbull Supports Error Correction Code (ECC) for 32-bit data width

of DDR2 SDRAM

LogiCOREtrade Facts

Core Specifics

Supported Device Family Virtex-II Pro Virtex-4

Version of Core plb_ddr2 v101a

Resources Used

Min Max

Virtex-II Pro Virtex-4 Virtex-II

Pro Virtex-4

Slices

See Table 23 amp Table 24LUTs

FFs

Block RAMs NA NA

Provided with Core

Documentation Product Specification

Design File Formats VHDL

Constraints File NA

Verification NA

Instantiation Template NA

Reference Designs None

Design Tool Requirements

Xilinx Implementation Tools

ISE 81i or later

Verification NA

Simulation ModelSim SEPE 60a or later

Synthesis XST 81i or later

Support

Support provided by Xilinx Inc

devices

Discontinued IP

DS326 March 22 2006 wwwxilinxcom 1Product Specification

copy 2005 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and further disclaimers are as listed at httpwwwxilinxcomlegalhtm All other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without noticeNOTICE OF DISCLAIMER Xilinx is providing this design code or information as is By providing the design code or information as one possible implementation of this fea-ture application or standard Xilinx makes no representation that this implementation is free from any claims of infringement You are responsible for obtaining any rights you may require for your implementation Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation including but not limited to any warran-ties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose

PLB DDR2 SDRAM Controller Design ParametersTo allow a user to create a PLB DDR2 SDRAM controller that is uniquely tailored for the system certain features are parameterizable in the PLB DDR2 SDRAM controller design This allows a user to have a design that only utilizes the resources required by the system and runs at the best possible performance The features that are parameterizable in the PLB DDR2 SDRAM controller are shown in Table 1

Table 1 PLB DDR2 SDRAM Controller Design Parameters

Generic Feature Description Parameter Name Allowable ValuesDefault Value

VHDL Type

PLB DDR2 SDRAM Controller Features

G1 Include logic to support PLB bursts and cacheline transactions

C_INCLUDE_BURST_CACHELN_SUPPORT

0 = Controller will break up PLB burst or cacheline transfers into single memory read or write operations1 = Include logic to support PLB bursts and cacheline transfers

0 integer

G2 Include support for registered DIMM

C_REG_DIMM 0 = Unregistered DIMM1 = Registered DIMM

0 integer

G3 Supported number of external DDR2 SDRAM memory banks

C_NUM_BANKS_MEM(1) 1 - 4 1 integer

G4 Include logic to create extra setup time on DDR2 SDRAM address and control signals

C_EXTRA_TSU 0 = Does not create extra setup time1 = Creates extra setup time

0 integer

G5 Number of generated clock pairs supplied to the DDR2 SDRAM memory

C_NUM_CLK_PAIRS 1 - 4 1 integer

G6 Target FPGA family C_FAMILY virtex2p virtex4 virtex2p string

G7 Number of IDELAYCTRL modules to instantiate for Virtex-4 implementation

C_NUM_IDELAYCTRL 1 - 20 1 integer

G8 Include logic to separate DDR2 SDRAM clock domain from PLB clock domain

C_DDR_ASYNC_SUPPORT 1 = Include logic to separate DDR2 SDRAM clock domain from PLB clock domain0 = Not supported

1 integer

G9 Enable differential DQS capability for DDR2 SDRAM devices

C_DDR_ENABLE_DIFF_DQS

0 = Disable differential DQS logic1 = Enable differential DQS logic

0 integer

G10 Support open row management in DDR2 controller

C_USE_OPEN_ROW_MNGT

0 = Disable open row management capability1 = Support open row management

0 integer

Discontinued IP

2 wwwxilinxcom DS326 March 22 2006Product Specification

G10 On Die Termination selection

C_DDR2_ODT_SETTING 0 75 1500 = Disables ODT 75 = Enables ODT and On Die Terminating resistance (Rtt) will be 75 Ω

150 = ODT enabled and Rtt will be 150 Ω

0 integer

Error Correction Code (ECC) Features

G11 Include support for ECC logic(2)

C_INCLUDE_ECC_SUPPORT

0 = Donrsquot include logic to support ECC1 = Include logic to support ECC

0 integer

G12 Enable use of ECC registers including ECCCR ECCSR ECCSEC ECCDEC amp ECCPEC

C_ENABLE_ECC_REG 0 = Disables all ECC and IPIF interrupt registers (all register default conditions are implemented)1 = Enable all ECC registers

1 integer

G13 ECC default enable or disable condition (controls reset condition of ECCCR[3031])

C_ECC_DEFAULT_ON 0 = ECC default disable (must write to ECCCR to enable ECC)1 = ECC default enable

1 integer

G14 Support interrupts in IPIF for ECC error conditions (Enables use of IPIF interrupt registers)

C_INCLUDE_ECC_INTR 0 = No ECC error interrupt support (no IPIF interrupt registers available)1 = ECC error interrupts supported (IPIF interrupt registers available)

0 integer

G15 Support ECC force error testing

C_INCLUDE_ECC_TEST 0 = No ECC test support1 = Enable ECC test support

0 integer

G16 Specifies single-bit data error interrupt threshold counter value

C_ECC_SEC_THRESHOLD 1 - 4095(3) 1 integer

G17 Specifies double-bit data error interrupt threshold counter value

C_ECC_DEC_THRESOLD 1 - 4095(3) 1 integer

G18 Specifies parity field bit error interrupt threshold counter value

C_ECC_PEC_THRESHOLD 1 - 4095(3) 1 integer

G19 Internal parameter to indicate the number of ECC check bits

C_NUM_ECC_BITS 7 = Fixed for the 32-bit DDR2 SDRAM memory

7 integer

Table 1 PLB DDR2 SDRAM Controller Design Parameters (Continued)

VHDL Type

Discontinued IP

G20 Load Mode Register command cycle time (ps)

C_DDR_TMRD Note(4) 15000 integer

G21 Write Recovery Time (ps) C_DDR_TWR Note(4) 15000 integer

G22 Write-to-Read Command Delay (Tck)

C_DDR_TWTR Note(4) 1 integer

G23 Delay after ACTIVE command before PRECHARGE command (ps)

C_DDR_TRAS Note(4) 45000 integer

G24 Delay after ACTIVE command before another ACTIVE or AUTOREFRESH command (ps)

C_DDR_TRC Note(4) 65000 integer

G25 Delay after AUTOREFRESH before another command (ps)

C_DDR_TRFC Note(4) 75000 integer

G26 Delay after ACTIVE command before READWRITE command (ps)

C_DDR_TRCD Note(4) 21000 integer

G27 Delay after ACTIVE command for row before ACTIVE command for another row (ps)

C_DDR_TRRD Note(4) 10000 integer

G28 Delay after PRECHARGE command (ps)

C_DDR_TRP Note(4) 20000 integer

G29 Average periodic refresh command interval (ps)

C_DDR_TREFI Note(4) 7800000 integer

G30 No more than 4 bank ACTIVE commands may be issued in a given tFAW(min) period (ps)

C_DDR_TFAW Note(4 5) 50000 integer

G31 CAS Latency C_DDR_CAS_LAT 3 4 5 3 integer

G32 Cumulative data width of DDR2 SDRAM

C_DDR_DWIDTH 32 64 32 integer

G33 DDR2 SDRAM address width

C_DDR_AWIDTH Note(6) 13 integer

G34 DDR2 SDRAM column address width

C_DDR_COL_AWIDTH Note(6) 9 integer

G35 DDR2 SDRAM bank address width(6)

C_DDR_BANK_AWIDTH 2 3 2 integer

VHDL Type

Discontinued IP

Allowable Parameter CombinationsThe user must be aware of following parameter combinationsbull The PLB DDR2 SDRAM controller supports four memory address ranges of DDR2 SDRAM Each memory address range of

G36 DDR2 SDRAM clock period (ps)

C_DDR_CLK_PERIOD_PS 3750 5000 7500 5000 integer

Address Space

G37 Base Address for Memory x (x = 0 to 3)

C_MEMx_BASEADDR Valid address(78) - std_logic_vector

G38 High Address for Memory x (x = 0 to 3)

C_MEMx_HIGHADDR Valid address(78) - std_logic_vector

G39 ECC register base address C_ECC_BASEADDR Valid address(9) - std_logic_vector

G40 ECC register high address C_ECC_HIGHADDR Valid address(9) - std_logic_vector

PLB Interface

G41 PLB data bus width C_PLB_DWIDTH 64 64 integer

G42 PLB address bus width C_PLB_AWIDTH 32 32 integer

G43 Number of PLB masters C_PLB_NUM_MASTERS 1 - 16 4 integer

G44 PLB clock period (ps) C_PLB_CLK_PERIOD_PS - 10000 integer

Simulation Only

G45 DDR2 SDRAM initialization time for simulation(10) (ps)

C_SIM_INIT_TIME_PS ge 200 us 200000000 integer

Auto Calculated Parameter

G46 Number of bits required to encode the number of PLB Masters

C_PLB_MID_WIDTH 1 - log2 (C_PLB_NUM_MASTERS)

2 integer

Notes 1 C_NUM_BANKS_MEM specifies the number of DDR2 SDRAM slots with identical device characteristics All the DDR2 SDRAM device

characteristics specified in parameters G20 through G36 are applicable for each external DDR2 SDRAM banks2 ECC support only when C_DDR_DWIDTH = 32 3 Threshold values are limited by size of error counter registers Current implementation has 12-bit counter registers 4 Values are as per the DDR2 SDRAM JEDEC standard C_DDR_AWIDTH + C_DDR_COL_AWIDTH + C_DDR_BANK_AWIDTH +

log2(C_DDR_DWIDTH8) must be lt C_PLB_AWIDTH - 15 C_DDR_TFAW setting is only valid when C_DDR_BANK_AWIDTH = 36 Values are as per the DDR2 SDRAM JEDEC standard C_DDR_AWIDTH + C_DDR_COL_AWIDTH + C_DDR_BANK_AWIDTH +

log2(C_DDR_DWIDTH8) must be lt C_PLB_AWIDTH - 1 7 The address range generics are designated as C_MEM0_BASEADDR C_MEM1_BASEADDR C_MEM0_HIGHADDR

C_MEM1_HIGHADDR etc8 The range specified by C_MEMx_BASEADDR and C_MEMx_HIGHADDR must comprise a complete contiguous power of two range such

that range = 2n and the n least significant bits of C_MEMx_BASEADDR must be zero9 The range specified by C_ECC_BASEADDR and C_ECC_HIGHADDR must comprise a complete contiguous power of two range such that

range = 2n and the n least significant bits of C_ECC_BASEADDR must be zero10 This parameter adjusts the initialization time of the DDR2 SDRAM for simulation only Must be ge 200 us

VHDL Type

Discontinued IP

DDR2 SDRAM has its own independent base address and address range Each address range specified by C_MEMx_BASEADDR and C_MEMx_HIGHADDR must comprise a complete contiguous power of two range such that range = 2m and the m least significant bits of C_MEMx_BASEADDR must be zero The range specified by these parameters should not exceed the DDR2 SDRAM space

bull The address range specified by C_ECC_BASEADDR and C_ECC_HIGHADDR must comprise a complete contiguous power of two such that range = 2n and the n least significant bits of C_ECC_BASEADDR must be zero

bull The ECC logic is included only when C_DDR_DWIDTH = 32 and C_INCLUDE_ECC_SUPPORT = 1bull The parameter C_EXTRA_TSU is ignored when C_REG_DIMM = 1

PLB DDR2 SDRAM Controller IO SignalsTable 2 provides a summary of all PLB DDR2 SDRAM controller inputoutput (IO) signals

Table 2 PLB DDR2 SDRAM Controller IO signal Descriptions

Port Signal Name Interface IOInitial State Description

DDR2 SDRAM Signals

P1 DDR_Clk[0C_NUM_CLK_PAIRS - 1] DDR2 O 0 DDR2 SDRAM clock(2)

P2 DDR_Clkn[0C_NUM_CLK_PAIRS - 1] DDR2 O 1 DDR2 SDRAM inverted clock

P3 DDR_CKE[0C_NUM_BANKS_MEM - 1] DDR2 O 0 DDR2 SDRAM clock enable

P4 DDR_CSn[0C_NUM_BANKS_MEM - 1] DDR2 O 1 Active low DDR2 SDRAM chip select(s)

P5 DDR_RASn DDR2 O 1 Active low DDR2 SDRAM row address strobe

P6 DDR_CASn DDR2 O 1 Active low DDR2 SDRAM column address strobe

P7 DDR_WEn DDR2 O 1 Active low DDR2 SDRAM write enable

P8 DDR_DM[0C_DDR_DWIDTH8 - 1] DDR2 O 1 DDR2 SDRAM data mask

P9 DDR_BankAddr[0C_DDR_BANK_AWIDTH - 1] DDR2 O 0 DDR2 SDRAM bank address

P10 DDR_Addr[0C_DDR_AWIDTH - 1] DDR2 O 0 DDR2 SDRAM address

P11 DDR_DQ_o[0C_DDR_DWIDTH - 1] DDR2 O 0 Output data to DDR2 SDRAM

P12 DDR_DQ_i[0C_DDR_DWIDTH - 1] DDR2 I - Input data from DDR2 SDRAM

P13 DDR_DQ_t[0C_DDR_DWIDTH - 1] DDR2 O 0 3-state enable for DDR2 SDRAM data buffers

P14 DDR_DQS_o[0C_DDR_DWIDTH8 - 1] DDR2 O 0 Output data strobe to DDR2 SDRAM

P15 DDR_DQS_i[0C_DDR_DWIDTH8 - 1] DDR2 I - Input data strobe from DDR2 SDRAM

P16 DDR_DQS_t[0C_DDR_DWIDTH8 - 1] DDR2 O 1 3-state enable for DDR2 SDRAM data strobe buffers

P17 DDR_DQSn_o[0C_DDR_DWIDTH8 - 1] DDR2 O 0 Output differential data strobe to DDR2 SDRAM

P18 DDR_DQSn_i[0C_DDR_DWIDTH8 - 1] DDR2 I - Input differential data strobe from DDR2 SDRAM

Discontinued IP

P19 DDR_DQSn_t[0C_DDR_DWIDTH8 - 1] DDR2 O 1 3-state enable for DDR2 SDRAM differential data strobe buffers

P20 DDR_DM_ECC DDR2 O 1 DDR2 SDRAM ECC data mask

P21 DDR_DQ_ECC_o[0C_NUM_ECC_BITS - 1] DDR2 O 0 Output ECC data to DDR2 SDRAM

P22 DDR_DQ_ECC_i[0C_NUM_ECC_BITS - 1] DDR2 I - Input ECC data from DDR2 SDRAM

P23 DDR_DQ_ECC_t[0C_NUM_ECC_BITS - 1] DDR2 O 0 3-state enable for DDR2 SDRAM ECC data buffer

P24 DDR_DQS_ECC_o DDR2 O 1 Output ECC data strobe to DDR2 SDRAM

P25 DDR_DQS_ECC_i DDR2 I - Input ECC data strobe from DDR2 SDRAM

P26 DDR_DQS_ECC_t DDR2 O 0 3-state enable for DDR2 SDRAM ECC data strobe buffers

P27 DDR_DQSn_ECC_o DDR2 O 1 Output differential ECC data strobe to DDR2 SDRAM

P28 DDR_DQSn_ECC_i DDR2 I - Input differential ECC data strobe from DDR2 SDRAM

P29 DDR_DQSn_ECC_t DDR2 O 0 3-state enable for DDR2 SDRAM differential ECC data strobe buffers

P30 DDR_ODT[0C_NUM_BANKS_MEM - 1](1) DDR2 O 0 ODT signal for DDR2 SDRAM

P31 DDR_Init_done DDR2 O 0 Indicates the DDR2 SDRAM initialization is complete

Clock Signals

P32 Device_Clk CLK(2) I - Device clock

P33 Device_Clk_n CLK(2) I - Device clock phase shifted by 180 degrees

P34 Device_Clk90_in CLK(2) I - Device clock phase shifted by 90 degrees

P35 Device_Clk90_in_n CLK(2) I - Device clock phase shifted by 270 degrees

P36 DDR_Clk90_in(3) CLK(2) I - DDR2 SDRAM feedback clock shifted by 90 degrees

P37 DDR_Clk90_in_n(3) CLK(2) I - DDR2 SDRAM feedback clock shifted by 270 degrees

P38 Clk_200(4) CLK I - 200 MHz clock input used in Virtex-4 implementation

P39 Cal_Clk (4) CLK I - 14 Clk_200 clock input used in Virtex-4 implementation

PLB Slave Signals(5)

P40 PLB_PAValid PLB I - PLB primary address valid indicator

Table 2 PLB DDR2 SDRAM Controller IO signal Descriptions (Continued)

Discontinued IP

P41 PLB_busLock PLB I - PLB lock

P42 PLB_masterID[0C_PLB_MID_WIDTH - 1] PLB I - PLB current master indicator

P43 PLB_RNW PLB I - PLB read not write

P44 PLB_BE[0C_PLB_DWIDTH8 - 1] PLB I - PLB byte enables

P45 PLB_size[03] PLB I - PLB transfer size

P46 PLB_type[02] PLB I - PLB transfer type

P47 PLB_MSize[01] PLB I - PLB master data bus size

P48 PLB_compress PLB I - PLB compressed data transfer indicator

P49 PLB_guarded PLB I - PLB guarded transfer indicator

P50 PLB_ordered PLB I - PLB synchronize transfer indicator

P51 PLB_lockErr PLB I - PLB lock error indicator

P52 PLB_abort PLB I - PLB abort bus request indicator

P53 PLB_ABus[0C_PLB_AWIDTH - 1] PLB I - PLB address bus

P54 PLB_SAValid PLB I - PLB secondary address valid indicator

P55 PLB_rdPrim PLB I - PLB secondary to primary read request indicator

P56 PLB_wrPrim PLB I - PLB secondary to primary write request indicator

P57 PLB_wrDBus[0C_PLB_DWIDTH - 1] PLB I - PLB write data bus

P58 PLB_wrBurst PLB I - PLB burst write transfer indicator

P59 PLB_rdBurst PLB I - PLB burst read transfer indicator

P60 Sl_addrAck PLB O 0 Slave address acknowledge

P61 Sl_wait PLB O 0 Slave wait indicator

P62 Sl_SSize[01] PLB O 0 Slave data bus size

P63 Sl_rearbitrate PLB O 0 Slave rearbitrate bus indicator

P64 Sl_MBusy[0C_PLB_NUM_MASTERS - 1] PLB O 0 Slave busy indicator

P65 Sl_MErr[0C_PLB_NUM_MASTERS - 1] PLB O 0 Slave error indicator

P66 Sl_wrDAck PLB O 0 Slave write data acknowledge

P67 Sl_wrComp PLB O 0 Slave write transfer complete indicator

P68 Sl_wrBTerm PLB O 0 Slave terminate write burst transfer

P69 Sl_rdDBus[0C_PLB_DWIDTH - 1] PLB O 0 Slave read bus

P70 Sl_rdWdAddr[03] PLB O 0 Slave read word address

P71 Sl_rdDAck PLB O 0 Slave read data acknowledge

Discontinued IP

P72 Sl_rdComp PLB O 0 Slave read transfer complete indicator

P73 Sl_rdBTerm PLB O 0 Slave terminate read burst transfer

P74 IP2INTC_Irpt PLB O 0 System interrupt controller

P75 PLB_Clk PLB I - PLB clock

P76 PLB_Rst PLB I - PLB reset

Notes 1 When this signal is asserted high the selected Rtt value is specified by the parameter C_DDR2_ODT_SETTING For more information please

refer to section On Die Termination (ODT)2 For more information on clocking options please refer to section DDR2 SDRAM Clocking3 Input signal is unused when targeting for Virtex-4 architecture4 Input signal is unused when targeting architecture other than Virtex-45 Please refer to the IBM PLB Architecture specification for more detailed information on these signals

Discontinued IP

Parameter-Port DependenciesThe dependencies between the PLB DDR2 SDRAM controller design parameters and IO signals are shown in Table 3 When certain features are parameterized the related logic will not be part of the design the unused input signals and related output signals are set to a specified value

Table 3 Parameter-Port Dependencies

Generic or Port Parameter Affects Depends Description

Design ParametersG3 C_NUM_BANKS_MEM P3 P4

P30- Specifies the number of external DDR2

SDRAM banks

G5 C_NUM_CLK_PAIRS P1 P2 - Number of generated DDR2 SDRAM clock pairs

G11 C_INCLUDE_ECC_SUPPORT P20 P21P22 P23P24 P25P26 P27P28 P29

G32 ECC signals are used when C_INCLUDE_ECC_SUPPORT = 1 and C_DDR_DWIDTH = 32

G12 C_ENABLE_ECC_REG - G32 G11 Parameter is used when C_INCLUDE_ECC_SUPPORT = 1 and C_DDR_DWIDTH = 32

G13 C_ECC_DEFAULT_ON - G32 G11 Parameter is used when C_INCLUDE_ECC_SUPPORT = 1 and C_DDR_DWIDTH = 32

G14 C_INCLUDE_ECC_INTR P74 G32 G11 G12

Parameter is available when C_INCLUDE_ECC_SUPPORT = 1 and C_ENABLE_ECC_REG = 1 and C_DDR_DWIDTH = 32

G15 C_INCLUDE_ECC_TEST - G32 G11 G12

Parameter is used when C_INCLUDE_ECC_SUPPORT = 1 and C_ENABLE_ECC_REG = 1 and C_DDR_DWIDTH = 32

G16 C_ECC_SEC_THRESHOLD - G32 G11 G12 G14

Parameter is used when C_INCLUDE_ECC_SUPPORT = 1 and C_ENABLE_ECC_REG = 1 and C_INCLUDE_ECC_INTR = 1 and C_DDR_DWIDTH = 32

G17 C_ECC_DEC_THRESHOLD - G32 G11 G12 G14

G18 C_ECC_PEC_THRESHOLD - G32 G11 G12 G14

Discontinued IP

G39 C_ECC_BASEADDR - G32 G11 G12

G40 C_ECC_HIGHADDR - G32 G11 G12

G19 C_NUM_ECC_BITS P21 P22 P23

G32 G11 The parameter is used when C_INCLUDE_ECC_SUPPORT = 1 and C_DDR_DWIDTH = 32

G32 C_DDR_DWIDTH P8 P11 P12 P13P14 P15P16 P17P18 P19P20 P21P22 P23P24 P25P26 P27P28 P29

- All ECC related signals are used only when C_DDR_DWIDTH = 32 and C_INCLUDE_ECC_SUPPORT = 1

G33 C_DDR_AWIDTH P10 - Size of port depends on setting of C_ADDR_WIDTH parameter

G35 C_DDR_BANK_AWIDTH P9 - Size of port depends on C_DDR_BANK_AWIDTH parameter setting

G9 C_DDR_ENABLE_DIFF_DQS P17 P18P19 P27P28 P29

- Input signals are unused and output signals are set to the default value when C_DDR_ENABLE_DIFF_DQS = 0

G6 C_FAMILY P36 P37 P38 P39

- Input clock signals are used when C_FAMILY = virtex4

IO Signals

P1 DDR_Clk[0C_NUM_CLK_PAIRS - 1] - G5 The number of clock pairs is generated based on C_NUM_CLK_PAIRS

P2 DDR_Clkn[0C_NUM_CLK_PAIRS - 1] - G5 The number of inverted clock pairs is generated based on C_NUM_CLK_PAIRS

P3 DDR_CKE[0C_NUM_BANKS_MEM - 1]

- G3 The number of clock enables is generated based on C_NUM_BANKS_MEM

P4 DDR_CSn[0C_NUM_BANKS_MEM - 1] - G3 The number of chip selects is generated based on C_NUM_BANKS_MEM

Table 3 Parameter-Port Dependencies (Continued)

Discontinued IP

P8 DDR_DM[0C_DDR_DWIDTH8 - 1] - G32 Width of data mask signal depends on generic C_DDR_DWIDTH

P9 DDR_BankAddr[0C_DDR_BANK_AWIDTH]

- G35 Bank address width depends on generic C_DDR_BANK_AWIDTH

P10 DDR_Addr[0C_DDR_AWIDTH - 1] - G33 DDR2 SDRAM address width depends on generic C_DDR_AWIDTH

P11 DDR_DQ_o[0C_DDR_DWIDTH - 1] - G32 Data output width depends on generic C_DDR_DWIDTH

P12 DDR_DQ_i[0C_DDR_DWIDTH - 1] - G32 Data input width depends on generic C_DDR_DWIDTH

P13 DDR_DQ_t[0C_DDR_DWIDTH - 1] - G32 Data 3-state enable signal width depends on generic C_DDR_DWIDTH

P74 IP2INTC_Irpt - G11 G12 G14

Interrupt output signal is used when C_INCLUDE_ECC_SUPPORT = 1 and C_ENABLE_ECC_REG = 1 and C_INCLUDE_ECC_INTR = 1

P30 DDR_ODT[0C_NUM_BANKS_MEM - 1] - G3 On Die Termination signal width depends on generic C_NUM_BANKS_MEM

P14 DDR_DQS_o[0C_DDR_DWIDTH8 - 1] - G21 Output data strobe width depends on generic C_DDR_DWIDTH

P15 DDR_DQS_i[0C_DDR_DWIDTH8 - 1] - G32 Input data strobe width depends on generic C_DDR_DWIDTH

P16 DDR_DQS_t[0C_DDR_DWIDTH8 - 1] - G33 3-state enable data strobe width depends on generic C_DDR_DWIDTH

P17 DDR_DQSn_o[0C_DDR_DWIDTH8 - 1]

- G32 G9 Output differential data strobe width depends on generic C_DDR_DWIDTH Output is driven high when C_DDR_ENABLE_DIFF_DQS = 0

P18 DDR_DQSn_i[0C_DDR_DWIDTH8 - 1] - G32 G9 Input differential data strobe width depends on generic C_DDR_DWIDTH Input signals is unused when C_DDR_ENABLE_DIFF_DQS = 0

P19 DDR_DQSn_t[0C_DDR_DWIDTH8 - 1] - G32 G9 3-state enable differential data strobe width depends on generic C_DDR_DWIDTH Signals is unused when C_DDR_ENABLE_DIFF_DQS = 0

P20 DDR_DM_ECC - G11 G32 ECC data mask output driven high when C_INCLUDE_ECC_SUPPORT = 0 or C_DDR_DWIDTH = 64

Discontinued IP

P21 DDR_DQ_ECC_o[0C_NUM_ECC_BITS - 1]

- G18 G11 G32

ECC data output width depends on generic C_NUM_ECC_BITS ECC output is driven low when C_INCLUDE_ECC_SUPPORT = 0 or C_DDR_DWIDTH = 64 and should not be used

P22 DDR_DQ_ECC_i[0C_NUM_ECC_BITS - 1]

- G19 G11 G32

ECC data input width depends on generic C_NUM_ECC_BITS ECC input is unused when C_INCLUDE_ECC_SUPPORT = 0 or C_DDR_DWIDTH = 64

P23 DDR_DQ_ECC_t[0C_NUM_ECC_BITS - 1]

- G19 G11 G32

ECC data 3-state enable signal width depends on generic C_NUM_ECC_BITS ECC data 3-state enable signal is unused when C_INCLUDE_ECC_SUPPORT = 0 or C_DDR_DWIDTH = 64

P24 DDR_DQS_ECC_o - G11 G32 ECC output data strobe is driven high When C_INCLUDE_ECC_SUPPORT = 0 or C_DDR_DWIDTH = 64

P25 DDR_DQS_ECC_i - G11 G32 ECC input data strobe is grounded When C_INCLUDE_ECC_SUPPORT = 0 or C_DDR_DWIDTH = 64

P26 DDR_DQS_ECC_t - G11 G32 ECC 3-state enable data strobe signal is unused when C_INCLUDE_ECC_SUPPORT= 0 or C_DDR_DWIDTH = 64

P27 DDR_DQSn_ECC_o - G9 G11 G32

ECC output differential ECC data strobe is driven high when C_INCLUDE_ECC_SUPPORT= 0 or C_DDR_ENABLE_DIFF_DQS = 0 or C_DDR_DWIDTH = 64

P28 DDR_DQSn_ECC_i - G9 G11 G32

ECC input differential ECC data strobe is unused when C_INCLUDE_ECC_SUPPORT= 0 or C_DDR_ENABLE_DIFF_DQS = 0 or C_DDR_DWIDTH = 64

P29 DDR_DQSn_ECC_t - G9 G11 G32

ECC 3-state enable differential ECC data strobe signal is unused when C_INCLUDE_ECC_SUPPORT= 0 or C_DDR_ENABLE_DIFF_DQS = 0 or C_DDR_DWIDTH = 64

P36 DDR_CLK90_in - G6 Unused when C_FAMILY = virtex4

P37 DDR_CLK90_in_n - G6 Unused when C_FAMILY = virtex4

P38 Clk_200 - G6 Used when C_FAMILY = virtex4

P39 Cal_Clk - G6 Used when C_FAMILY = virtex4

Discontinued IP

DDR2 ECC Register DescriptionsThe PLB DDR2 SDRAM controller registers shown in Table 4 are included with the ECC logic for the PLB DDR2 SDRAM controller by using the ECC parameters shown in Table 1 when enabled (C_ENABLE_ECC_REG = 1)

Table 4 ECC Register Summary

GroupingBase Address + Offset

(hex)Register

NameAccess Type

Default Value (hex) Description

ECC Core C_ECC_BASEADDR + 0

ECCCR(1) RW 00000003(4) ECC Control Register

C_ECC_BASEADDR + 4

ECCSR(1) RROW(3) 00000000 ECC Status Register

C_ECC_BASEADDR + 8

ECCSEC(1) RROW(3) 00000000 ECC Single Error Count Register

C_ECC_BASEADDR + C

ECCDEC(1) RROW(3) 00000000 ECC Double Error Count Register

C_ECC_BASEADDR + 10

ECCPEC(1) RROW(3) 00000000 ECC Parity field Error Count Reg-ister

PLB IPIF ISC C_ECC_BASEADDR + 11C

DGIE(2) RW 00000000 Device Global Interrupt Enable Register

C_ECC_BASEADDR + 120

IPISR(2) RTOW(5) 00000000 IP Interrupt Status Register

IPIER(2) RW 00000000 IP Interrupt Enable Register

Notes 1 Only used if C_INCLUDE_ECC_SUPPORT = 1 C_ENABLE_ECC_REG = 1 and C_DDR_DWIDTH = 322 Only used if C_INCLUDE_ECC_SUPPORT = 1 C_ENABLE_ECC_REG = 1 C_INCLUDE_ECC_INTR = 1 and

C_DDR_DWIDTH = 323 ROW = Reset On Write A write operation will reset the register4 Reset condition of ECCCR depends on the value of parameter C_ECC_DEFAULT_ON5 TOW = Toggle On Write Writing rsquo1rsquo to a bit position within the register causes the corresponding bit position in the register to toggle

ECC Control Register (ECCCR)Note This register is available only when C_INCLUDE_ECC_SUPPORT = 1 and C_ENABLE_ECC_REG = 1 and C_DDR_DWIDTH = 32

The ECC Control Register is shown in Figure 1 The ECC Control Register determines if ECC check bits will be generated during mem-ory write operation and checked during a memory read operation The ECC Control Register also defines testing modes if enabled by the parameter C_INCLUDE_ECC_TEST Table 5 defines the bit values for the ECCCR

Discontinued IP

Figure 1 ECC Control Register

FORCE_DE RE

darr darr

0 26 27 28 29 30 31

uarr uarr uarr uarrUnused FORCE_

PEFORCE_

SE WE

Table 5 ECCCR Bit Definitions

Bit(s) NameCore

AccessReset Value Description

0-26 Reserved

27 FORCE_PE RW rsquo0rsquo Force Parity Field Bit Error(1) Available for testing and determines if parity field bit errors are forced in the data stored in the memory See ECC Testing for more information rsquo0rsquo = No parity field bit errors are created rsquo1rsquo = Parity field bit errors are forced in stored data

28 FORCE_DE RW rsquo0rsquo Force Double-bit Error(1) Available for testing and determines if double-bit errors are forced in the data stored in the memory See ECC Testing for more information rsquo0rsquo = No double-bit errors are created rsquo1rsquo = Double-bit errors are forced in the stored data

29 FORCE_SE RW rsquo0rsquo Force Single-bit Error(1) Available for testing and determines if single-bit errors are forced in the data stored in the memory See ECC Testing for more information rsquo0rsquo = No single-bit errors are created rsquo1rsquo = Single-bit errors are forced in the stored data

30 RE RW rsquo1rsquo(2) ECC Read Enable rsquo0rsquo = ECC read logic is bypassed rsquo1rsquo = ECC read logic is enabled

31 WE RW rsquo1rsquo(2) ECC Write Enable rsquo0rsquo = ECC write logic is bypassed rsquo1rsquo = ECC write logic is enabled

Notes 1 This bit is available only if C_INCLUDE_ECC_TEST = 1 and C_DDR_DWIDTH = 322 Reset value is determined by parameter C_ECC_DEFAULT_ON If C_ECC_DEFAULT_ON = 1 then this bit is equal to rsquo1rsquo

If C_ECC_DEFAULT_ON = 0 then this bit is equal to rsquo0rsquo

Discontinued IP

ECC Status Register (ECCSR)Note This register is available only when C_INCLUDE_ECC_SUPPORT = 1 and C_ENABLE_ECC_REG = 1 and C_DDR_DWIDTH = 32

The ECC Status Register is illustrated in Figure 2 Table 6 describes the function of each bit in the ECC Status Register

Figure 2 ECC Status Register

DE

darr

0 21 22 28 29 30 31

uarr uarr uarr uarrUnused SE_SYND PE SE

Table 6 ECCSR Bit Definitions

Bit(s) Name Core Access Reset Value Description

0-21 Reserved

22-28 SE_SYND RROW(1) 0000000 Single-bit Error Syndrome Indicates the ECC syndrome value of the most recent memory transaction in which a single-bit error was detected The 7-bit syndrome value indicates the data bit position in which an error was detected and corrected

29 PE RROW(1) rsquo0rsquo Parity Field Bit Error During a memory transaction an error was detected in a parity field bit rsquo0rsquo = No parity field bit errors detected rsquo1rsquo = Parity field bit error detected and corrected

30 DE RROW(1) rsquo0rsquo Double-Bit Error During a memory transaction a double-bit error was detected and is not correctable rsquo0rsquo = No double-bit errors were detected rsquo1rsquo = Double-bit error was detected

31 SE RROW(1) rsquo0rsquo Single-Bit Error During memory transaction a single-bit error was detected and corrected rsquo0rsquo = No single-bit errors were detected rsquo1rsquo = Single-bit error detected and corrected

Notes 1 ROW = Reset On Write Any write operation to the ECCSR will reset the register

ECC Single-Bit Error Count Register (ECCSEC)Note This register is available only when C_INCLUDE_ECC_SUPPORT = 1 and C_ENABLE_ECC_REG = 1 and C_DDR_DWIDTH = 32

The ECC Single-bit Error Count register records the number of ECC single-bit errors that occurred during the memory transaction as shown in Table 7 ECC logic will correct the detected single-bit errors When the value in this register reaches 4095 (the max count) the next single-bit error detected will reset the register to 0 This count consumes 12-bits as shown in Figure 3

Discontinued IP

Figure 3 ECCSEC Register

0 19 20 31

uarr uarrUnused SEC

Table 7 ECCSEC Bit Definitions

0-19 Reserved

20-31 SEC RROW(1) 0 Single-Bit Error Count Indicates the number of single-bit errors that occurred during the pervious memory transactions The maximum error count is 4095

Notes 1 ROW = Reset On Write Any write operation to the ECCSEC register will reset the register

ECC Double-Bit Error Count Register (ECCDEC)Note This register is available only when C_INCLUDE_ECC_SUPPORT = 1 and C_ENABLE_ECC_REG = 1 and C_DDR_DWIDTH = 32

The ECC Double-bit Error Count register as shown in Figure 4 records the number of ECC double-bit errors that occurred during the memory transaction shown in Table 8 ECC cannot correct double-bit errors detected When the value in this register reaches 4095 (the max count) the next double-bit error detected will reset the register to 0

Figure 4 ECCDEC Register

0 19 20 31

uarr uarrUnused DEC

Table 8 ECCDEC Bit Definitions

0-19 Reserved

20-31 DEC RROW(1) 0 Double-Bit Error Count Indicates the number of double-bit errors that occurred during the pervious memory transactions The maximum error count is 4095

Notes 1 ROW = Reset On Write Any write operation to the ECCDEC register will reset the register

ECC Parity Field Bit Error Count Register (ECCPEC)Note This register is available only when C_INCLUDE_ECC_SUPPORT = 1 C_ENABLE_ECC_REG = 1 and C_DDR_DWIDTH = 32

Discontinued IP

The ECC Parity field bit Error Count register as shown in Figure 5 records the number of bit errors that occurred in the ECC parity field during the memory transaction shown in Table 9 ECC logic will correct detected parity field bit errors When the value in this register reaches 4095 (the max count) the next parity field bit error detected will reset the register

Figure 5 ECCPEC Register

0 19 20 31

uarr uarrUnused PEC

Table 9 ECCPEC Register Bit Definitions

0-19 Reserved

20-31 PEC RROW(1) 0 Parity Field Bit Error Count Indicates the number of errors that occurred in the parity field bits during the last memory transactions The maximum error count is 4095

Notes 1 ROW = Reset On Write Any write operation to the ECCPEC register will reset the register

ECC Interrupt DescriptionsNote The interrupts described here are only available if C_INCLUDE_ECC_SUPPORT = 1 C_ENABLE_ECC_REG = 1 and C_INCLUDE_ECC_INTR = 1 and C_DDR_DWIDTH = 32

The ECC module has 3 distinct interrupts that are sent to the IPIF The IPIF utilizes the IP Interrupt Service Controller (IPISC) and allows each interrupt to be enabled independently (via the Interrupt Enable Register (IPIER))

Device Global Interrupt Enable Register (DGIE)The Device Global Interrupt Enable register is used to globally enable the final interrupt output from the IPIF interrupt service as shown in Figure 6 and described in Table 10

Figure 6 DGIE Register

0 31

uarr uarrGIE Unused

Discontinued IP

Table 10 DGIE Register Description

0 GIE RW rsquo0rsquo Global Interrupt Enable rsquo0rsquo = Interrupts disabled rsquo1rsquo = Interrupts enabled

1-31 Read zeros Unused

IP Interrupt Status Register (IPISR)Note This register is available only when C_INCLUDE_ECC_SUPPORT = 1 C_INCLUDE_ECC_INTR = 1 and C_DDR_DWIDTH = 32

The IP Interrupt Status Register is the interrupt capture register for the ECC logic as shown in Figure 7 and described in Table 11

Figure 7 IPISR Register

DE_ISdarr

0 28 29 30 31

uarr uarr uarrUnused PE_IS SE_IS

Table 11 IPISR Description

Bit(s) NameCore

0-28 Reserved

29 PE_IS RTOW(1) rsquo0rsquo Parity Field Bit Error Interrupt Status Indicates a parity field bit error has occurred during the memory data transaction In the ECC module parity field bit errors will be corrected as data is read from memory This interrupt is for system monitoring only and does not indicate corrupt data rsquo0rsquo = Disabled rsquo1rsquo = Enabled

30 DE_IS RTOW(1) rsquo0rsquo Double-Bit Error Interrupt Status Indicates a double-bit data error has occurred during the memory transaction In the ECC module double-bit errors can be detected but not corrected When this interrupt is asserted the data read from memory is not valid rsquo0rsquo = Disabled rsquo1rsquo = Enabled

31 SE_IS RTOW(1) rsquo0rsquo Single-Bit Error Interrupt Status Indicates a single-bit error has been detected during the memory transaction In the ECC module single-bit errors will be detected and corrected This interrupt is for system monitoring only and does not indicate corrupt data rsquo0rsquo = Disabled rsquo1rsquo = Enabled

Notes 1 TOW is Toggle On Write Writing a rsquo1rsquo to a bit position within the register causes the corresponding bit position in the register to toggle

Discontinued IP

IP Interrupt Enable Register (IPIER)Note This register is available only when C_INCLUDE_ECC_SUPPORT = 1 and C_ENABLE_ECC_REG = 1 and C_INCLUDE_ECC_INTR = 1 and C_DDR_DWIDTH = 32

The IP Interrupt Enable Register has an enable bit for each defined bit of the IP Interrupt Status register as shown in Figure 8 and described in Table 12

Figure 8 IPIER Register

DE_IEdarr

0 28 29 30 31

uarr uarr uarrUnused PE_IE SE_IE

Table 12 IPIER Description

Bit(s) NameCore

0-28 Reserved

29 PE_IE RW rsquo0rsquo Parity Field Bit Error Interrupt Enable Enables assertion of the interrupt for indicating parity field bit errors have occurred rsquo0rsquo = Disabled rsquo1rsquo = Enabled

30 DE_IE RW rsquo0rsquo Double-bit Error Interrupt Enable Enables assertion of the interrupt for indi-cating double-bit data errors have occurred rsquo0rsquo = Disabled rsquo1rsquo = Enabled

31 SE_IE RW rsquo0rsquo Single-bit Error Interrupt Enable Enables assertion of the interrupt for indicat-ing single-bit data errors have occurred rsquo0rsquo = Disabled rsquo1rsquo = Enabled

Discontinued IP

Connecting to MemoryBig-Endian Memory Data Types and OrganizationDDR2 SDRAM can be accessed as byte (8 bits) halfword (2 bytes) word (4 bytes) or double word (8 bytes) depending on the size of the bus to which the processor is attached Data to and from the PLB is organized as big-endian The bit and byte labeling for the big-endian data types is shown below in Figure 9

Figure 9 Big-Endian Memory Data Types

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Memory to PLB DDR2 SDRAM Controller ConnectionsThe data and address signals at the PLB DDR2 SDRAM controller are labeled with big-endian bit labeling (for example D(031) D(0) is the MSB) whereas most memory devices are either endian agnostic (they can be connected in either way) or little-endian D(310) with D(31) as the MSB

Caution must be exercised with the connections to the external memory devices to avoid incorrect data and address connections

Table 13 shows the correct mapping of PLB DDR2 SDRAM controller pins to the memory device pins for 32-bit data width Figure 10shows the interconnection between the PLB DDR2 SDRAM controller and the DDR2 SDRAM for 32-bit data width

Discontinued IP

Table 13 PLB DDR2 SDRAM controller interconnect to 32-bit Data width DDR2 SDRAM

Description DDR2 SDRAM Controller Signal [MSBLSB] DDR2 SDRAM Signal [MSBLSB]

Data Bus DDR_DQ[0C_DDR_DWIDTH - 1] DQ[C_DDR_DWIDTH - 10]

Bank Address DDR_BankAddr[0C_DDR_BANK_AWIDTH - 1] BA[C_DDR_BANK_AWIDTH - 10]

Address DDR_Addr[0C_DDR_AWIDTH - 1] A[C_DDR_AWIDTH - 10]

Data Strobe DDR_DQS[0C_DDR_DWIDTH8 - 1] UDQS LDQS

Differential Data Strobe

DDR_DQSn[0C_DDR_DWIDTH8 - 1] UDQS LDQS

Data Mask DDR_DM[0C_DDR_DWIDTH8 - 1] UDM LDM

ECC Check Bits DDR_DQ_ECC[0C_NUM_ECC_BITS - 1] DQ_ECC[C_NUM_ECC_BITS - 10]

ECC Data Strobe DDR_DQS_ECC DQS_ECC

Differential ECC Data Strobe

DDR_DQSn_ECC DQSn_ECC

ECC Data Mask DDR_DM_ECC DM_ECC

ExampleFigure 10 illustrates an example of connecting memory to the PLB DDR2 SDRAM controller design The example shown here has the following specified parametersbull C_INCLUDE_ECC_SUPPORT = 1bull C_NUM_BANKS_MEM = 1bull C_DDR_DWIDTH = 32bull C_NUM_ECC_BITS = 7bull C_DDR_BANK_AWIDTH = 2bull C_DDR_AWIDTH = 13bull C_DDR_ENABLE_DIFF_DQS = 0

Discontinued IP

Figure 10 PLB DDR2 SDRAM Controller Connection Example to 32-bit DDR2 SDRAM

DDR_DQ(015)DDR_DQS(01)

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR2 SDRAM Controller

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

DQ(80)UnusedLDQSUnusedLDMUnused

Table 14 shows the correct mapping of PLB DDR2 SDRAM controller pins to memory device pins for 64-bit data width Figure 11shows the interconnection between PLB DDR2 SDRAM controller and DDR2 SDRAM for 64-bit data width

Table 14 PLB DDR2 SDRAM controller interconnect to 64-bit DDR2 SDRAM

DescriptionPLB DDR2 SDRAM Controller Signal

[MSBLSB] DDR2 SDRAM Signal [MSBLSB]

Data Strobe DDR_DQS[0C_DDR_DWIDTH8 - 1] DQS[C_DDR_DWIDTH8 - 10]

DDR_DQSn[0C_DDR_DWIDTH8 - 1] DQSn[C_DDR_DWIDTH8 - 10]

Data Mask DDR_DM[0C_DDR_DWIDTH8 - 1] DM[C_DDR_DWIDTH8 -10]

Discontinued IP

ExampleFigure 11 illustrates an example of connecting memory to the PLB DDR2 SDRAM controller for 64-bit DDR2 SDRAM The example shown here has the following specified parametersbull C_INCLUDE_ECC_SUPPORT = 0bull C_NUM_BANKS_MEM = 1bull C_DDR_DWIDTH = 64bull C_DDR_BANK_AWIDTH = 3bull C_DDR_AWIDTH = 13bull C_DDR_ENABLE_DIFF_DQS = 1

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

PLB DDR2 SDRAM ControllerDQSn(30)

DDR_DQSn(03)

DDR_DQSn(47)DQSn(30)

DDR2 SDRAM Address MappingAn address offset is calculated based on the width of the DDR2 SDRAM data bus The DDR2 SDRAM column address is then mapped to the PLB address bus followed by the row address and bank address

The PLB address bus bit locations for the DDR2 SDRAM column row and bank addresses are calculated as shown in Table 15 and Table 16

Table 15 DDR2 SDRAM Address Offset Calculations

Variable Equation

ADDR_OFFSET log2(C_DDR_DWIDTH8)

COLADDR_STARTBIT C_PLB_AWIDTH - (C_DDR_COL_AWIDTH + ADDR_OFFSET)

COLADDR_ENDBIT COLADDR_STARTBIT + C_DDR_COL_AWIDTH - 1

ROWADDR_STARTBIT COLADDR_STARTBIT - C_DDR_AWIDTH

Discontinued IP

Table 17 and Table 18 show an example of the mapping between the PLB address and the DDR2 SDRAM address In this example the data width of the DDR2 SDRAM is 32 the data width of the PLB address bus is 64 the DDR2 SDRAM column address width is 9 the DDR2 SDRAM row address width is 13 and the DDR2 SDRAM bank address width is 2

Table 17 DDR2 SDRAM Address Offset Calculation For C_DDR_DWIDTH = 32 And C_DDR_BANK_AWIDTH = 2

Variable Equation Value

ADDR_OFFSET log2(C_DDR_DWIDTH8) log2(328) = 2

32 - (9 + 2) = 21

COLADDR_ENDBIT COLADDR_STARTBIT + C_DDR_COL_AWIDTH - 1 21 + (9 - 1) = 29

ROWADDR_STARTBIT COLADDR_STARTBIT - C_DDR_AWIDTH 21 - 13 = 8

ROWADDR_ENDBIT ROWADDR_STARTBIT + C_DDR_AWIDTH - 1 8 + 13 - 1 = 20

BANKADDR_STARTBIT ROWADDR_STARTBIT - C_DDR_BANK_AWIDTH 8 - 2 = 6

BANKADDR_ENDBIT BANKADDR_STARTBIT + C_DDR_BANK_AWIDTH - 1 6 + 2 - 1 = 7

Table 18 DDR2 SDRAM - PLB Address Bus Assignment For C_DDR_DWIDTH = 32 And C_DDR_BANK_AWIDTH = 2

DDR2 SDRAM Address PLB Address Bus

Column Address PLB_ABus(2128) amp rsquo0rsquo

Row Address PLB_ABus(820)

Bank Address PLB_ABus(67)

ROWADDR_ENDBIT ROWADDR_STARTBIT + C_DDR_AWIDTH - 1

BANKADDR_STARTBIT ROWADDR_STARTBIT - C_DDR_BANK_AWIDTH

BANKADDR_ENDBIT BANKADDR_STARTBIT + C_DDR_BANK_AWIDTH - 1

Table 16 DDR2 SDRAM - PLB Address Bus Assignments

Column Address PLB_ABus(COLADDR_STARTBIT to COLADDR_ENDBIT)

Row Address PLB_ABus(ROWADDR_STARTBIT to ROWADDR_ENDBIT)

Bank Address PLB_ABus(BANKADDR_STARTBIT to BANKADDR_ENDBIT)

Table 15 DDR2 SDRAM Address Offset Calculations (Continued)

Variable Equation

Discontinued IP

Table 19 and Table 20 show an example of the mapping between the PLB address and the DDR2 SDRAM address when the data width of the DDR2 SDRAM is 64 the data width of the PLB is 64 the column address width is 8 the row address width is 13 and the bank address width is 3

32 - (8 + 3) = 21

Column Address PLB_ABus(2128)

IMPORTANT Virtex-4 and Virtex-II Pro IO pairs share input and output clock signals Since the DDR registers in the IO blocks use both of the input and output clock signals the ports assigned to the IO pairs must use the same input and output clocks Care should be taken when making port IO assignments The DDR_DQ and DDR_DM signals use the system clock as the output clock and the DDR_DQS signals use a 90 degree phase shift of the system clock as the output clock Therefore a DDR_DQS signal should not be assigned with a DDR_DQ signal or a DDR_DM signal in an IO pair

Note This PLB DDR2 SDRAM controller design utilizes the DDR registers in the FGPA IO blocks and must be targeted to FPGA families that support this feature

The DDR_DQ and DDR_DQS buses are 3-stateable the user should pullup these signals in the FPGA IO blocks or external to the FPGA in the board design Note that the PLB DDR2 SDRAM controller design will drive the DQS signals to a high value lsquo1rsquo during the IDLE state so only one PLB DDR2 SDRAM controller can be used to control a DDR2 SDRAM ie two PLB DDR2 SDRAM controllers can-not share the same DDR2 SDRAM

Discontinued IP

PLB DDR2 SDRAM Controller DesignThe block diagram for the PLB DDR2 SDRAM controller is shown in Figure 12 The PLB DDR2 SDRAM controller consists of the PLB IPIF and the DDR2 SDRAM controller The PLB IPIF provides the bus protocol interface The DDR2 SDRAM controller provides the DDR2 SDRAM interface including the control state machines initialization logic and IO registers

The separation of the Command State Machine and the Data State Machine allows for the application of commands to the DDR2 SDRAM while data receptiontransmission is in progress Overlapping the DDR2 SDRAM commands with the data transfer when accessing data in the same row of the same bank allows for more optimal DDR2 SDRAM operation

The PLB DDR2 SDRAM controller consists of1 The PLB IPIF module provides the interface between the PLB connections and DDR2 SDRAM controller2 The ECC module creates the ECC check bits that are stored in memory with bus data The ECC module (during a read cycle) will

detect single and double-bit errors and only correct single-bit errors The ECC module is only instantiated when C_INCLUDE_ECC_SUPPORT = 1

3 The Init state machine module issues the initialization sequence of commands to the DDR2 SDRAM upon power up or self refresh4 The Command State Machine issues commands (readwrite auto refresh precharge etc) to the DDR2 SDRAM after the completion

of the initialization sequence5 The Data State Machine controls the flow of data to and from the DDR2 SDRAM6 The Write Async FIFO module separates the DDR2 SDRAM clock domain from the PLB clock domain to operate the PLB DDR2

SDRAM controller with two independent frequencies7 FIFO Read Control module is responsible to generates the read enable signal to the Async FIFO used in the Write Async FIFO

module8 The IO Reg module uses DDR IO registers to send the data on both edges of DDR2 SDRAM clock during writing to DDR2

SDRAM and to capture the data on both edges of internal FPGA clock during reading from the DDR2 SDRAM9 The Reg Unreg module registers the commands issued to the DDR2 SDRAM when the parameter C_REG_DIMM = 110 The Read Data Path module stores the data captured from IO Reg module in to an asynchronous FIFO and transfers the same to

PLB11 The Counters module incorporates logic to count various DDR2 SDRAM timing parameters and enable the Command State

Machine to issue commands at the end of the count12 The Clock Generator module generates the complemented clocks (DDR_Clk amp DDR_Clkn) to the DDR2 SDRAM13 The Multiple Data Width module is instantiated when the data width of the DDR memory is equal to or greater than the data width

of the PLB In this controller the Multiple Data Width module will be instantiated when the C_DDR_DWIDTH = 64

14 The Tap Control amp Data Tap Increment modules calibrate the IDELAY (pulse center taps required to center align the data with respect to internal FPGA clock) for Virtex-4 devices The Tap Control module calculates the pulse center taps and then the Data Tap Increment module calibrates the IDELAY

15 The IDELAYCTRL module(s) are specific to Virtex-4 devices The IDELAYCTRL module requires a 200 MHz clock and controls the tap value of the IDELAY modules instantiated in the IO Reg module

Discontinued IP

Figure 12 PLB DDR2 SDRAM Controller Block Diagram

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

Clk_DDR_Rddata Clk_DDR_Rddata_n3

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Note 1 Included only when C_INCLUDE_ECC_SUPPORT = 1 and C_DDR_DWIDTH = 32Note 2 Included only when C_FAMILY = Virtex-4Note 3 Included only when C_FAMILY = not Virtex-4

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

TAP Control2Calib Done

DDR_ReadDQS_RiseDDR_ReadDQS_ECC_Rise

Valid tap count amp idelay

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Error Correction Code (ECC)The DDR2 SDRAM controller design utilizes ECC only with the following parameter settingsbull C_INCLUDE_ECC_SUPPORT = 1bull C_DDR_DWIDTH = 32

ECC detects both single-bit and double-bit errors and corrects single-bit errors This ECC logic can be enabled or disabled using the parameters provided in Table 1 Figure 13 illustrates the control and data signals intercepted by the ECC logic from the IPIC to the IPIF Interface of the DDR2 SDRAM controller logic

Figure 13 ECC Logic Block Diagram

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC Write Logic ECC Read Logic ECC Registers

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

MuxECC Byte amp HalfWord (BHW) Logic

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

bhw2bus_AddrAckbhw2bus_WrAckbhw2bus_RdAckbhw2bus_Data

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_RdReqbhw2ecc_RNW

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

A level of muxing is created when using ECC on these signals to enable or disable the use of ECC read or ECC write logic The byte and halfword logic shown in Figure 13 is utilized during an active byte or halfword write operation when ECC write logic is enabled With the ECC check bit data generated and stored for each 32-bits of DDR2 SDRAM data a read-modify-write operation is

Discontinued IP

required for any PLB byte or halfword write request to DDR2 SDRAM The byte or halfword data to write is muxed with the 32-bit word after reading from the corresponding memory location The new 32-bit data word is then presented to the ECC write logic and the ECC check bits are re-created for the memory write

In a write cycle the ECC logic will pipeline WrReq to the DDR2 SDRAM Command State Machine until the ECC check bit data is ready to write to memory Additional latency should be expected on any byte or halfword write transaction when ECC write logic is enabled

During a memory read the ECC check bits read from memory IP2ECC_Chk_Bits are compared with the check bits calculated on the data word read The result of this comparison is stored in the syndrome and indicates the data bit or parity field bit error Table 21 illus-trates the error type decoding based on the syndrome

Table 21 ECC Error Decoding

Syndrome (MSB)

Syndrome(MSB-10) Result

0 = 0 No errors in memory read

1 ne 0 Single-bit error Syndrome holds bit position to correct

If the Syndrome(MSB-10) has a single-bit = lsquo1rsquo then a parity field bit error is detected and Syndrome(MSB-10) holds the parity field bit to correct

When C_NUM_ECC_BITS = 7 the following values for Syndrome(MSB-10) would rep-resent a parity field bit error

bull 000000bull 000001bull 000010bull 000100bull 001000bull 010000bull 100000

0 ne 0 double-bit error Not correctable

ECC TestingTo enable testing on the ECC core logic C_INCLUDE_ECC_TEST = 1

The ECC Control Register (ECCCR) described in ECC Control Register (ECCCR) includes control bits for enabling or disabling the test logic The following list describes possible forcing errors combinations If any other combination is attempted no errors will be forced on the data written to memorybull No bit error forcingbull Force single-bit data errors (ECC Control Register (ECCCR) FORCE_SE = lsquo1rsquo)bull Force double-bit data errors (ECC Control Register (ECCCR) FORCE_DE = lsquo1rsquo)bull Force parity bit errors (ECC Control Register (ECCCR) FORCE_PE = lsquo1rsquo)bull Force single-bit data and single parity field bit errors (ECC Control Register (ECCCR) FORCE_SE = lsquo1rsquo and FORCE_PE = lsquo1rsquo)

For single-bit error testing a mask shift register forces single-bit errors on the data written to memory The 64-bit mask shift register has the least significant single-bit equal to lsquo1rsquo When testing is enabled during a memory write the shift register clocks the lsquo1rsquo towards to most significant bit

For double-bit error testing a mask shift register forces double-bit errors on the data written to memory The 64-bit mask shift register has two adjacent bits equal to lsquo1rsquo (starting in the two least significant bit positions) and rotates the 11 pattern in the shift register (towards the two most significant bits) on each memory write

Discontinued IP

When parity field bit error testing is enabled a mask shift register (with a size of C_NUM_ECC_BITS 2) forces single-bit errors on the check bits stored in memory The check bit mask shift register has the least significant single-bit equal to lsquo1rsquo and rotates the lsquo1rsquo (towards the most significant bit) on each memory write

Note For all ECC testing conditions PLB DDR2 SDRAM controller supports ECC logic only for 32-bit data width of DDR2 SDRAM and an error might not be forced into memory while writing a 32-bit double word

Init State MachineThe DDR2 SDRAMs must be powered-up and initialized in a predefined manner After power supplies and all the clocks are stable the DDR2 SDRAM requires a 200 us delay prior to applying an executable command

The Init State Machine provides the 200 us delay and the sequencing of the required DDR2 SDRAM start-up commands It instructs the command state machine to send the proper commands in a proper sequence to the DDR2 SDRAM This state machine starts execution after Reset and returns to the IDLE state when Reset is applied When the initialization sequence has been completed the DDR_Init_done signal is asserted

Note that after reset has been applied the 200 us delay is again implemented before any commands are issued to the DDR2 SDRAM

The ENABLE_DLL state in the Init State Machine configures the Extended Mode Register (EMR) and the RESET_DLL state config-ures the Mode Register

Figure 14 DDR2 SDRAM Init State Machine

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL PRECHARGE2 REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

(calib_done and FIFO_rst_done) = 1

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

A simplified version of the Init State Machine is shown in Figure 14

Command State MachineThe Command Sate Machine provides the address bus and commands signals to the DDR2 SDRAM It sends the pending transaction signal to the Data State Machine to start the receptiontransmission of data If a burst transaction is in progress or a secondary transaction has been received the Command State Machine will send the next command to the DDR2 SDRAM while data receptiontransmission is still in progress to optimize the DDR2 SDRAM operation A simplified version of the Command State Machine when open row man-agement is disabled (ie C_USE_OPEN_ROW_MNGT = 0) is shown in Figure 15 For readability only the major state transitions are shown

Discontinued IP

Figure 15 DDR2 SDRAM Command State Machine

Tras_min_end + FIFO_rst_done

Refresh|Trefi_endIDLEIDLE

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

Comb_Bus2IP_CS +GPcnt_end

Comb_Bus2IP_CS +GPcnt_end READ_CAL_CMD

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

Tras_min_end +Trefi_end | CS

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Supporting Open Row ManagementTo enable open row management the design parameter C_USE_OPEN_ROW_MNGT must be set to 1 By setting this parameter the addressable row of memory currently being accessed will remain open for subsequent operations Upon the completion of the current read or write transaction a PRECHARGE command will not be executed to the memory device In not closing the row at the end on the previous transaction the subsequent operation can bypass the ACTIVE command (in conjunction with the READWRITE command) This is only true when the subsequent operation is to access the same addressable row of memory

However if the subsequent operation is to the same addressable row of memory but in a different bank address the ACTIVE command must be issued at the beginning of the read or write operation

Discontinued IP

It is recommended the parameter C_USE_OPEN_ROW_MNGT = 1 when accesses to memory will occur in a sequential manner If the addressable accesses into DDR SDRAM can not be predicted (or will not occur in a sequential manner) then it is suggested the param-eter C_USE_OPEN_ROW_MNGT be set to 0

While the open row management feature improves latency on back to back operations when accessing the same row of addressable memory there is a penalty for crossing row addresses When C_USE_OPEN_ROW_MNGT = 1 on a subsequent operation that requires a different addressable row of memory a PRECHARGE must first be executed to the previously open row prior to completing the pend-ing operation

When C_USE_OPEN_ROW_MNGT = 0 the DDR SDRAM controller will execute a PRECHARGE at the end of read or write trans-action to the current row being accessed in the SDRAM memory This behavior is highlighted by transitioning to the PRECHARGE_CMD state in the Command State Machine (see Command State Machine on page 32)

Open Row Management with Multiple CS Banks of MemoryNote the following behavior when open row management is enabled C_USE_OPEN_ROW_MNGT = 1 and multiple external chip selectable banks of memory are enabled ie C_NUM_BANKS_MEM is greater than 1 If any back to back read or write operations access two different external chip selectable banks of memory the currently access row of memory will be closed ie a PRECHARGE command is issued before accessing a different chip selectable bank of memory

For example if two memory banks (ie C_NUM_BANKS_MEM = 2) are specified as followsbull C_MEM0_BASEADDR = 0x3000_0000bull C_MEM0_HIGHADDR = 0x3FFF_FFFFbull C_MEM1_BASEADDR = 0x4000_0000bull C_MEM1_HIGHADDR = 0x4FFF_FFFF

The external chip selects to DDR memory is DDR_CSn(01) where DDR_CSn(0) is used to access 0x3000_0000 to 0x3FFF_FFFF and DDR_CSn(1) is asserted to access 0x4000_0000 to 0x4FFF_FFFF

If the first operation is accessing address 0x3000_1000 and the subsequent operation is accessing address 0x4000_1000 the row addresses match to allow open row management However since DDR_CSn(0) will negate after the first transaction and DDR_CSn(1) will assert for the second transaction a PRECHARGE must be issued and close the open row for the operation at address 0x3000_1000 Then an ACTIVE command is issued to open the row for the operation at address 0x4000_1000

Discontinued IP

Data State MachineThe Data State Machine is responsible for controlling the flow of data to and from the DDR2 SDRAM The Data State Machine monitors the pend_read or pend_write signals from the Command State Machine to determine if more data transmissions are necessary The Data State Machine waits for C_DDR_CAS_LAT during read operations and asserts the ddr_brst_end signal when the DDR2 SDRAM has completed the data transfer The Data State Machine provides the read_data_en signal to the input DDR registers of an FPGA and Read Data Path FIFO A simplified version of the Data State Machine is shown in Figure 16

Figure 16 DDR2 SDRAM Data State Machine

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

ddr_brst_endpend_read

pend_write

pend_writeddr_brst_end

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Write Async FIFO and FIFO Read controlThis core requires the PLB logic to operate at a separate clock frequency than the DDR2 SDRAM interface The parameter C_DDR_ASYNC_SUPPORT is set to the constant value of 1 to allow the user to separate the system and DDR2 SDRAM clock domains The PLB_Clk is used for writing in to the Async FIFO and the DDR2 SDRAM device_Clk is used for reading the data from the FIFO The logic includes a state machine and an asynchronous FIFO in order to synchronize the command data address data mask and control signals The logic in this module is shown in Figure 17 which includes state machine logic as well as instantiation of multiple asynchronous FIFOs The output of the asynchronous FIFO is then provided in to the IO reg module

The Command FIFO write enable signal (cmd_fifo_wr_en) is asserted when a DDR2 SDRAM command (Active Write Read Refresh Precharge) is issued by the Command State MachineThe control signal dq_oe_cmb enables writing of data and commands to the Data FIFO and Command FIFO respectively Reading of both the Command FIFO and the Data FIFO is controlled by the FIFO Read Control module The FIFO Read Control module monitors the empty flags of Command FIFO and Data FIFO to enable reading each FIFO

Figure 17 Block Diagram of Write Path Asynchronous Logic

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

command_fifo_read_en

Data FIFO

DDR_write_data DDR_write_data_mask

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

RASn CASn WEn CSn BankAdrr Addr Dq_oe_cmb din

wr_en

write_data write_data_mask

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_RASn DDR_CASn DDR_WEn DDR_CSn DDR_BankAdrr DDR_Addr

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

Tap Control and Data Tap IncrementThe Tap Control and Data Tap Increment modules calibrate (shown in Figure 12) are only instantiated when targeting Virtex-4 architec-tures (C_FAMILY = virtex4) Non Virtex-4 implementations do not instantiate these modules The IDELAY module instantiation on all DQ and DQS signals is shown in Figure 20

The Tap Control module issues back to back read cycles to the memory during the initialization sequence During these read cycles the incoming DQS signal(s) are sampled and the midpoint of the pulse is determined

Once the midpointtap value is determined for the DQS signal(s) the Data Tap Increment module also sets the IDELAY tap value of the corresponding DQ data bits to the same value

The IDELAY modules (in the IOB) are calibrated at an incremental value determined by the clock input to the IDELAYCTRL mod-ule(s) In this design a 200 MHz clock is applied to the IDELAYCTRL module(s) which in turn set the time delay of the 64 count tap value

IO Registers

Control SignalsAll control signals and the address bus to the DDR2 SDRAM are registered in the IOBs of the FPGA

Write Data The DDR IO registers are used to output the write data to the DDR2 SDRAM as shown in Figure 18 Since the DDR2 SDRAM clocks (DDR_Clk and DDR_Clkn) are generated from the Clk90 output of the DCM the CLK0 output of the DCM is used to clock out the data so that the DDR2 SDRAM clock is centered on the DDR2 SDRAM data

Discontinued IP

Figure 18 Write Data Path

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

Write_data[0C_DDR_DWIDTH-1]

Write_data[C_DDR_DWIDTH to C_DDR_DWIDTH2-1]

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

CNot included in core logic

Device_Clk

Write_data_mask DDR_DM [i]2

Not included in core logic

Device_Clk_n

Device_Clk90_n

Note 1 Signal Device_Clk Device_Clk_n Device_Clk90 amp Device_Clk90_n are derived from Device_Clk

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Note 2 Signals are duplicated based on the parameter C_DDR_DWIDTH

Discontinued IP

Read Data (Non Virtex-4 Implementation)The DDR IO registers sample the read data from the DDR2 SDRAM as shown in Figure 19 The clock output (DDR_Clk) is used to supply the feedback clock (matching trace lengths) back into the FPGA This feedback clock is fed into a DCM and generates DDR_Clk90_in and DDR_Clk90_in_n These clock signals are used to capture the read data at the IOB during a read cycle as shown in Figure 19

During a read cycle the data strobe signal from the DDR2 SDRAM (DDR_DQS) is registered only on the rising edge of DDR_Clk90_in so that it is always high while the DDR2 SDRAM is transmitting data This signal will be used by the Read Data Path logic as the write enable into a FIFO

Figure 19 DDR2 SDRAM Input Data Registers

D

C0C1

Q0DDR_RdData_high

Q1 DDR_RdData_lowDDR_RdData

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

CENot included in core logic

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

Note1 Similar register logic exists for the ECC signals when C_INCLUDE_ECC_SUPPORT = 1

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Note2 Signals are duplicated based on the parameter C_DDR_DWIDTH

Discontinued IP

Read Data (Virtex-4 Implementation)The IOB IDELAY components and IDDR registers are used to read data from the DDR2 SDRAM as shown in Figure 20 The IDELAY modules are calibrated during the initialization sequence to center align the input DQ and DQS signals to the Device_Clk The calibra-tion determines the appropriate sample time based on Tsu and Th requirements on the IDDR register components

Figure 20 V4 IDDR Register Usage

DDR_DQ_i IDELAY

Data_idelay_ceData_idelay_incData_idelay_rst

dq_idelay_out

Device_Clk

IDDR DDR_ReadData [0 C_DDR_DWIDTH2 - 1]

Cal_Clk

DDR_DQS_i IDELAY

DQS_idelay_ceDQS_idelay_incDQS_idelay_rst

dqs_idelay_out

Device_Clk

IDDR

DDR_ReadDQS_Rise [0 C_DDR_DWIDTH8 - 1]

Cal_ClkDDR_ReadDQS_Fall [0 C_DDR_DWIDTH8 - 1]

Q1

Q2

DDR_DQSn_i IDELAY

DQSn_idelay_ceDQSn_idelay_incDQSn_idelay_rst

dqsn_idelay_out

Device_Clk

IDDR

DDR_ReadDQSn_Rise [0 C_DDR_DWIDTH8 - 1]

Cal_ClkDDR_ReadDQSn_Fall [0 C_DDR_DWIDTH8 - 1]

Q1

Q2

Note 1 DDR_DQSn IOB is only instantiated when C_DDR_ENABLE_DIFF_DQS = 1 2 Similatr IOB logic exists for all ECC signals when C_INCLUDE_ECC_SUPPORT = 1

Discontinued IP

Read Data Path LogicThe read data output from the IOB will be a vector of size C_DDR_DWIDTH 2 when applied as an input to the Read Data Path mod-ule

The Read Data Path logic consists of an asynchronous FIFO in which the DDR2 SDRAM data is written on the rising edge of the Clk_DDR_Rddata (derived from DDR_Clk90_in the DCM CLK90 output from the DDR feedback clock for non Virtex4 implementa-tions) clock and read on the rising edge of PLB clock For Virtex-4 design implementations the FIFO write clock is the rising edge of the Device_Clk the same clock used to capture data in the IOB IDDR register components

The asynchronous FIFO width is C_DDR_DWIDTH 2 Once the FIFO is not empty the data is read from the FIFO and a read acknowledge is generated The asynchronous FIFO of the Read Data Path module is shown in Figure 21

Figure 21 Read Data Path Module for Non Virtex-4 Architecture

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

The asynchronous FIFO of the Read Data Path module for Virtex-4 implementation is shown in Figure 22

Figure 22 Read Data Path module for Virtex-4 Architecture

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DDR_ReadData [0C_DDR_ DWIDTH2-1]

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Multiple data width readwrite module will be instantiated in the design when DDR2 SDRAM is of 64-bit widthDuring a read transaction this logic selects the upper or lower 64-bit data out of 128-bit data returned by the DDR2 SDRAM During a write transaction the logic sends the 64-bit data onto the correct lane of the data to be written into DDR2 SDRAM

On Die Termination (ODT)Termination resistance can be enabled on the DDR2 SDRAM memory devices ODT allows selectable effective resistance (Rtt (eff)) to be enabled or disabled on a per transaction basis

The ODT feature minimizes signal reflections in addition to the termination available in the FPGA IO buffers

The PLB DDR2 Controller signal DDR_ODT allows the controller to independently turn on or off the termination resistance internal to the DDR2 SDRAM

The impedance value of On Die Termination effective resistance (Rtt) can be selected using the parameter C_DDR2_ODT_SETTING described in Table 1 as ldquoODT not selectedrdquo or ODT selected (75Ω or 150Ω ) Rtt values are set during DDR2 SDRAM initialization process using the Extended Mode Register (EMRS1) by the controller based on the parameter setting Figure 23 shows the ODT struc-ture

Discontinued IP

Figure 23 ODT Structure

When C_DDR2_ODT_SETTING = 75

PLB DDR2

Controllerto internal logic

150

Vdd

150

DDR_DQ [0n]DDR_DQS [0n]DDR_DQSn[0n]DDR_DM [0n]

DDR_DQ_ECC [0n]DDR_DQS_ECCDDR_DQSn_ECCDDR_DM_ECC

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

Figure 24 shows the ODT turn-on delay tAOND and turn-off delay tAOFD timing When ODT is enabled it will be active for all mem-ory transactions The ODT pin will be asserted (equal to 1) tAOND before the data is active on the data pins and ODT will be disabled (equal to 0) once tAOFD is met

Figure 24 ODT Timing

tAONDtAOFD

Differential Data StrobeDDR2 SDRAM supports an additional differential data strobe DQSn Differential DQS is enabled by the Initialization State Machine in writing to the Extended Mode Register of the DDR2 SDRAM memory (when C_DDR_ENABLE_DIFF_DQS = 1) If differential strobes are enabled DQS operates the same as in single-ended mode with the addition of DQSn operating as the complement of DQS

Since the DQS signal behavior is source-synchronous during read operations the DDR2 SDRAM will drive both the DQS and DQSn signals if differential DQS is enabled During write operations the PLB DDR2 controller will drive the DQS and DQSn

The DQS and DQSn signals are designed as two independent IO signals to the DDR2 SDRAM a differential IO buffer in the FPGA is not required

DDR2 SDRAM ClockingPLB DDR2 SDRAM ClockingTable 22 shows the clock frequency combinations supported in the PLB DDR2 SDRAM controller for the PLB bus clock and the DDR2 SDRAM

Table 22 Supported Clocking Configurations

C_PLB_CLK_PERIOD_PS C_DDR_CLK_PERIOD_PS

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

Non Virtex-4 Clock GenerationThe clocking scheme required in the FPGA (for design implementations other than Virtex-4) and used by the PLB DDR2 SDRAM con-troller core is shown in Figure 25 or Figure 26

Figure 25 PLB DDR2 SDRAM Non-Virtex-4 Clocking (Option 1)

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_ClkDevice_Clk_n

Device_Clk90_inDevice_Clk90_in_n

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Note 1 This clocking configuration uses local clock inversion for the generation of Device_Clk_n Device_Clk90_in_nand DDR_Clk90_in_n

Note 2 An additional BUFG is used for the PLB_Clk in this configurationNote 3 A total of 5 BUFGs are used in this configuration

PLB DDR2 SDRAMController

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

Note 1 This clocking configuration uses global clock inversion for the generation of Device_Clk_n Device_Clk90_in_n

and DDR_Clk90_in_n

Controller

DDR2 SDRAM Clock Input SynchronizationFor design implementations other than Virtex-4 a DCM is required for the DDR feedback clock DDR_Clk_FB The DCM on the feed-back clock is used to create a clock pair that is center aligned with the DQ signals during a read cycle The DDR_Clk output will need to be connected to the DDR_Clk_fb shown in Figure 25 and Figure 26 as an external board connection The CLK90 output of the DDR_Clk_FB DCM is used by the PLB DDR2 SDRAM core to register the data (DQ) during a read cycle

Due to the variance in board layout and timing on the DDR_DQ amp DDR_DQS signals the phase shifting on the DDR_Clk_FB should be analyzed

Discontinued IP

Virtex-4 Clock GenerationThe clocking scheme required in the FPGA for design implementations targeting Virtex-4 used by the PLB DDR2 SDRAM controller core is shown in Figure 27 or Figure 28

Figure 27 PLB DDR2 SDRAM Virtex-4 Clocking (Option 1)

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

Note 1 This clocking configuration uses local clock inversion for the generation of Device_Clk_n amp Device_Clk90_in_nNote 2 An additional BUFG is used for the PLB_Clk in this configurationNote 3 A total of 5 BUFGs are used in this configuration

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Note 1 This clocking configuration uses global clock inversion for the generation of Device_Clk_n amp Device_Clk90_in_nNote 2 An additional BUFG is used for the PLB_Clk in this configurationNote 3 A total of 7 BUFGs are used in this configuration

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

200 MHz Clk PLB DDR2 SDRAMController

IDELAYCTRL

Ref_Clk

Controller Clock InputsA DCM is required to generate the clocks used by PLB DDR2 SDRAM controller as shown in Figure 25 through Figure 28 A 90 degree and 270 degree phase shifted output of the DCM is a required input to the PLB DDR2 SDRAM controller core These are used to gen-erate the DDR_ClkDDR_Clkn and DQS signals to DDR2 SDRAM The inverted clock can be derived using local inversion (to mini-mize BUFG system resource usage) or use direct outputs of the DCM

DDR2 Clock GenerationThe clock output to the DDR2 SDRAM is generated using the DDR IOB registers as shown in Figure 29 The Device_Clk90_in is used to generate the DDR_Clk (and DDR_Clkn) so that the clock is centered on the DQ signal to the DDR2 SDRAM

Discontinued IP

Figure 29 DDR2 SDRAM Clock Generation

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Note 1 Duplicated based on parameter C_NUM_CLK_PAIRS

Discontinued IP

Timing DiagramsThe following diagrams illustrate the relationship between the PLB signals and the DDR2 SDRAM signals for various transactions

Figure 30 illustrates the timing relationship for a Single PLB doubleword write to a 32-bit DDR2 SDRAM memory with parameter C_INCLUDE_ECC_SUPPORT = 1

Figure 30 Single PLB Doubleword Write to a 32-Bit DDR2 SDRAM Memory

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

NOPNOP ACT NOP WRITE NOP PC

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

RA(x)=Row Address CA(x)=Column AddressBA(x)=Bank Address PC=Precharge

Discontinued IP

Figure 31 illustrates the timing relationship for a single PLB doubleword read to a 32-bit DDR2 SDRAM memory with parameter C_INCLUDE_ECC_SUPPORT = 1

Figure 31 Single PLB Doubleword Read to a 32-Bit DDR2 SDRAM Memory

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

NOPNOP ACT NOPREAD NOP PC

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Figure 32 illustrates the timing relationship for a PLB burst of two doubleword write to a 64-bit DDR2 SDRAM memory

Figure 32 PLB Burst of Two Doubleword Write to a 64-Bit DDR2 SDRAM Memory

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

NOPNOP ACT NOP WRITE NOP WRITE NOP PC

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Figure 33 PLB Burst of Two Doubleword Read to a 64-Bit DDR2 SDRAM Memory

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

NOPNOP ACT NOP READ NOP READ NOP PC

1FFF

F

f f f f

Figure 33 illustrates the timing relationship for a PLB burst of two doubleword read to a 64-bit DDR2 SDRAM memory

Design ConstraintsTiming ConstraintsFor complete timing coverage all clock inputs to the FPGA should be assigned a timing constraint All proper timing constraints for the PLB DDR2 SDRAM controller will be drived by the ISE tool for any of the recommended DCM configurations (for design implemen-tations other than Virtex4) shown in Figure 25 or Figure 26 For design implementations other than Virtex-4 a timing constraint should be placed on the system clock input as well as the DDR clock feedback An example for running the PLB at 100 MHz and the DDR2 SDRAM clock at 133 MHz is shown in Figure 34

Figure 34 Non Virtex-4 Timing Constraints

NET PLB_Clk TNM_NET = PLB_ClkTIMESPEC TS_PLB_Clk = PERIOD PLB_Clk 10 ns HIGH 50

NET Device_Clk TNM_NET = Device_ClkTIMESPEC TS_Device_Clk = PERIOD Device_Clk 75 ns HIGH 50

NET DDR_Clk_fb TNM_NET = DDR_Clk_fbTIMESPEC TS_DDR_Clk_fb = PERIOD DDR_Clk_fb 75 ns HIGH 50

Discontinued IP

For Virtex-4 design implementation using the recommended DCM setup shown in Figure 27 or Figure 28 only the external clock inputs are required to be assigned a timing constraint An example for a Virtex-4 implementations is shown in Figure 35 where the PLB clock is running at 100 MHz and the DDR2 SDRAM clock frequency is 133 MHz

Figure 35 Virtex-4 Timing Constraints

NET Clk_200 TNM_NET = Clk_200TIMESPEC TS_Clk_200 = PERIOD Clk_200 5 ns HIGH 50

Pin ConstraintsThe DDR2 SDRAM IO signals should be set to the SSTL_18 IO standard If external pullup or pull down termination is not available on the DDR2 SDRAM DQ or DQS signals then these pins should be specified to use either pullup or pulldown resistors Pulldown resis-tors are preferred An example is shown in Figure 36

Figure 36 PLB DDR2 SDRAM Controllerrsquos Pin Constraints

NET DDR_Clk IOSTANDARD = SSTL18_INET DDR_Clkn IOSTANDARD = SSTL18_INET DDR_CKE IOSTANDARD = SSTL18_INET DDR_CSn IOSTANDARD = SSTL18_INET DDR_RASn IOSTANDARD = SSTL18_INET DDR_CASn IOSTANDARD = SSTL18_INET DDR_WEn IOSTANDARD = SSTL18_INET DDR_DMltgt IOSTANDARD = SSTL18_INET DDR_BankAddrltgt IOSTANDARD = SSTL18_INET DDR_Addrltgt IOSTANDARD = SSTL18_INET DDR_DQltgt IOSTANDARD = SSTL18_IINET DDR_DQSltgt IOSTANDARD = SSTL18_IINET DDR_DQSnltgt IOSTANDARD = SSTL18_IINET DDR_DM_ECC IOSTANDARD = SSTL18_INET DDR_DQ_ECCltgt IOSTANDARD = SSTL18_IINET DDR_DQS_ECC IOSTANDARD = SSTL18_IINET DDR_DQSn_ECC IOSTANDARD = SSTL18_IINET DDR_Odt IOSTANDARD = SSTL18_I

IDELAY ConstraintsFor Virtex-4 design implementations the use of the IDELAY in the DDR2 SDRAM IOB modules is required When using any IDELAY component within the FPGA an IDELAYCTRL module is necessary The IDELAYCTRL module provides the necessary tap increments for each IDELAY module to which it is associated

In the ISE tools if only one IDELAYCTRL module is instantiated and the DDR2 SDRAM signal pin assignments are across multiple clock regions the tools will replicate the IDELAYCTRL module To prevent the tools from duplicating the IDELAYCTRL to all loca-tions on the FPGA the user must specify how many IDELAYCTRL modules are needed This is specified with the C_NUM_IDELAYCTRL design parameter It is the responsibility of the designer to location constrain each IDELAYCTRL based on the clock regions where DDR2 SDRAM IOB signals reside

For instance if C_NUM_IDELAYCTRL = 4 then the user must add UCF constraints to location constrain these modules as shown in Figure 37

Figure 37 Virtex-4 IDELAY Constraints

INST plb_ddr2_0IDELAYCTRL_I0 LOC=IDELAYCTRL_XnYm INST plb_ddr2_0IDELAYCTRL_I1 LOC=IDELAYCTRL_XnYm INST plb_ddr2_0IDELAYCTRL_I2 LOC=IDELAYCTRL_XnYm INST plb_ddr2_0IDELAYCTRL_I3 LOC=IDELAYCTRL_XnYm

Discontinued IP

Design ImplementationTarget TechnologyThe intended target technology is a Virtex-II Pro and Virtex-4 family FPGAs

Device Utilization and Performance BenchmarksThe PLB DDR2 SDRAM controller is a module that will be used with other design modules in the FPGA The utilization and timing numbers reported in this section are estimates Following estimates are calculated by setting C_PLB_CLK_PERIOD_PS = 10000 and C_DDR_CLK_PERIOD_PS = 5000 As the PLB DDR2 SDRAM controller is combined with other cores the utilization of FPGA resources and timing of the PLB DDR2 SDRAM controller design will vary from the results reported here

The PLB DDR2 SDRAM controller benchmarks are shown in Table 23 and Table 24 for Virtex-II Pro (XC2VP20) and Virtex-4 (XC4VLX25) FPGAsDiscontinued IP

Table 23 Performance and Resource Utilization Benchmarks (Virtex-II Pro)

Parameter Values(other parameters at default values) Device Resources fMAX (MHz)

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Notes 1 These benchmark designs contain only the PLB DDR2 SDRAM controller without any additional logic Benchmark numbers approach the

performance ceiling rather than representing performance under typical user conditions

Discontinued IP

Table 24 Performance and Resource Utilization Benchmarks (Virtex-4)

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Specification Exceptions1 Additive latency feature of DDR2 SDRAM is not supported Additive latency of DDR2 SDRAM is set to zero which causes read

latencies of the DDR2 SDRAM to be the same as its CAS latency2 Off Chip Driver (OCD) calibration of DDR2 SDRAM is not supported

Discontinued IP

Reference DocumentsThe following documents contain reference information important to understanding the PLB DDR2 SDRAM controller design1 JEDECrsquos DDR2 SDRAM specification JESD79-2A2 IBM PLB Specification Rev 353 PLB IPIF (v100f) Design Specification (DS458)

Revision History

Date Version Revision

032206 10 Initial release

Discontinued IP

- Introduction
- Features
- PLB DDR2 SDRAM Controller Design Parameters
- - Allowable Parameter Combinations
  - - PLB DDR2 SDRAM Controller IO Signals
    - Parameter-Port Dependencies
    - DDR2 ECC Register Descriptions
    - - ECC Control Register (ECCCR)
      - ECC Status Register (ECCSR)
      - ECC Single-Bit Error Count Register (ECCSEC)
      - ECC Double-Bit Error Count Register (ECCDEC)
      - ECC Parity Field Bit Error Count Register (ECCPEC)
      - ECC Interrupt Descriptions
      - Device Global Interrupt Enable Register (DGIE)
        
        IP Interrupt Status Register (IPISR)
        
        IP Interrupt Enable Register (IPIER)
        
        Connecting to Memory
        
        Big-Endian Memory Data Types and Organization
        
        Memory to PLB DDR2 SDRAM Controller Connections
        
        Example
        
        DDR2 SDRAM Address Mapping
        
        PLB DDR2 SDRAM Controller Design
        
        ECC Testing
        
        Init State Machine
        
        Command State Machine
        
        Supporting Open Row Management
        
        Open Row Management with Multiple CS Banks of Memory
        
        Data State Machine
        
        Write Async FIFO and FIFO Read control
        
        Tap Control and Data Tap Increment
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        Read Data (Non Virtex-4 Implementation)
        
        Read Data (Virtex-4 Implementation)
        
        Read Data Path Logic
        
        
        Multiple Data Width
        
        On Die Termination (ODT)
        
        
        DDR2 SDRAM Clocking
        
        PLB DDR2 SDRAM Clocking
        
        Non Virtex-4 Clock Generation
        
        DDR2 SDRAM Clock Input Synchronization
        
        Virtex-4 Clock Generation
        
        Controller Clock Inputs
        
        DDR2 Clock Generation
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        Design Implementation
        
        Target Technology
        
        Device Utilization and Performance Benchmarks
        
        Specification Exceptions
        
        Reference Documents
        
        Revision History
        
        ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedJobOptions true DSCReportingLevel 0 SyntheticBoldness 100 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveEPSInfo true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputCondition () PDFXRegistryName (httpwwwcolororg) PDFXTrapped Unknown Description ltlt FRA ltFEFF004f007000740069006f006e00730020007000650072006d0065007400740061006e007400200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000500044004600200064006f007400e900730020006400270075006e00650020007200e90073006f006c007500740069006f006e002000e9006c0065007600e9006500200070006f0075007200200075006e00650020007100750061006c0069007400e90020006400270069006d007000720065007300730069006f006e00200061006d00e9006c0069006f007200e90065002e00200049006c002000650073007400200070006f0073007300690062006c0065002000640027006f00750076007200690072002000630065007300200064006f00630075006d0065006e007400730020005000440046002000640061006e00730020004100630072006f0062006100740020006500740020005200650061006400650072002c002000760065007200730069006f006e002000200035002e00300020006f007500200075006c007400e9007200690065007500720065002egt ENU (Use these settings to create PDF documents with higher image resolution for improved printing quality The PDF documents can be opened with Acrobat and Reader 50 and later) JPN ltFEFF3053306e8a2d5b9a306f30019ad889e350cf5ea6753b50cf3092542b308000200050004400460020658766f830924f5c62103059308b3068304d306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e305930023053306e8a2d5b9a30674f5c62103057305f00200050004400460020658766f8306f0020004100630072006f0062006100740020304a30883073002000520065006100640065007200200035002e003000204ee5964d30678868793a3067304d307e30593002gt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e0020005000440046002d0044006f006b0075006d0065006e00740065006e0020006d00690074002000650069006e006500720020006800f60068006500720065006e002000420069006c0064006100750066006c00f600730075006e0067002c00200075006d002000650069006e0065002000760065007200620065007300730065007200740065002000420069006c0064007100750061006c0069007400e400740020007a0075002000650072007a00690065006c0065006e002e00200044006900650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f0062006100740020006f0064006500720020006d00690074002000640065006d002000520065006100640065007200200035002e003000200075006e00640020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt PTB ltFEFF005500740069006c0069007a006500200065007300740061007300200063006f006e00660069006700750072006100e700f5006500730020007000610072006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000500044004600200063006f006d00200075006d00610020007200650073006f006c007500e700e3006f00200064006500200069006d006100670065006d0020007300750070006500720069006f0072002000700061007200610020006f006200740065007200200075006d00610020007100750061006c0069006400610064006500200064006500200069006d0070007200650073007300e3006f0020006d0065006c0068006f0072002e0020004f007300200064006f00630075006d0065006e0074006f0073002000500044004600200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002c002000520065006100640065007200200035002e0030002000650020007300750070006500720069006f0072002egt DAN ltFEFF004200720075006700200064006900730073006500200069006e0064007300740069006c006c0069006e006700650072002000740069006c0020006100740020006f0070007200650074007400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006d006500640020006800f8006a006500720065002000620069006c006c00650064006f0070006c00f80073006e0069006e006700200066006f00720020006100740020006600e50020006200650064007200650020007500640073006b00720069006600740073006b00760061006c0069007400650074002e0020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e006500730020006d006500640020004100630072006f0062006100740020006f0067002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt NLD ltFEFF004700650062007200750069006b002000640065007a006500200069006e007300740065006c006c0069006e00670065006e0020006f006d0020005000440046002d0064006f00630075006d0065006e00740065006e0020007400650020006d0061006b0065006e0020006d00650074002000650065006e00200068006f0067006500720065002000610066006200650065006c00640069006e00670073007200650073006f006c007500740069006500200076006f006f0072002000650065006e0020006200650074006500720065002000610066006400720075006b006b00770061006c00690074006500690074002e0020004400650020005000440046002d0064006f00630075006d0065006e00740065006e0020006b0075006e006e0065006e00200077006f007200640065006e002000670065006f00700065006e00640020006d006500740020004100630072006f00620061007400200065006e002000520065006100640065007200200035002e003000200065006e00200068006f006700650072002egt ESP ltFEFF0055007300650020006500730074006100730020006f007000630069006f006e006500730020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000500044004600200063006f006e0020006d00610079006f00720020007200650073006f006c00750063006900f3006e00200064006500200069006d006100670065006e00200070006100720061002000610075006d0065006e0074006100720020006c0061002000630061006c006900640061006400200061006c00200069006d007000720069006d00690072002e0020004c006f007300200064006f00630075006d0065006e0074006f00730020005000440046002000730065002000700075006500640065006e00200061006200720069007200200063006f006e0020004100630072006f00620061007400200079002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004e00e4006900640065006e002000610073006500740075007300740065006e0020006100760075006c006c006100200076006f0069006400610061006e0020006c0075006f006400610020005000440046002d0061007300690061006b00690072006a006f006a0061002c0020006a006f006900640065006e002000740075006c006f0073007400750073006c00610061007400750020006f006e0020006b006f0072006b006500610020006a00610020006b007500760061006e0020007400610072006b006b007500750073002000730075007500720069002e0020005000440046002d0061007300690061006b00690072006a0061007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f006200610074002d0020006a00610020004100630072006f006200610074002000520065006100640065007200200035002e00300020002d006f0068006a0065006c006d0061006c006c0061002000740061006900200075007500640065006d006d0061006c006c0061002000760065007200730069006f006c006c0061002egt ITA ltFEFF00550073006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000500044004600200063006f006e00200075006e00610020007200690073006f006c0075007a0069006f006e00650020006d0061006700670069006f00720065002000700065007200200075006e00610020007100750061006c0069007400e00020006400690020007300740061006d007000610020006d00690067006c0069006f00720065002e0020004900200064006f00630075006d0065006e00740069002000500044004600200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f00700070007200650074007400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006d006500640020006800f80079006500720065002000620069006c00640065006f00700070006c00f80073006e0069006e006700200066006f00720020006200650064007200650020007500740073006b00720069006600740073006b00760061006c0069007400650074002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e006500730020006d006500640020004100630072006f0062006100740020006f0067002000520065006100640065007200200035002e00300020006f0067002000730065006e006500720065002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006e00e40072002000640075002000760069006c006c00200073006b0061007000610020005000440046002d0064006f006b0075006d0065006e00740020006d006500640020006800f6006700720065002000620069006c0064007500700070006c00f60073006e0069006e00670020006f006300680020006400e40072006d006500640020006600e50020006200e400740074007200650020007500740073006b00720069006600740073006b00760061006c0069007400650074002e0020005000440046002d0064006f006b0075006d0065006e00740065006e0020006b0061006e002000f600700070006e006100730020006d006500640020004100630072006f0062006100740020006f00630068002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006100720065002egt KOR ltFEFFd5a5c0c1b41c0020c778c1c40020d488c9c8c7440020c5bbae300020c704d5740020ace0d574c0c1b3c4c7580020c774bbf8c9c0b97c0020c0acc6a9d558c5ec00200050004400460020bb38c11cb97c0020b9ccb4e4b824ba740020c7740020c124c815c7440020c0acc6a9d558c2edc2dcc624002e0020c7740020c124c815c7440020c0acc6a9d558c5ec0020b9ccb4e000200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt CHS ltFEFF4f7f75288fd94e9b8bbe7f6e521b5efa76840020005000440046002065876863ff0c5c065305542b66f49ad8768456fe50cf52068fa87387ff0c4ee563d09ad8625353708d2891cf30028be5002000500044004600206587686353ef4ee54f7f752800200020004100630072006f00620061007400204e0e002000520065006100640065007200200035002e00300020548c66f49ad87248672c62535f003002gt CHT ltFEFF4f7f752890194e9b8a2d5b9a5efa7acb76840020005000440046002065874ef65305542b8f039ad876845f7150cf89e367905ea6ff0c4fbf65bc63d066075217537054c18cea3002005000440046002065874ef653ef4ee54f7f75280020004100630072006f0062006100740020548c002000520065006100640065007200200035002e0030002053ca66f465b07248672c4f86958b555f3002gt gtgtgtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice

Page 2: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

PLB DDR2 SDRAM Controller Design ParametersTo allow a user to create a PLB DDR2 SDRAM controller that is uniquely tailored for the system certain features are parameterizable in the PLB DDR2 SDRAM controller design This allows a user to have a design that only utilizes the resources required by the system and runs at the best possible performance The features that are parameterizable in the PLB DDR2 SDRAM controller are shown in Table 1

Table 1 PLB DDR2 SDRAM Controller Design Parameters

VHDL Type

G1 Include logic to support PLB bursts and cacheline transactions

C_INCLUDE_BURST_CACHELN_SUPPORT

0 = Controller will break up PLB burst or cacheline transfers into single memory read or write operations1 = Include logic to support PLB bursts and cacheline transfers

0 integer

G2 Include support for registered DIMM

C_REG_DIMM 0 = Unregistered DIMM1 = Registered DIMM

0 integer

G3 Supported number of external DDR2 SDRAM memory banks

C_NUM_BANKS_MEM(1) 1 - 4 1 integer

G4 Include logic to create extra setup time on DDR2 SDRAM address and control signals

C_EXTRA_TSU 0 = Does not create extra setup time1 = Creates extra setup time

0 integer

G5 Number of generated clock pairs supplied to the DDR2 SDRAM memory

C_NUM_CLK_PAIRS 1 - 4 1 integer

G6 Target FPGA family C_FAMILY virtex2p virtex4 virtex2p string

G7 Number of IDELAYCTRL modules to instantiate for Virtex-4 implementation

C_NUM_IDELAYCTRL 1 - 20 1 integer

G8 Include logic to separate DDR2 SDRAM clock domain from PLB clock domain

C_DDR_ASYNC_SUPPORT 1 = Include logic to separate DDR2 SDRAM clock domain from PLB clock domain0 = Not supported

1 integer

G9 Enable differential DQS capability for DDR2 SDRAM devices

C_DDR_ENABLE_DIFF_DQS

0 = Disable differential DQS logic1 = Enable differential DQS logic

0 integer

G10 Support open row management in DDR2 controller

C_USE_OPEN_ROW_MNGT

0 = Disable open row management capability1 = Support open row management

0 integer

Discontinued IP

0 integer

1 integer

0 integer

7 integer

VHDL Type

Discontinued IP

VHDL Type

Discontinued IP

Address Space

PLB Interface

Simulation Only

2 integer

VHDL Type

Discontinued IP

DDR2 SDRAM Signals

Discontinued IP

Clock Signals

Discontinued IP

SDRAM banks

Discontinued IP

IO Signals

Discontinued IP

- G18 G11 G32

- G19 G11 G32

Discontinued IP

(hex)Register

NameAccess Type

C_ECC_BASEADDR + 4

C_ECC_BASEADDR + 8

C_ECC_BASEADDR + C

C_ECC_BASEADDR + 10

Discontinued IP

FORCE_DE RE

darr darr

0 26 27 28 29 30 31

PEFORCE_

SE WE

Bit(s) NameCore

0-26 Reserved

Discontinued IP

DE

darr

0 21 22 28 29 30 31

0-21 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused SEC

0-19 Reserved

0 19 20 31

uarr uarrUnused DEC

0-19 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused PEC

0-19 Reserved

0 31

uarr uarrGIE Unused

Discontinued IP

DE_ISdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

DE_IEdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 3: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

0 integer

1 integer

0 integer

7 integer

VHDL Type

Discontinued IP

VHDL Type

Discontinued IP

Address Space

PLB Interface

Simulation Only

2 integer

VHDL Type

Discontinued IP

DDR2 SDRAM Signals

Discontinued IP

Clock Signals

Discontinued IP

SDRAM banks

Discontinued IP

IO Signals

Discontinued IP

- G18 G11 G32

- G19 G11 G32

Discontinued IP

(hex)Register

NameAccess Type

C_ECC_BASEADDR + 4

C_ECC_BASEADDR + 8

C_ECC_BASEADDR + C

C_ECC_BASEADDR + 10

Discontinued IP

FORCE_DE RE

darr darr

0 26 27 28 29 30 31

PEFORCE_

SE WE

Bit(s) NameCore

0-26 Reserved

Discontinued IP

DE

darr

0 21 22 28 29 30 31

0-21 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused SEC

0-19 Reserved

0 19 20 31

uarr uarrUnused DEC

0-19 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused PEC

0-19 Reserved

0 31

uarr uarrGIE Unused

Discontinued IP

DE_ISdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

DE_IEdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 4: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

VHDL Type

Discontinued IP

Address Space

PLB Interface

Simulation Only

2 integer

VHDL Type

Discontinued IP

DDR2 SDRAM Signals

Discontinued IP

Clock Signals

Discontinued IP

SDRAM banks

Discontinued IP

IO Signals

Discontinued IP

- G18 G11 G32

- G19 G11 G32

Discontinued IP

(hex)Register

NameAccess Type

C_ECC_BASEADDR + 4

C_ECC_BASEADDR + 8

C_ECC_BASEADDR + C

C_ECC_BASEADDR + 10

Discontinued IP

FORCE_DE RE

darr darr

0 26 27 28 29 30 31

PEFORCE_

SE WE

Bit(s) NameCore

0-26 Reserved

Discontinued IP

DE

darr

0 21 22 28 29 30 31

0-21 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused SEC

0-19 Reserved

0 19 20 31

uarr uarrUnused DEC

0-19 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused PEC

0-19 Reserved

0 31

uarr uarrGIE Unused

Discontinued IP

DE_ISdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

DE_IEdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 5: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

Address Space

PLB Interface

Simulation Only

2 integer

VHDL Type

Discontinued IP

DDR2 SDRAM Signals

Discontinued IP

Clock Signals

Discontinued IP

SDRAM banks

Discontinued IP

IO Signals

Discontinued IP

- G18 G11 G32

- G19 G11 G32

Discontinued IP

(hex)Register

NameAccess Type

C_ECC_BASEADDR + 4

C_ECC_BASEADDR + 8

C_ECC_BASEADDR + C

C_ECC_BASEADDR + 10

Discontinued IP

FORCE_DE RE

darr darr

0 26 27 28 29 30 31

PEFORCE_

SE WE

Bit(s) NameCore

0-26 Reserved

Discontinued IP

DE

darr

0 21 22 28 29 30 31

0-21 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused SEC

0-19 Reserved

0 19 20 31

uarr uarrUnused DEC

0-19 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused PEC

0-19 Reserved

0 31

uarr uarrGIE Unused

Discontinued IP

DE_ISdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

DE_IEdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 6: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

DDR2 SDRAM Signals

Discontinued IP

Clock Signals

Discontinued IP

SDRAM banks

Discontinued IP

IO Signals

Discontinued IP

- G18 G11 G32

- G19 G11 G32

Discontinued IP

(hex)Register

NameAccess Type

C_ECC_BASEADDR + 4

C_ECC_BASEADDR + 8

C_ECC_BASEADDR + C

C_ECC_BASEADDR + 10

Discontinued IP

FORCE_DE RE

darr darr

0 26 27 28 29 30 31

PEFORCE_

SE WE

Bit(s) NameCore

0-26 Reserved

Discontinued IP

DE

darr

0 21 22 28 29 30 31

0-21 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused SEC

0-19 Reserved

0 19 20 31

uarr uarrUnused DEC

0-19 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused PEC

0-19 Reserved

0 31

uarr uarrGIE Unused

Discontinued IP

DE_ISdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

DE_IEdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 7: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

Clock Signals

Discontinued IP

SDRAM banks

Discontinued IP

IO Signals

Discontinued IP

- G18 G11 G32

- G19 G11 G32

Discontinued IP

(hex)Register

NameAccess Type

C_ECC_BASEADDR + 4

C_ECC_BASEADDR + 8

C_ECC_BASEADDR + C

C_ECC_BASEADDR + 10

Discontinued IP

FORCE_DE RE

darr darr

0 26 27 28 29 30 31

PEFORCE_

SE WE

Bit(s) NameCore

0-26 Reserved

Discontinued IP

DE

darr

0 21 22 28 29 30 31

0-21 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused SEC

0-19 Reserved

0 19 20 31

uarr uarrUnused DEC

0-19 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused PEC

0-19 Reserved

0 31

uarr uarrGIE Unused

Discontinued IP

DE_ISdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

DE_IEdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 8: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

Discontinued IP

SDRAM banks

Discontinued IP

IO Signals

Discontinued IP

- G18 G11 G32

- G19 G11 G32

Discontinued IP

(hex)Register

NameAccess Type

C_ECC_BASEADDR + 4

C_ECC_BASEADDR + 8

C_ECC_BASEADDR + C

C_ECC_BASEADDR + 10

Discontinued IP

FORCE_DE RE

darr darr

0 26 27 28 29 30 31

PEFORCE_

SE WE

Bit(s) NameCore

0-26 Reserved

Discontinued IP

DE

darr

0 21 22 28 29 30 31

0-21 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused SEC

0-19 Reserved

0 19 20 31

uarr uarrUnused DEC

0-19 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused PEC

0-19 Reserved

0 31

uarr uarrGIE Unused

Discontinued IP

DE_ISdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

DE_IEdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 9: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

Discontinued IP

SDRAM banks

Discontinued IP

IO Signals

Discontinued IP

- G18 G11 G32

- G19 G11 G32

Discontinued IP

(hex)Register

NameAccess Type

C_ECC_BASEADDR + 4

C_ECC_BASEADDR + 8

C_ECC_BASEADDR + C

C_ECC_BASEADDR + 10

Discontinued IP

FORCE_DE RE

darr darr

0 26 27 28 29 30 31

PEFORCE_

SE WE

Bit(s) NameCore

0-26 Reserved

Discontinued IP

DE

darr

0 21 22 28 29 30 31

0-21 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused SEC

0-19 Reserved

0 19 20 31

uarr uarrUnused DEC

0-19 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused PEC

0-19 Reserved

0 31

uarr uarrGIE Unused

Discontinued IP

DE_ISdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

DE_IEdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 10: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

SDRAM banks

Discontinued IP

IO Signals

Discontinued IP

- G18 G11 G32

- G19 G11 G32

Discontinued IP

(hex)Register

NameAccess Type

C_ECC_BASEADDR + 4

C_ECC_BASEADDR + 8

C_ECC_BASEADDR + C

C_ECC_BASEADDR + 10

Discontinued IP

FORCE_DE RE

darr darr

0 26 27 28 29 30 31

PEFORCE_

SE WE

Bit(s) NameCore

0-26 Reserved

Discontinued IP

DE

darr

0 21 22 28 29 30 31

0-21 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused SEC

0-19 Reserved

0 19 20 31

uarr uarrUnused DEC

0-19 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused PEC

0-19 Reserved

0 31

uarr uarrGIE Unused

Discontinued IP

DE_ISdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

DE_IEdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 11: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

IO Signals

Discontinued IP

- G18 G11 G32

- G19 G11 G32

Discontinued IP

(hex)Register

NameAccess Type

C_ECC_BASEADDR + 4

C_ECC_BASEADDR + 8

C_ECC_BASEADDR + C

C_ECC_BASEADDR + 10

Discontinued IP

FORCE_DE RE

darr darr

0 26 27 28 29 30 31

PEFORCE_

SE WE

Bit(s) NameCore

0-26 Reserved

Discontinued IP

DE

darr

0 21 22 28 29 30 31

0-21 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused SEC

0-19 Reserved

0 19 20 31

uarr uarrUnused DEC

0-19 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused PEC

0-19 Reserved

0 31

uarr uarrGIE Unused

Discontinued IP

DE_ISdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

DE_IEdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 12: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

Discontinued IP

- G18 G11 G32

- G19 G11 G32

Discontinued IP

(hex)Register

NameAccess Type

C_ECC_BASEADDR + 4

C_ECC_BASEADDR + 8

C_ECC_BASEADDR + C

C_ECC_BASEADDR + 10

Discontinued IP

FORCE_DE RE

darr darr

0 26 27 28 29 30 31

PEFORCE_

SE WE

Bit(s) NameCore

0-26 Reserved

Discontinued IP

DE

darr

0 21 22 28 29 30 31

0-21 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused SEC

0-19 Reserved

0 19 20 31

uarr uarrUnused DEC

0-19 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused PEC

0-19 Reserved

0 31

uarr uarrGIE Unused

Discontinued IP

DE_ISdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

DE_IEdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 13: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

- G18 G11 G32

- G19 G11 G32

Discontinued IP

(hex)Register

NameAccess Type

C_ECC_BASEADDR + 4

C_ECC_BASEADDR + 8

C_ECC_BASEADDR + C

C_ECC_BASEADDR + 10

Discontinued IP

FORCE_DE RE

darr darr

0 26 27 28 29 30 31

PEFORCE_

SE WE

Bit(s) NameCore

0-26 Reserved

Discontinued IP

DE

darr

0 21 22 28 29 30 31

0-21 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused SEC

0-19 Reserved

0 19 20 31

uarr uarrUnused DEC

0-19 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused PEC

0-19 Reserved

0 31

uarr uarrGIE Unused

Discontinued IP

DE_ISdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

DE_IEdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 14: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

(hex)Register

NameAccess Type

C_ECC_BASEADDR + 4

C_ECC_BASEADDR + 8

C_ECC_BASEADDR + C

C_ECC_BASEADDR + 10

Discontinued IP

FORCE_DE RE

darr darr

0 26 27 28 29 30 31

PEFORCE_

SE WE

Bit(s) NameCore

0-26 Reserved

Discontinued IP

DE

darr

0 21 22 28 29 30 31

0-21 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused SEC

0-19 Reserved

0 19 20 31

uarr uarrUnused DEC

0-19 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused PEC

0-19 Reserved

0 31

uarr uarrGIE Unused

Discontinued IP

DE_ISdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

DE_IEdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 15: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

FORCE_DE RE

darr darr

0 26 27 28 29 30 31

PEFORCE_

SE WE

Bit(s) NameCore

0-26 Reserved

Discontinued IP

DE

darr

0 21 22 28 29 30 31

0-21 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused SEC

0-19 Reserved

0 19 20 31

uarr uarrUnused DEC

0-19 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused PEC

0-19 Reserved

0 31

uarr uarrGIE Unused

Discontinued IP

DE_ISdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

DE_IEdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 16: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

DE

darr

0 21 22 28 29 30 31

0-21 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused SEC

0-19 Reserved

0 19 20 31

uarr uarrUnused DEC

0-19 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused PEC

0-19 Reserved

0 31

uarr uarrGIE Unused

Discontinued IP

DE_ISdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

DE_IEdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 17: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

0 19 20 31

uarr uarrUnused SEC

0-19 Reserved

0 19 20 31

uarr uarrUnused DEC

0-19 Reserved

Discontinued IP

0 19 20 31

uarr uarrUnused PEC

0-19 Reserved

0 31

uarr uarrGIE Unused

Discontinued IP

DE_ISdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

DE_IEdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 18: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

0 19 20 31

uarr uarrUnused PEC

0-19 Reserved

0 31

uarr uarrGIE Unused

Discontinued IP

DE_ISdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

DE_IEdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 19: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

DE_ISdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

DE_IEdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 20: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

DE_IEdarr

0 28 29 30 31

Bit(s) NameCore

0-28 Reserved

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 21: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

n n+1 n+2 n+3

0 1 2 3

MSB LSB

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSB LSB

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSB

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

n

0 1 2

MSB LSB

0 63

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Word

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 22: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

Discontinued IP

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 23: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

DDR_DM(01)

DDR_DQ_ECC(06)

DDR_DQS_ECC

DDR_DM_ECC

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

x16

DDR2 SDRAMMemory 3

x16

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

DQ(159)

UDQS

UDM

Discontinued IP

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 24: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

DDR_DM(03)

DDR2 SDRAM

DDR_DQ(3263)

DDR_DQS(47)

DDR_DM(47)

Memory 1x32

DDR2 SDRAMMemory 2

x32

DDR_Addr(012)

DDR_BankAddr(02)

DQ(310)

DQS(30)

DM(30)

DQ(310)

DQS(30)

DM(30)

DDR_DQSn(03)

Variable Equation

Discontinued IP

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 25: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

32 - (9 + 2) = 21

Variable Equation

Discontinued IP

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 26: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

32 - (8 + 3) = 21

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 27: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

Discontinued IP

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 28: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

Write AsyncFIFO

PLB_Clk

PLB

IPIF

IO

REG

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n

Device_Clk90

Device_Clk90_n3

DDR_Clk90_in3

DDR_Clk90_in_n3

PLB

Sys_Clk

ECC1

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

control signals

IDELAY Logic2

IPIC

IF

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL2

Cal_Clk2

Clk_200

Data Tap Inc2

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]

DDR_BankAddr [0n ]

DDR_DQ_t[0n]

DDR_DQ_ECC_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0 n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_DQS_ECC_o

DDR_DM_ECC

DDR_DQS_ECC_i

DDR_DQSn_ECC_o

DDR_DQS_ECC_t

DDR_DQ_ECC_o[0n]

DDR_DQ_ECC_i[0n]

DDR_ODT

DDR_DQSn_ECC_i

DDR_DQSn_ECC_t

Discontinued IP

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 29: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

Bus

2IP_

WrR

eq

Bus

2IP_

Dat

a

ECC

2IP_

Chk

_Bits

IP2E

CC

_Chk

_Bits

IP2E

CC

_Rea

d_D

ata

IP2E

CC

_RdA

ck

ECC Logic

ECC

CR

IP2B

us_R

dAck

IP2B

us_D

ata

IP2E

CC

_WrA

ck

IP2B

us_W

rAck

ECC

2IP_

Dat

aEC

C2I

P_W

rReq

IPIC

Bus

2IP_

CS

Bus

2IP_

CE

Bus

2IP_

RdC

E

Bus

2IP_

WrC

E

reg_

wra

ck

reg_

data

reg_

rdac

k

IP2E

CC

_Add

rAck

reg_

addr

ack

ecc2

bhw

_add

rack

Bus

2IP_

CS

IP2B

us_A

ddrA

ck

Bus

2IP_

BE

Bus

2IP_

Bur

st

Bus2

IP_A

ddr

ECC

2IP_

Add

r

ECC

2IP_

CS

ECC

2IP_

BE

Bus

2IP_

RdR

eq

ECC

2IP_

CE

ECC

2IP_

RN

WEC

C2I

P_B

urst

Bus

2IP_

RN

W

bhw

2ecc

_

ecc2

bhw

_wra

ck

bhw2ecc_BE

ecc2

bhw

_rda

ck

ecc2bhw_data

ECC

CR

Discontinued IP

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 30: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

Syndrome (MSB)

Discontinued IP

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 31: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

IDLE

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

DONE

cmd_done

REFRESH2

SET_OP

cmd_done

reset

cmd_done

ODT_ACTIVE

odt_count

Discontinued IP

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 32: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

ACT_CMD

LOAD _MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load _mr

Precharge

GPcnt_end

GPcnt _endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE _WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end +

Tras_min_end

RdReq + Burst

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 33: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

Discontinued IP

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 34: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

IDLE

WRITE_DATAREAD_DATA

DONE

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 35: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

PLB_Clkwr_clk

wr_en

data_fifo_wr_en

PLB_Clkwr_clk

din

wr_en

DDR_dq_oe_cmb

rd_clk

empty

rd_en

dout

rd_clk

dout

rd_en

emptycmd_fifo_wr_en

Discontinued IP

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 36: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

IO Registers

Discontinued IP

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 37: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

D

D0

D1

C0C1

Q

CDevice_Clk

Write_data_en

DDR_DQ_t [i]

DDR_DQ_o [i]

D

D0

D1

C0C1

Q

C

DDR_DQS_t [i]2

DDR_DQS_o[i]2

Write_dqs_en

Device_Clk90

GND

VCC

DQ

Device_Clk

Device_Clk_n

Device_Clk90_n

D

D0

D1

C0C1

Q

C

DDR_DQSn_t [i]2

DDR_DQSn_o[i]2

Write_dqsn_en

Device_Clk90

GND

VCC

Device_Clk90_n

Discontinued IP

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 38: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

D

C0C1

Q0DDR_RdData_high

DQ

C

DDR_Clk90_in

DDR_DQ_i[i]2

DDR_RdDQS

DDR_DQS_i[i]2

ddr_read_data_en

CE

DQ

C

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DQ

C

DDR_RdDQSn

DDR_DQSn_i[i]2

ddr_read_dqs_ce DQ

C

read_dqs_ce

DDR_Clk90_in

Discontinued IP

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 39: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

DDR_DQ_i IDELAY

dq_idelay_out

Device_Clk

Cal_Clk

DDR_DQS_i IDELAY

dqs_idelay_out

Device_Clk

IDDR

Q1

Q2

DDR_DQSn_i IDELAY

dqsn_idelay_out

Device_Clk

IDDR

Q1

Q2

Discontinued IP

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 40: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

DQ

C

Read_dataDIN

WREN

WRCLK

RDEN

RDCLK

DOUT

EMPTYCLR

PLB_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

fifo_rdenRdAck

Read_data_en

Discontinued IP

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 41: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

D Q C

Read_data_en

Read_data

fifo_rden

PLB_Clk

fifo_empty

RdAck

fifo_wr_data

fifo_wren

Device_Clk

0

1

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

1

D Q

Device_Clk

DIN

WEEN

WECLK

RDEN

DOUT

RDCLK

EMPTY

Multiple Data Width

Discontinued IP

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 42: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

PLB DDR2

150

Vdd

150

DDR2 SDRAM

Rtt( eff ) = 75

PLB DDR2

300

Vdd

300

Rtt( eff ) = 150

DDR2 SDRAM

Ω

Discontinued IP

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 43: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

tAONDtAOFD

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 44: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

CLKIN

CLKFB

CLK0

CLK90External

DDR2 SDRAM

FPGA

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCM

DD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

DDR_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 45: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

CLKIN

CLKFB

CLK0

CLK90External

DDR2

FPGA

PLB DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLKIN

CLKFB

CLK0

CLK90

DCMDD

R_C

lk_f

b

CLK CLKn DDR_Clkn

Clock

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

DCM

CLK180

CLK270

PLB_Clk

System Clk

DDR2 Device

and DDR_Clk90_in_n

Controller

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 46: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

CLKIN

CLKFB

CLK0

CLK90External

FPGA

Cal_Clk

DDR_Clk

DDR_ClknClock

DCM

PLB_Clk

System Clk

DDR2 Device

PLB DDR2

Controller

200 MHz ClkSDRAM

CLKDV

IDELAYCTRL

Ref_Clk

Discontinued IP

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 47: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

CLKIN

CLKFB

CLK0

CLK90External

FPGA

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

Device_Clk90_in_n

DCM

PLB_Clk

System Clk

DDR2 Device

CLK180

CLK270

Cal_ClkCLKDV

Device_Clk_n

IDELAYCTRL

Ref_Clk

Discontinued IP

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 48: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

D0

D1

C0C1

Q

Device_Clk90_in

VCC

GND

D0

D1

C0C1

QGND

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 49: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12

Addr0Addr0

00

FFFF

DATA

BA(A0)

RA(A0) CA(A0) 1FFF

FF 0

data0

FF 0 F 0 F 0

Data0

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 50: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

DDR_DM_ECC

DDR_DQ_ECC[06]

DDR_DQS_ECC

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Addr0Addr0

00

FFFF

DATA

1FFF

F

FF 0 F 0F 0 F

F

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 51: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

PLB_wrDBus[063]

Sl_addrAck

Sl_wrDAck

Sl_wrComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17

A0A0

BB

0001000000010000

D0 D0+2

BA(A0)

RA(A0) CA(A0) C+2(A0)

D0 D0+2

f f 00000000 f f

Discontinued IP

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

C_N

UM

_BA

NK

S_M

EM

C_R

EG

_DIM

M

C_I

NC

LU

DE

_BU

RST

_CA

CH

EL

N_S

UPP

OR

T

C_D

DR

_DW

IDT

H

C_I

NC

LU

DE

_EC

C_S

UPP

OR

T

C_I

NC

LUD

E_EC

C_I

NTR

C_I

NC

LUD

E_EC

C_T

EST

C_D

DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 52: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

Cycles

PLB_Clk

PLB_PAValid

PLB_ABus[031]

PLB_size[03]

PLB_BE[07]

PLB_RNW

Sl_rdDBus[063]

Sl_addrAck

Sl_rdDAck

Sl_rdComp

DDR_Clk

DDR_Clkn

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[07]

DDR_DQ[063]

DDR_DQS[07]

00 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24

A0A0

BB

0001000000010000

D0 D0+2

1FFF

F

f f f f

Discontinued IP

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DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

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AB

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DQ

S

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PEN

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W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 53: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

Discontinued IP

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PEN

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W_M

NG

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2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

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DQ

S

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PEN

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W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 54: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

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NG

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2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

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C_S

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NTR

C_I

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LUD

E_EC

C_T

EST

C_D

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_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 55: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

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PEN

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W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1126 960 880 1008 2187

1 0 1 32 0 0 0 0 0 0 1195 1150 1206 1038 2028

1 1 1 32 0 0 0 0 0 0 1293 1207 1206 1116 2044

1 0 1 32 1 0 0 1 0 75 2085 2001 2390 1010 2053

1 1 1 32 1 0 0 1 0 150 2226 2090 2391 1010 2049

1 0 0 32 0 0 0 0 1 0 1162 1055 1025 1007 2107

4 1 0 32 0 0 0 0 1 0 1279 1139 1070 1010 2212

1 0 1 32 1 1 0 1 0 75 2141 2063 2467 1008 2057

1 0 1 32 1 1 1 1 0 0 2129 2054 2464 1022 2214

1 1 1 32 1 1 1 1 0 0 2237 2112 2466 1006 2487

1 0 1 64 0 0 0 0 0 0 1647 1469 1360 1016 2040

1 1 1 64 0 0 0 1841 1582 1360 1042 2065

1 1 1 64 1 0 0 1889 1620 1358 1025 2409

1 0 0 64 0 1 0 1615 1369 1175 1009 2028

1 1 0 64 0 1 0 1809 1480 1175 1093 2066

4 0 1 64 0 1 0 1657 1496 1405 1009 2242

4 1 1 64 0 1 150 1866 1617 1409 1015 2162

Discontinued IP

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LUD

E_EC

C_T

EST

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DR

_EN

AB

LE_D

IFF_

DQ

S

C_U

SE_O

PEN

_RO

W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 56: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

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PEN

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W_M

NG

T

C_D

DR

2_O

DT_

SETT

ING Slice

Flip Flops

Slices 4-

input LUTs

PLBfMAX

DDR2fMAX

1 0 0 32 0 0 0 0 0 0 1670 2913 1782 1492 2666

1 1 0 32 0 0 0 0 0 0 1748 1973 1659 1292 2682

1 1 0 64 0 0 0 0 0 0 2758 2913 2319 1199 2684

1 1 1 32 0 0 0 0 0 0 1878 2179 1828 1228 2672

1 1 1 64 0 0 0 0 0 0 2358 2722 2413 1159 2702

1 0 1 32 1 0 0 1 0 75 2912 3438 3424 1109 2670

1 1 1 32 1 0 0 1 0 75 3010 3390 3424 1037 2669

1 1 0 32 0 0 0 0 1 0 1844 2139 1713 1024 2669

1 1 1 32 0 0 0 0 1 0 1825 2189 2174 1025 2673

1 1 1 64 0 0 0 0 1 0 2297 2686 2768 1136 2675

1 0 1 32 1 0 0 1 1 150 2907 3405 3416 1025 2668

1 1 1 32 1 0 0 1 1 150 3005 3489 3416 1013 2669

2 1 1 32 0 0 0 0 0 0 1816 2136 1961 1147 2696

4 1 1 32 0 0 0 0 0 0 1822 1976 1986 1039 2693

2 1 1 64 0 0 0 0 1 0 2853 3106 2786 1031 2670

4 1 1 64 0 0 0 0 1 0 2868 2988 2789 1106 2699

Discontinued IP

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History

Page 57: DS425 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design,

Revision History

Discontinued IP

- Introduction
- Features
        
        
        
        
        
        
        Example
        
        
        
        ECC Testing
        
        Init State Machine
        
        
        
        
        Data State Machine
        
        
        
        IO Registers
        
        Control Signals
        
        Write Data
        
        
        
        
        
        Multiple Data Width
        
        
        
        DDR2 SDRAM Clocking
        
        
        
        
        
        
        
        Timing Diagrams
        
        Design Constraints
        
        Timing Constraints
        
        Pin Constraints
        
        IDELAY Constraints
        
        
        Target Technology
        
        
        
        Reference Documents
        
        Revision History