Direct Communicationand Synchronization Mechanismsin Chip MultiprocessorsStamatis KavadiasComputer Science DepartmentUniversity of Crete (UOC-CSD)andInstitute of Computer ScienceFoundation for Research and Technology Hellas (FORTH-ICS)Motivation and Approach CMP architectures becoming more distributed (manycore) Utilize scalable NoC (>> few tens of cores) Scalable communication mechanisms required to exploit chip Locality will be very important Low latency communication exploit locality effectively Fast synchronization improve efficiency of fine-grain comp. This study advocates: Use on-chip scratchpad memory for comm/comp Exploit direct communication and synchronization mechanisms Aim scalable mechanisms & implementation Exploit increased (replicated) resources Reduce overheads with on-chip bulk transfers Enable efficient communication supporting NoC optimizations2University of Crete & Foundation for Research & Technology - HellasProposed Architectural Enhancements& Contributions Modify contemporary CMP architecture to support: Shared address space extension for direct scratchpad access Cache integration of a network interface (NI) Direct communication mechanisms for RDMA & messages Direct synchronization mechanisms (counters & queues) The contributions of this thesis are: Design a CMP network interface integrated at top memory hierarchy levels Introduce event responses technique for cache integration of NI communication & synchronization mechanisms Design direct synch. mechanisms with existing cache resources Refine HW design to reduce gates by 19.3% (