10/23/2006
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Critical Dimension Control and its Implications in IC Performance
Costas J. SpanosFLCC, 10/23/06
10/23/2006
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Critical Dimension in Perspective(Leff in particular)
• Controls both leakage and saturation current• Depends on Litho, Etch, Implant, Diffusion, Annealing• Its components can be measured with limited precision:
– CD SEM: 1-2nm– Ellipsometry: ~0.5nm– Electrical: ~0.2nm
• Has “hierarchical” nature with different variation mechanisms– Wafer to wafer– Across wafer– Across field, in 100’s of µm distances– Feature to feature, due to pattern density, etc.– Line edge roughness in 10’s of nm distances
• Industry strives to keep TOTAL variability under 10%. This means 3 sigma total of less than 1nm in the next couple years.
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Outline
• CD Control• CD Modeling• IC Performance Impact• New Directions
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Some of the recent advances in CD Control come from added Process Visibility – PEB, for example
Transient heating and cooling
Uniformity Control
Courtesy OnWafer Technologies
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PEB Temp Control Using Wireless Metrologyusing multi-zone plate modeling and feedback
AfterBefore
16 plates, 120 ºC Target
2.700oC
Target = 120oC
0.175oC
Courtesy OnWafer Technologies
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Post Exposure bake Driven CDU Improvement
AcrossPlate Plate to
Plate
Optimize CD
Optimize TemperatureProcess of Record
0
0.5
1
1.5
2
2.5
3
3.5
Courtesy OnWafer Technologies
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We can also monitor Plasma Etch Temperature…
Routine He Reduced He
pre-etchpre-etch
main etchmain etch
de-chuckde-chuckover etchover etch
Courtesy OnWafer Technologies
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Present Status of “Active” CD Control
Spin
HMDS
PA Bake
Exposure
PEB
Develop
PD Bake
Photoresist Removal
Poly Etch System
ADIADI AEIAEI
Etch
Etch
Etch
ELMELM
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On-wafer and in-line metrology in pattern transfer
Spin
HMDS
PA Bake
Exposure
PEB
Develop
PD Bake
Photoresist Removal
ELMELM
Poly Etch SystemEtch
Etch
Etch
T (t, x, y)T (t, x, y)
T (t, x, y)V (t, x, y)E (t, x, y)…
T (t, x, y)V (t, x, y)E (t, x, y)…
I (x, y)I (x, y)
OCDOCD
Thin FilmThin Film
OCDOCD OCDOCD
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CDU control has to incorporate many strategies
Spin
HMDS
PA Bake
Exposure
PEB
Develop
PD Bake
Photoresist Removal
ELMELM
Poly Etch SystemEtch
Etch
Etch
T (t, x, y)FF control
T (t, x, y)FF control
T (t, x, y)V (t, x, y)E (t, x, y)FF/FB Control, chuck diagnostics
T (t, x, y)V (t, x, y)E (t, x, y)FF/FB Control, chuck diagnostics
I (x, y)Optimal Pattern Design
I (x, y)Optimal Pattern Design
OCDProfile Inversion
FB Control
OCDProfile Inversion
FB Control
Thin FilmFB/FF Control
Thin FilmFB/FF Control
OCDFB Control
OCDFB Control
OCDFB/FF Control
OCDFB/FF Control
Feb. 2004 P. 11
Joint TSMC, UCB, OnWafer Paper, SPIE 2004Experiments
Various PEB plate parameters determine behavior in each segment. These parameters were varied and CD data was collected at the same time
Overshoot meanOvershoot range
Steady state duration
Cooling meanCooling range
Dynamic Profile V.S. CD Dynamic Profile V.S. CD –– 9 factors 9 factors
Heating rate meanHeating rate range
• 9 thermal-related factors are extracted and linked to CD maps.
• Regression analysis is performed to establish statistical significance.
Steady state meanSteady state range
Feb. 2004 P. 12
CD range =3.4nm
Baseline
00.0010.0020.0030.0040.0050.0060.0070.0080.0090.01
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CDU
0.09
0.091
0.092
0.093
0.094
0.095
0.096
0.097
0.098
0.099
CD m
ean
CDUCD Mean
PHP compensated
00.0010.0020.0030.0040.0050.0060.0070.0080.0090.01
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CDU
0.09
0.091
0.092
0.093
0.094
0.095
0.096
0.097
0.098
0.099
CD m
ean
CDUCD mean
PHP re-compensated
0.0000.0010.0020.0030.0040.0050.0060.0070.0080.0090.010
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
CDU
0.094
0.095
0.096
0.097
0.098
0.099
0.100
0.101
0.102
0.103
CD m
ean
CDUCD mean
20 Wafers
20 Wafers
25 Wafers
CDU=3.5nm
Across Wafer CDU =3.8nm
Wafer to Wafer
CD range 3.4nm
CD range 1.5nm
CDU=3.5nm
CD range 1.0nm
Baseline
Adjusted
2nd iteration
4 PHP/ 4DEV4 PHP/ 4DEVWithin Lot CDU Summary
Joint TSMC, UCB, OnWafer Paper, SPIE 2004
• Dramatic CDU improvement was achieved with TCM
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Supervisory Control with Wireless Metrology
Example chip speed map
• Across-wafer (AW) CD (gate-length) uniformity impacts IC performance– Large AW CDV large chip-to-chip performance variation
low yield
• How to cope with increasing AW CD variation?– Employ design tricks, e.g., adaptive body biasing, which has limitations– Reduce AW CD variation during manufacturing is the most effective
approach
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CD Uniformity Control Approach• Making each process step spatial uniform
is prohibitively expensive
• Our approach: manipulate PEB temperature spatial distribution of multi-zone bake plate (and die-to-die dose) to compensate for other systematic across-wafer CD variation sources
CDU Control Framework
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Multi-zone PEB Bake Plate
24
36
5 71
Approximate schematic setup of multi-zone bake plate
Each zone is given an individual steady state target temperature,
by adjusting an offset value
T=Ttarget-Offset+effect of other zones
Zone offset knobs
PEB BakePlate
→
∆O ),( yxT→
∆ ),( yxCD→
∆
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Develop Inspection (DI) CDU Control Methodology II
• DI CD is a function of zone offsets
baselineresistDI CDSTCD→→→
+∆=
( )
( )⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡=
⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡=
→
721
72111
...,...
...,...
OOOg
OOOg
T
TT
mm
baselineTTT→→→
−=∆
( )
( )⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡=
⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡=
→
721
72111
...,...
...,...
OOOf
OOOf
CD
CDCD
nn
DI
• Seen as a constrained quadratic programming problem• Minimize
• Subject to: Upi
Low OOO ≤≤
⎟⎠⎞
⎜⎝⎛ −⎟
⎠⎞
⎜⎝⎛ −
→→→→
ettDI
T
ettDI CDCDCDCD argarg
7...2,1=i
Temperature Offset Model
CD Offset Model
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Final Inspection (FI) CDU Control Methodology
• Across-wafer FI CD is function of zone offsets
baselineresistDI CDSTCD→→→
+∆=
• Minimize: ⎟⎠⎞
⎜⎝⎛ −⎟
⎠⎞
⎜⎝⎛ −
→→→→
ettFI
T
ettFI CDCDCDCD argarg
DIFIps CDCDCD→→∆→
−=∆
⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡=∆+=
→→→
)...,(...
)...,(
721
7211
OOOg
OOOgCDCDCD
n
psDIFI
• Plasma etching induced AW CD bias (signature)
Upi
Low OOO ≤≤• Subject to: 7...2,1=i
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FI CDU Control Verification Experiment Setup• Focus on Pitch 250 L/S 1:1, plate B• Use two-week-average FICD and bias signatures to generate offsets• Verification experiment is done sequentially • PEB adjustment is checked first to ensure it is close to the model-
predicted one• DICD is then checked to ensure its correct adjustment• FICD is finally checked
6 wfrs
Plate B (PEB adjusted)(Litho)
PEB verification
MeasureDICD
DICD verification
Chamber (Etch)
MeasureFICD
FICD verification
Verification experiment setupVerification experiment setup
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Long Term Overall Improvement ~35%in recently completed experiment at AMD/SDC
across-wafer sigma of 250 1:1 lines, using CDSEM
0
0.5
1
1.5
2
2.5 Before
After
Confirmation Wafers (done six months after calibration)
σ=1.36nm
m=141.9nm
σ=1.21nm
m=142.1nm
σ=1.26nm
m=141.7nm
σ=1.14nm
m=141.5nm
σ=1.41nm
m=141.4nm
σ=1.39nm
m=142.4nm
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Verification experiment results (before control vs. after control)
FI CDV before and after control
0
0.5
1
1.5
2
2.5
Before AfterFI
CD
V 1
sigm
a(nm
) Wfr1
Wfr2
Wfr3
Wfr4
Wfr5
Wfr6
DI CDV before and after control
00.5
11.5
22.5
33.5
44.5
Before After
DI C
DV
1 si
gma
(nm
) Wfr1
Wfr2
Wfr3
Wfr4
Wfr5
Wfr6
DICD uniformity is sacrificed in order to optimize FICD uniformity
Qiaolin (Charlie) Zhang, on internship at AMD/ Spansion 2005-06
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Data Mining for Yield Ramping (APC)• What is it: Exploit existing tool/wafer data
for control optimization• Basic Idea:
– Wafer Metrology alone has limited precision – enhance it by combining tool/process/wafer data using multivariate techniques
– Identify basic operating fingerprints, and distinguish from fingerprints in “rogue” situations
– Combine basic operating fingerprints to predictive models suitable for APC
• Potential Payoff: – Faster, more disciplined yield ramp– Rational deployment of metrology and control resources– Leapfrog present metrology precision/accuracy limitations
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Example of Proposed Control Deployment
Process AProcess A Process BProcess BIncoming Wafer
Physical Wafer Measurements
Outgoing Wafer
Process A Model
Process B Model
Recipe ModelMaintenance
Model Prediction of Physical and Electrical Wafer parameters
ModelMaintenance
SPC & recipe Filter
SPC & recipe Filter
Control Limits driving control alarms
Model-based Controller
Model-based Controller
Generate Corrections
Control Decisions(supervisor decides on feedback/feed-forward)
Process Specifications
Production Metrology
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Virtual Metrology Preview
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
AV
EP
mos
Idsa
t Act
ual
-0.4 -0.3 -0.2 -0.1 .0 .1 .2AVEPmosIdsat Predicted P<.0001RSq=0.96 RMSE=0.0324
-0.8
-0.75
-0.7
-0.65
-0.6
-0.55
-0.5
-0.45
AV
Evt
P A
ctua
l
-0.80 -0.70 -0.65 -0.60 -0.55 -0.50AVEvtP Predicted P<.0001 RSq=0.96RMSE=0.0155
RSquareRSquare AdjRoot Mean Square ErrorMean of ResponseObservations (or Sum Wgts)
0.9637950.9391110.032425-0.11287
38
Summary of FitRSquareRSquare AdjRoot Mean Square ErrorMean of ResponseObservations (or Sum Wgts)
0.9604880.9458540.015473-0.62092
38
Summary of Fit
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Outline
• CD Control• CD Modeling• IC Performance Impact• New Directions
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Motivation• Monte Carlo simulation:
delay power
Canonical circuit Manuf. statisticsµ, σ2
spatial correlation
, ρ(∆x, ∆y)Manuf. statisticsµsys(x,y), σ2
rand
(ρµm(∆x, ∆y))
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Decomposition of Spatial CD Variation
= +
Average Wafer Scaled Mask Errors Across-Field Variation
Across-Wafer Variation
+ + +
Die-to-Die Variation “Random” VariationJ. Cain and C. Spanos, “Electrical linewidth metrology for systematic CD variation characterization and causal analysis,” Metrology, Inspection, and Process Control for Microlithography XVII, Proceedings of SPIE vol. 5038, pp. 350-361, 2003.
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Spatial Correlation & Process Control• Calculation of spatial correlation,
before and following decomposition of variance:
( ) nzz kjjk /*∑=ρ
• Large(mm)-scale spatial correlation is largely accounted for by systematic variation; smaller, (µm)-scale correlation may still have structure, focus of current work
( ) σ/xxz ii −=
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Outline
• CD Control• CD Modeling• IC Performance Impact• New Directions
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Digital Circuit Design and Sizing• Digital Circuit Sizing Optimization Problem
– Goal: size the gates in a combinational logic circuit– Minimize the effects of individual gate delay variations and
spatial correlations on the overall circuit delay• Previous Work: Geometric Programming approach
– Objective:where: Di = nominal delay for gate i
k = a constant ~ 2derived from Pelgrom’s Model
with model parameter γ– Constraints: Fixed maximum total circuit area
)]}([min{max }{ DkD ipi
ipathsallcircuitp σ+∑∈
∈
iii DxD )()( 2/1−= γσ
† S. Boyd, S.-J. Kim, D. Patil, and M. Horowitz , “A Heuristic Method for Statistical Digital Circuit Sizing ,” 31st SPIE International Symposium on Microlithography, February 2006.
†† M. Pelgrom, A. Duinmaijer and A. Welbers, “Matching Properties of MOS Transistors,”, IEEE J. Solid-state Circuits, Vol.24, No. 5, pp.1433-1439, Oct. 1989.
†
††
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Performance Analysis• 32-bit Ladner-Fisher adder circuit is sized and analyzed
– 459 gates, 3214 paths from input to output gates• Monte Carlo analysis with 5000 samples
– RC model for nominal delay and a delay variation only due to vth
– Overall circuit delay statistics are compared under two designs:
• Nominal Design, σ =0.88• Statistical Design, σ =0.47
• Limitations– gate delay variation depends only on Vth
– Ignored spatial correlations between the gates † S. Boyd, S.-J. Kim, D. Patil, and M. Horowitz , “A Heuristic Method for Statistical Digital Circuit Sizing ,” 31st SPIE International Symposium on Microlithography, February 2006.
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More Comprehensive Designs• Adding delay variation dependence on Leff in the
objective function:
iiLeffiithi DxDxD )()()( 2/12/1 −− += γγσ
)]}([min{max }{ DkD ipi
ipathsallcircuitp σ+∑∈
∈
• Adding variation dependence on Leff and Spatial Correlation
]}[)]([min{max,,
22}{ ∑∑
≠∈∈∈ ++
jipjijiiji
piipathsallcircuitp kDkD σσρσ
iiLeffiithi DxDxD )()()( 2/12/1 −− += γγσ
where:
where:
⎩⎨⎧
≥≤−−
=LijB
LijBLij
XdXdXd
ρρ )1(/1
ρij ≡ spatial correlation between gate i and j with separation dij
XL characteristic correlation lengthρB characteristic correlation baseline
Large scale model
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Monte Carlo Analysis on Circuit Delay• 32-bit Ladner-Fisher adder circuit is analyzed• Four types of Monte Carlo analysis are performed for each design
1. σ(D)~σ(Vth): gate delay variation results from σ(Vth)
2. σ(D)~σ(Vth)+sp.corr: gate delay variation results from σ(Vth) and spatial correlations exist between the gates
3. σ(D)~σ(Vth)+σ(Leff): gate delay variation results from both σ(Vth)and σ(Leff)
4. σ(D)~σ(Vth)+σ(Leff)+sp. corr: gate delay variation results from σ(Vth), σ(Leff) and spatial correlations exits between the gates
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frequ
ency
a) Deterministic design objective
delay
frequ
ency
delay
frequ
ency
delay
frequ
ency
Simulation Results (5000 Monte Carlo Samples)b) Minimize delay variations due to Vth
c) Min. delay var. due to Vth and Leff d) Min. delay var. due to Vth, Leff and Spa. Corr.
(4) σ(D) ~ σ(Vth)+σ(Leff) +sp. corr.
(1) σ(D) ~ σ(Vth)(2) σ(D) ~ σ(Vth)+sp.corr.(3) σ(D) ~ σ(Vth)+σ(Leff)
(4) σ(D) ~ σ(Vth)+σ(Leff) +sp. corr.
(1) σ(D) ~ σ(Vth)(2) σ(D) ~ σ(Vth)+sp.corr.(3) σ(D) ~ σ(Vth)+σ(Leff)
(4) σ(D) ~ σ(Vth)+σ(Leff) +sp. corr.
(1) σ(D) ~ σ(Vth)(2) σ(D) ~ σ(Vth)+sp.corr.(3) σ(D) ~ σ(Vth)+σ(Leff)
(4) σ(D) ~ σ(Vth)+σ(Leff) +sp. corr.
(1) σ(D) ~ σ(Vth)(2) σ(D) ~ σ(Vth)+sp.corr.(3) σ(D) ~ σ(Vth)+σ(Leff)
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Simulation Results• Focus on the last analysis which considers both delay variations due to Vthand Leff, and spatial correlations
delay
frequ
ency
a) Deterministic designσ(D) = 3.02, yield = 63.42%
b) Minimize delay variations due to Vth
σ(D) = 1.96, yield = 92.06%
c) Min. delay var. due to Vth and Leff
σ(D) = 1.52, yield = 96.62%
d) Min. delay var. due to Vth, Leff and spatial correlation
σ(D) = 1.36, yield = 98.22%
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Outline
• CD Control• CD Modeling• IC Performance Impact• New Directions
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Matching Properties of MOSFETs
( ) ( ) ( )12 12 12 121, ', ' ' , ' ' 'P x y P x y G x x y y dx dy
area
∞ ∞
−∞−∞
∆ = − −∫ ∫( )
( )
1 2 1 212 12,
2 2
', ' ' , ' ' , '2 2
, , ,1, 2 2 2 2
0
x x y yx y
D DG x y BOX x y BOX x y
L L W Wfor x yBOX x y
else
+ += =
⎛ ⎞ ⎛ ⎞= − − +⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠
⎛ ⎞ ⎛ ⎞∈ − ∈ −⎧ ⎜ ⎟ ⎜ ⎟= ⎝ ⎠ ⎝ ⎠⎨⎩
• Average value of the parameter over any area is given by the integral of P(x,y) over this area.
• Actual mismatch is given by the difference of two integrals
• This integral can be interpreted as the convolution of a geometry function with the “mismatch source” function P(x,y)
( ) ( )( )
( )( )1 1 2 2
12 12, ,
1, ', ' ' ' ', ' ' 'area x y area x y
P x y P x y dx dy P x y dx dyarea
⎧ ⎫⎪ ⎪∆ = −⎨ ⎬⎪ ⎪⎩ ⎭∫∫ ∫∫
x
(x12,y12)
(x1,y1) (x2,y2)
W
L
Dx
( ) ( ) ( ), , ,x y x y x yω ω ω ω ω ω∆ = ⋅P G P
†
† M. Pelgrom, A. Duinmaijer and A. Welbers, “Matching Properties of MOS Transistors,”, IEEE J. Solid-state Circuits, Vol.24, No. 5, pp.1433-1439, Oct. 1989.
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First Source of Variation – White Noise• The events have a correlation distance much smaller than the
transistor dimensions.• In Fourier domain it is a constant value for all spatial frequencies
• The assumption of short correlation distance implies that no relation exists between matching and the spacing D between two transistors.
( )2
2 PAPWL
σ ∆ =
( ) ( ) ( )222
2
1 , ,4
y x
y xx y x y x yP d d
ω ω
ω ωσ ω ω ω ω ω ω
π=∞ =∞
=−∞ =−∞∆ = ⋅∫ ∫ G P
But what if W and L are also variable?
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Additional Sources of Variation are Deterministic• Systematic error from across wafer variations• Systematic error from within field variations
– Scanner optics / mechanics– Mask errors– Pattern densities (in Litho, Etch, CMP, Anneal, etc.)– And, of course, LER…
( )2 2 2P xP S Dσ ∆ =
P
Wafer diameter
+ ?How do we deal with the complexity of the deterministic functions?
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Device Model and Yield under LER
Source
Drain
Li-1 Li+1Li
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FinFET LER
+ =
Body
Gate
AB
Ch
t
L
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FinFET LER
AB
C
A
C
B
h
t
h
L
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FinFET LER Issues• Hot carrier reliability• Mobility degradation due to surface scattering
– Si FinFET vs. TFT• Ioff and Ion variations due to LER• Orientation effects• Poly-Si vs. sc-Si
– TFT vs. bulk
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Transfer of LER• Transfer of LER from resist
film onto underlying film is a multi-step process
• Furthermore, the junction edges of tip and halo implants is redefine the LER underneath the etched gate stack
Schematic of a typical gate stack
Resist
Poly-SiGate Dielectric
Substrate
Hard MaskBARC
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Outline
• CD Control• CD Modeling• IC Performance Impact• New Directions
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In Summary• CD (and many other, equally critical elements)
vary in a complex manner• We are observability- and controllability-limited• Major efforts are under way to
– Enhance the metrology capability– Reform and expand the models of variability– Incorporate variability modeling into DFM tool
• We are bringing in enhanced CD metrology capability by the donation of the Timbre/TEL ODP tool