Copyright Agrawal, 2011Copyright Agrawal, 2011 ELEC5270/6270 Spring 11, Lecture 7ELEC5270/6270 Spring 11, Lecture 7 11
ELEC 5270/6270 Spring 2011ELEC 5270/6270 Spring 2011Low-Power Design of Electronic CircuitsLow-Power Design of Electronic Circuits
Energy Source DesignEnergy Source Design
Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor
Dept. of Electrical and Computer EngineeringDept. of Electrical and Computer EngineeringAuburn University, Auburn, AL 36849Auburn University, Auburn, AL 36849
[email protected]://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr11/course.html
OutlineOutline Energy source optimization methodsEnergy source optimization methods
Voltage and Clock Management Voltage and Clock Management Functional ManagementFunctional Management
Voltage and Clock Management (DVFS)Voltage and Clock Management (DVFS) BackgroundBackground
A typical system powered with batteryA typical system powered with battery Battery Simulation ModelBattery Simulation Model DC to DC converterDC to DC converter
Problem statementProblem statement Case I : System is Performance boundCase I : System is Performance bound Case II : A higher battery lifetime is requiredCase II : A higher battery lifetime is required Case III : Battery weight or size is constrainedCase III : Battery weight or size is constrained
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Energy Source Optimization MethodsEnergy Source Optimization Methods
• Dynamic Voltage Management • Multi-Voltage design
• Dynamic Frequency Management • Retiming
• Fetch Throttling• Dynamic Task Scheduling • Instruction Slowdown• Low Power solutions to common operations e.g. Low Power FSMs, Bus Encoding etc
• Dynamic Voltage and Frequency Scaling (DVFS)
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Energy Source Optimization MethodsEnergy Source Optimization Methods
Dynamic Voltage and Frequency Scaling (DVFS)
Instruction Slowdown Method
in Processors
Parallel Architectures
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Powering a SystemPowering a System
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VB +_
RB
VLRL
IL
AHr(capacity)
Ideal lifetime = AHr/IL = AHr.RB (1 + RL/RB) / VB
Power supplied to load, PL = IL2 RL = (VB
2/RB)(RL/RB) / (1+ RL/RB)2
Efficiency = PL / Battery Power = (1+ RB/RL) –1
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Lifetime, Power and EfficiencyLifetime, Power and Efficiency
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1.0
0.8
0.6
0.4
0.2
0.0
Eff
icie
ncy
or P
ower
0 1 2 3 4 5 6 7 8RL/RB
Life
time
(x A
Hr.
RB /
VB)
10
8
6
4
2
0
Lifetime
Efficiency
PL = VB2/(4RB)
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Maximum power transfer theorem
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Power Subsystem of an Electronic SystemPower Subsystem of an Electronic System
DC – DCVoltage
Converter
Electronic System
4.2 V to 3.5 V Lithium- ion
BatteryDecoupling Capacitor
VDD
GND
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Some CharacteristicsSome Characteristics
Lithium-ion batteryOpen circuit voltage: 4.2V, unit cell 400mAHr, for
efficiency ≥ 85%, current ≤ 1.2ADischarged battery voltage ≤ 3.0V
DC-to-DC converterSupplies VDD to circuit, VDD ≤ 1V for nanometer
technologies.VDD control for energy management.
Decoupling capacitor(s) provide smoothing of time varying current of the circuit.
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Battery Simulation ModelBattery Simulation ModelLithium-ion battery, unit cell capacity: N = 1 (400mAHr)Battery sizes, N = 2 (800mAHr), N = 3 (1.2AHr), etc.
Ref: M. Chen and G. A. Rincón-Mora, “Accurate Electrical Battery Model Capable of Predicting Runtime and I-V Performance,” IEEE Transactions on Energy Conversion, vol. 21, no. 2, pp. 504–511, June 2006.
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Model: Battery Lifetime PartModel: Battery Lifetime Part
SOC: State of chargeSOC: State of charge VVSOCSOC = 1 volt, for fully charged battery. = 1 volt, for fully charged battery.
CCCapacityCapacity = 3600 = 3600 ✕ AHr-rating ✕ f(Cycles) ✕ f(Temp)✕ AHr-rating ✕ f(Cycles) ✕ f(Temp) f(Cycles), f(Temp): effects of dropping capacity f(Cycles), f(Temp): effects of dropping capacity
with number of recharges and temperature. with number of recharges and temperature. Both are close to 1.Both are close to 1.
RRself-Dschargeself-Dscharge : A large leakage resistance. : A large leakage resistance.
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Voltage-Current CharacteristicVoltage-Current CharacteristicDetermined from experimental data.Determined from experimental data.Open circuit voltage:Open circuit voltage:
V = V = −1.031e−1.031e−35×SOC−35×SOC + 3.685 + 0.2156 × SOC + 3.685 + 0.2156 × SOC −0.1178 × SOC−0.1178 × SOC22 + 0.3201 × SOC + 0.3201 × SOC33
RRSeriesSeries = 0.07446 + 0.1562 e = 0.07446 + 0.1562 e – – 24.3724.37××SOCSOC Other resistance and capacitance are also Other resistance and capacitance are also
non-linear functions of SOC and represent non-linear functions of SOC and represent short-term (S) and long-term (L) transient short-term (S) and long-term (L) transient effects.effects.
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Lifetime from Battery SimulationLifetime from Battery Simulation
1008 sec
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Battery EfficiencyBattery EfficiencyConsider:
1.2AHr batteryIBatt = 3.6AIdeal Lifetime = 1.2AHr/3.6A
= 1/3 hour (1200s)Actual lifetime from simulation = 1008sEfficiency = (Actual lifetime)/(Ideal lifetime)
= 1008/1200
= 0.84 or 84%
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DC-to-DC Buck (Step-Down) ConverterDC-to-DC Buck (Step-Down) Converter Components:
Switch (FETs, VDMOS), diode, inductor, capacitor.
Switch control: pulse width modulated (PWM) signal.
Vs = D · Vg,
D is duty cycle of PWM control signal.
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Source: R. W. Erickson, “DC to DC Power Converters, “ Wiley Encyclopedia of Electrical and Electronics Engineering
s
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Asynchronous DC-to-DC Buck ConverterAsynchronous DC-to-DC Buck Converter
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Vref
+
–
L
C LoadVg
V
An Electronic System ExampleAn Electronic System Example
A 32-bit Ripple Carry Adder (RCA) 352 NAND gates (2 or 3 inputs) 1,472 transistors
In order to realize a practical circuit and to generate sufficient current for the battery model, 200,000 copies of RCA were used.
That makes it 352 x 200,000 ≈ 70 million gate circuit.
Critical path: 32bit ripple-carry adder. 45nm bulk CMOS technology, PTM models [4].Copyright Agrawal, 2011Copyright Agrawal, 2011 1616ELEC5270/6270 Spring 11, Lecture 7ELEC5270/6270 Spring 11, Lecture 7
HSPICE Simulation of 32-Bit RCA, VDD = 0.9V HSPICE Simulation of 32-Bit RCA, VDD = 0.9V
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Average total current, Icircuit = 74.32μA, Leakage current = 1.108μA100 random vectors including critical path vectors
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Critical path vectors
2ns
32-bit Ripple Carry Adder32-bit Ripple Carry Adder
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A0 B0 C0=0
C1 S0
A1 B1
C2 S1
A31 B31
C32 S31
Critical Path VectorsCritical Path Vectors
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Vector 1 C = 0000000000000000000000000000000A = 11111111111111111111111111111111B = 00000000000000000000000000000000S = 11111111111111111111111111111111
Vector 2 C = 1111111111111111111111111111111A = 11111111111111111111111111111111B = 00000000000000000000000000000001S = 00000000000000000000000000000000
HSPICE Simulation of 32-Bit RCA, VDD = 0.3V HSPICE Simulation of 32-Bit RCA, VDD = 0.3V
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Average total current, Icircuit = 0.2563μA, Leakage current = 0.092μA
100 random vectors including critical path vectors
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Critical path vectors
200ns
Finding Battery Current, IFinding Battery Current, IBattBatt
Assume 32-bit ripple carry adder (RCA) with about 350 gates represents circuit activity for the entire system.
Total current for 70 million gate circuit,
Icircuit = (average current for RCA) x 200,000
DC-to-DC converter translates VDD to 4.2V battery voltage; assuming 100% conversion efficiency,
IBatt = Icircuit x VDD/4.2
Example: HSPICE simulation of RCA: 100 random vectors VDD = 0.9V, vector period = 2ns, Average current for RCA = 74.32μA, IBatt = 3.18A
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Case I: PerformanceCase I: Performance
Battery should be capable of supplying power (current) for required system performance.
Battery should meet the lifetime (time between replacement or recharge) requirement.
Power management to extend the lifetime of selected battery.
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System is Performance Bound
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Step 1: Determine the operating voltage based on required performance.
Step 2: Determine minimum battery size for efficiency ≥ 85%
Step 3: Increase battery size over the minimum size to meet lifetime requirement.
Step 4: Determine a lower performance mode with maximum lifetime for a given battery.
Four Step DesignFour Step Design
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Step 1: Find Operating VoltageStep 1: Find Operating Voltage
Consider a performance requirement of 200MHz clock, critical path delay ≤ 5ns.
Circuit simulation gives,
VDD = 0.6V and IBatt = 477mA.
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Determine Operating Voltage for System Performance Requirement
200 MHz
477 mA
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Step 2: Determine Minimum Battery Size• For required current 477 mA• Battery Efficiency ≥ 85 % Select
400 mAHr Battery
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Simulating Selected BatterySimulating Selected Battery
A meaningful measure of the work done by the battery is its lifetime in terms of clock cycles.
For each VDD in the range of valid operation, i.e., VDD = 0.1V to 1.0V, we calculate lifetime using circuit delay and battery efficiency obtained from HSPICE simulation.
Minimum energy operation maximizes the lifetime in clock cycles.
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Higher Circuit Speed,Lower Battery Efficiency
Higher Battery Lifetime,Lower Circuit Speed
DVFS range
Simulation of 400mAHr BatterySimulation of 400mAHr Battery• Over entire operating voltage range of 0.1 V to 1 V• For both Ideal and Simulated battery
0.098 0.560 3.860 23.00 88.00 199.0 325.0 446.0 557.0 657.0 (MHz)
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Step 3: Battery Lifetime RequirementStep 3: Battery Lifetime Requirement
Suppose battery lifetime for the system is to be at least 3 hours.
For smallest battery, size N = 1 (400mAHr)
IBatt = 477mA,
Efficiency ≈ 98%,
Lifetime = 0.98 x 0.4/0.477 = 0.82 hour For 3 hours lifetime, battery size
N = 3/0.82 = 3.65 ≈ 4. We should use a 4 cell (1600mAHr) battery.Copyright Agrawal, 2011Copyright Agrawal, 2011 2929
System needs higher battery lifetime
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619 x109 clock cycles,50 minutes
2540x109 clock cycles205 min ( > 3 Hrs)
Meeting Lifetime RequirementMeeting Lifetime Requirement
0.098 0.560 3.860 23.00 88.00 199.0 325.0 446.0 557.0 657.0 (MHz)
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Step 4: Minimum Energy OperationStep 4: Minimum Energy Operation
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1660x109 clock cycles
6630x109 clock cycles
0.098 0.560 3.860 23.00 88.00 199.0 325.0 446.0 557.0 657.0 (MHz)
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Summarizing Power ManagementSummarizing Power Management
Battery sizeVDD = 0.6V, 200MHz VDD = 0.3V, 3.86MHz
Effici.%
LifetimeEffici.
%
Lifetime
N mAHrx103
secondsX10 9
cycles x103
secondsX10 9 cycles
1 400 98 3 619 100+ 414.5 1660
4 1600 100+ 12.3 2540 100+ 1364 6630
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> two-times
1. Battery size should match the current need and satisfythe lifetime requirement of the system:(a) Undersize battery has poor efficiency.(b) Oversize battery is bulky and expensive.
2 Minimum energy mode can significantly increase battery lifetime.
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Battery Size or Weight is Constrained
1. Some real life applications call for a fixed size (or weight) of a battery, e.g., bio-implantable devices, hearing aid.
2 Performance requirements are secondary and the primary goal is to maximize the lifetime (or number of cycles before next recharge).
3 Example:A CR2032(CR) Lithium-ion batteryNominal Voltage: 3VCapacity: 225mAHrNominal Current: 0.3 mAMaximum Current: 3 mA
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540x109 clock cycles
0.098 0.560 3.860 23.00 88.00 199.0 325.0 446.0 557.0 657.0 (MHz)
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ReferencesReferences1. M. Pedram and Q. Wu, “Design Considerations for Battery-Powered
Electronics,” Proc. 36th Design Automation Conference, June 1999, pp. 861– 866.
2. L. Benini, G. Castelli, A. Macii, E. Macii, M. Poncino, and R. Scarsi, “A Discrete-Time Battery Model for High-Level Power Estimation,” Proc. Conference on Design, Automation and Test in Europe, Mar. 2000, pp. 35 – 41.
3. M. Chen and G. A. Rincón-Mora, “Accurate Electrical Battery Model Capable of Predicting Runtime and I-V Performance,” IEEE Transactions on Energy Conversion, vol. 21, no. 2, pp. 504 – 511, June 2006.
4. Simulation model: 45nm bulk CMOS, predictive technology model (PTM), http://ptm.asu.edu/
5. Simulator: Synopsys HSPICE, www.synopsys.com/Tools/Verification/AMSVerification/CircuitSimulation/HSPICE/Documents/hspice ds.pdf Copyright Agrawal, 2011Copyright Agrawal, 2011 3535ELEC5270/6270 Spring 11, Lecture 7ELEC5270/6270 Spring 11, Lecture 7
6. M. Kulkarni, and V. D. Agrawal, “Matching Power Source to Electronic System: A Tutorial on Battery Simulation”, Proc. VLSI Design and Test Symposium, July 2010.
7. M. Kulkarni and V. D. Agrawal, “Energy Source Lifetime Optimization Energy Source Lifetime Optimization for a Digital System through Power Management,” for a Digital System through Power Management,” Proc. Proc. IEEE Proc. Proc. IEEE International Conf. Industrial Technology and 43rd IEEE Southeastern International Conf. Industrial Technology and 43rd IEEE Southeastern Symp. System TheorySymp. System Theory, March 2011., March 2011.
8. M. Kulkarni, S. Sheth and V. D. Agrawal, “Architectural Power Architectural Power Management for High Leakage Technologies,” Management for High Leakage Technologies,” Proc. Proc. IEEE Proc. Proc. IEEE International Conf. Industrial Technology and 43rd IEEE Southeastern International Conf. Industrial Technology and 43rd IEEE Southeastern Symp. System TheorySymp. System Theory, March 2011., March 2011.
9. M. Kulkarni, “Energy Source Lifetime Optimization for a Digital System Energy Source Lifetime Optimization for a Digital System through Power Management,” through Power Management,” Master’s ThesisMaster’s Thesis, ECE Dept., Auburn , ECE Dept., Auburn University, December 2010.University, December 2010.
10.10. K. Sheth, “A Hardware-Software Processor Architecture using Pipeline K. Sheth, “A Hardware-Software Processor Architecture using Pipeline Stalls for Leakage Power Management,” Stalls for Leakage Power Management,” Master’s ThesisMaster’s Thesis, ECE Dept., , ECE Dept., Auburn University, December 2008.Auburn University, December 2008.
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References (Cont.)References (Cont.)
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