8/17/06 ELEC 5970-003/6970-003 Lecture 1 1 ELEC 5970-003/6970-003 (Fall 2006) Low-Power Design of Electronic Circuits (ELEC 5270/6270) Introduction Vishwani

8/17/068/17/06 ELEC 5970-003/6970-003 Lecture 1ELEC 5970-003/6970-003 Lecture 1 11

ELEC 5970-003/6970-003 (Fall 2006)ELEC 5970-003/6970-003 (Fall 2006)Low-Power Design of Electronic CircuitsLow-Power Design of Electronic Circuits

(ELEC 5270/6270)(ELEC 5270/6270)

IntroductionIntroduction

Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor

Department of Electrical and Computer Department of Electrical and Computer EngineeringEngineering

Auburn UniversityAuburn Universityhttp://www.eng.auburn.edu/~vagrawalhttp://www.eng.auburn.edu/~vagrawal

[email protected]@eng.auburn.edu

http://www.eng.auburn.edu/~vagrawal

mailto:[email protected]


Course ObjectiveCourse Objective

Low-power is a current need in VLSI Low-power is a current need in VLSI design.design.

Learn basic ideas, concepts and Learn basic ideas, concepts and methods.methods.

Gain hands-on experience.Gain hands-on experience.


Student EvaluationStudent Evaluation

Homework (30%) ~ FourHomework (30%) ~ Four Class Project (30%)Class Project (30%) Student presentation (10%)Student presentation (10%) Final Exam (30%)Final Exam (30%)


IntroductionIntroduction

Why is it a concern?

Power Consumption of VLSI Chips


ISSCC, Feb. 2001, KeynoteISSCC, Feb. 2001, Keynote“Ten years from now, microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second – about the same number of calculations that the world's fastest supercomputer can perform now.

“Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor. . . .”

Patrick P. Gelsinger Senior Vice PresidentGeneral ManagerDigital Enterprise Group INTEL CORP.


VLSI Chip Power DensityVLSI Chip Power Density

40048008

80808085

8086

286386

486Pentium®

P6

1

10

100

1000

10000

1970 1980 1990 2000 2010

Year

Po

wer

Den

sity

(W

/cm

2 )

Hot Plate

NuclearReactor

RocketNozzle

Sun’sSurface

Source: Intel


SIA Roadmap for Processors SIA Roadmap for Processors (1999)(1999)

YearYear 19991999 20022002 20052005 20082008 20112011 20142014

Feature size (nm)Feature size (nm) 180180 130130 100100 7070 5050 3535

Logic Logic transistors/cmtransistors/cm22 6.2M6.2M 18M18M 39M39M 84M84M 180M180M 390M390M

Clock (GHz)Clock (GHz) 1.251.25 2.12.1 3.53.5 6.06.0 10.010.0 16.916.9

Chip size (mmChip size (mm22)) 340340 430430 520520 620620 750750 900900

Power supply (V)Power supply (V) 1.81.8 1.51.5 1.21.2 0.90.9 0.60.6 0.50.5

High-perf. Power High-perf. Power (W)(W) 9090 130130 160160 170170 175175 183183

Source: http://www.semichips.org

http://www.semichips.org/


Defining Low-Power DesignDefining Low-Power Design

Design practices that reduce power Design practices that reduce power consumption at least by one order of consumption at least by one order of magnitude; in practice 50% reduction is often magnitude; in practice 50% reduction is often acceptable.acceptable.

General topicsGeneral topics Algorithms and architecturesAlgorithms and architectures High-level and software techniquesHigh-level and software techniques Gate and circuit-level methodsGate and circuit-level methods Power estimation techniquesPower estimation techniques Test powerTest power


Specific Topics in Low-PowerSpecific Topics in Low-Power Power dissipation in CMOS circuitsPower dissipation in CMOS circuits Device technologyDevice technology

Low-power CMOS technologiesLow-power CMOS technologies Energy recovery methodsEnergy recovery methods

Circuit and gate level methodsCircuit and gate level methods Logic synthesisLogic synthesis Dynamic power reduction techniquesDynamic power reduction techniques Leakage power reductionLeakage power reduction

System level methodsSystem level methods MicroprocessorsMicroprocessors Arithmetic circuitsArithmetic circuits Low power memory technologyLow power memory technology

Test PowerTest Power Power estimationPower estimation


Power in a CMOS GatePower in a CMOS GateVVDDDD

iiDDDD(t)(t)

GroundGround


Power Dissipation in Power Dissipation in CMOS Logic (0.25µ)CMOS Logic (0.25µ)

%75 %5%20

PPtotaltotal (0→1) = (0→1) = CCLL V VDDDD22

+ + ttscscVVDDDD I Ipeakpeak ++ VVDDDDIIleakageleakage

CL


Power and EnergyPower and Energy Instantaneous power (Watts)Instantaneous power (Watts)

P P ((t t ) = ) = iiDD DD (t t ) ) VVDDDD

Peak power (Watts)Peak power (Watts)

PPpeakpeak = Max { = Max {P P ((t t )})} Average power (Watts)Average power (Watts)

PPavav = [ = [ ∫∫00

TT P P ((t t ) ) dt dt ] ] / T/ T

Energy (Joules)Energy (Joules)

E = ∫E = ∫00

TT P P ((t t ) ) dtdt


Components of PowerComponents of Power

DynamicDynamic Signal transitionsSignal transitions

Logic activityLogic activity GlitchesGlitches

Short-circuitShort-circuit StaticStatic

LeakageLeakage


Power of a TransitionPower of a Transition

VVDDDD

GroundGround

C

R

R

Power

= CVDD2/2


Logic Activity and GlitchesLogic Activity and Glitches

45

7

61

2

3

d=2d=1 d=1

d=1


Low-Power Design Low-Power Design TechniquesTechniques

Circuit and gate level methodsCircuit and gate level methods Reduced supply voltageReduced supply voltage Adiabatic switching and charge Adiabatic switching and charge

recoveryrecovery Logic design for reduced activityLogic design for reduced activity Reduced GlitchesReduced Glitches Transistor sizingTransistor sizing Pass-transistor logicPass-transistor logic Pseudo-nMOS logicPseudo-nMOS logic Multi-threshold gatesMulti-threshold gates


Low-Power Design Low-Power Design TechniquesTechniques

Functional and architectural Functional and architectural methodsmethods

Clock suppressionClock suppression Clock frequency reductionClock frequency reduction Supply voltage reductionSupply voltage reduction Power downPower down Algorithmic and Software methodsAlgorithmic and Software methods


Test PowerTest Power Power grid on a VLSI chip is designed Power grid on a VLSI chip is designed

for certain current capacity during for certain current capacity during functional operation:functional operation: Average current → heat dissipationAverage current → heat dissipation Peak current → noise, ground bouncePeak current → noise, ground bounce

Problem – Tests like scan or BIST are Problem – Tests like scan or BIST are nonfunctional and may cause higher nonfunctional and may cause higher than the functional circuit activity; a than the functional circuit activity; a functionally good chip can fail the functionally good chip can fail the test.test.


Power Estimation MethodsPower Estimation Methods Spice: Accurate but expensiveSpice: Accurate but expensive Logic-levelLogic-level

Event-driven simulationEvent-driven simulation StatisticalStatistical ProbabilisticProbabilistic

High-level: HierarchicalHigh-level: Hierarchical


Books on Low-Power Design Books on Low-Power Design (1) (1) L. Benini and G. De Micheli, L. Benini and G. De Micheli, Dynamic Power Management Design Dynamic Power Management Design

Techniques and CAD ToolsTechniques and CAD Tools, Boston: Springer, 1998., Boston: Springer, 1998. T. D. Burd and R. A. Brodersen, T. D. Burd and R. A. Brodersen, Energy Efficient Microprocessor Energy Efficient Microprocessor

DesignDesign, Boston: Springer, 2002., Boston: Springer, 2002. A. Chandrakasan and R. Brodersen, A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS DesignLow-Power Digital CMOS Design, ,

Boston: Springer, 1995.Boston: Springer, 1995. A. Chandrakasan and R. Brodersen, A. Chandrakasan and R. Brodersen, Low-Power CMOS DesignLow-Power CMOS Design, New York: , New York:

IEEE Press, 1998.IEEE Press, 1998. J.-M. Chang and M. Pedram, J.-M. Chang and M. Pedram, Power Optimization and Synthesis at Power Optimization and Synthesis at

Behavioral and System Levels using Formal MethodsBehavioral and System Levels using Formal Methods, Boston: , Boston: Springer, 1999.Springer, 1999.

M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, Advanced Low-Power Advanced Low-Power Digital Circuit TechniquesDigital Circuit Techniques, Boston: Springer, 1997., Boston: Springer, 1997.

R. Graybill and R. Melhem, R. Graybill and R. Melhem, Power Aware ComputingPower Aware Computing, New York: Plenum , New York: Plenum Publishers, 2002.Publishers, 2002.

S. Iman and M. Pedram, S. Iman and M. Pedram, Logic Synthesis for Low Power VLSI DesignsLogic Synthesis for Low Power VLSI Designs, , Boston: Springer, 1998.Boston: Springer, 1998.

J. B. Kuo and J.-H. Lou, J. B. Kuo and J.-H. Lou, Low-Voltage CMOS VLSI CircuitsLow-Voltage CMOS VLSI Circuits, New York: , New York: Wiley-Interscience, 1999.Wiley-Interscience, 1999.

J. Monteiro and S. Devadas, J. Monteiro and S. Devadas, Computer-Aided Design Techniques for Computer-Aided Design Techniques for Low Power Sequential Logic CircuitsLow Power Sequential Logic Circuits, Boston: Springer, 1997., Boston: Springer, 1997.

S. G. Narendra and A. Chandrakasan, S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Leakage in Nanometer CMOS TechnologiesTechnologies, Boston: Springer, 2005., Boston: Springer, 2005.

W. Nebel and J. Mermet, W. Nebel and J. Mermet, Low Power Design in Deep Submicron Low Power Design in Deep Submicron ElectronicsElectronics, Boston: Springer, 1997., Boston: Springer, 1997.


Books on Low-Power Design Books on Low-Power Design (2)(2) N. Nicolici and B. M. Al-Hashimi, N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI CircuitsPower-Constrained Testing of VLSI Circuits, ,

Boston: Springer, 2003.Boston: Springer, 2003. V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, Digital Digital

System Clocking: High Performance and Low-Power AspectsSystem Clocking: High Performance and Low-Power Aspects, Wiley-IEEE, , Wiley-IEEE, 2005.2005.

M. Pedram and J. M. Rabaey, M. Pedram and J. M. Rabaey, Power Aware Design MethodologiesPower Aware Design Methodologies, Boston: , Boston: Springer, 2002.Springer, 2002.

C. Piguet, C. Piguet, Low-Power Electronics DesignLow-Power Electronics Design, Boca Raton: Florida: CRC Press, , Boca Raton: Florida: CRC Press, 2005.2005.

J. M. Rabaey and M. Pedram, J. M. Rabaey and M. Pedram, Low Power Design MethodologiesLow Power Design Methodologies, Boston: , Boston: Springer, 1996.Springer, 1996.

S. Roudy, P. K. Wright and J. M. Rabaey, S. Roudy, P. K. Wright and J. M. Rabaey, Energy Scavenging for Wireless Energy Scavenging for Wireless Sensor NetworksSensor Networks, Boston: Springer, 2003., Boston: Springer, 2003.

K. Roy and S. C. Prasad, K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit DesignLow-Power CMOS VLSI Circuit Design, New York: , New York: Wiley-Interscience, 2000.Wiley-Interscience, 2000.

E. Sánchez-Sinencio and A. G. Andreaou, E. Sánchez-Sinencio and A. G. Andreaou, Low-Voltage/Low-Power Integrated Low-Voltage/Low-Power Integrated Circuits and Systems – Low-Voltage Mixed-Signal CircuitsCircuits and Systems – Low-Voltage Mixed-Signal Circuits, New York: IEEE , New York: IEEE Press, 1999.Press, 1999.

W. A. Serdijn, W. A. Serdijn, Low-Voltage Low-Power Analog Integrated CircuitsLow-Voltage Low-Power Analog Integrated Circuits, , Boston:Springer, 1995.Boston:Springer, 1995.

S. Sheng and R. W. Brodersen, S. Sheng and R. W. Brodersen, Low-Power Wireless Communications: A Low-Power Wireless Communications: A Wideband CDMA System DesignWideband CDMA System Design, Boston: Springer, 1998., Boston: Springer, 1998.

G. Verghese and J. M. Rabaey, G. Verghese and J. M. Rabaey, Low-Energy FPGAsLow-Energy FPGAs, Boston: springer, 2001., Boston: springer, 2001. G. K. Yeap, G. K. Yeap, Practical Low Power Digital VLSI DesignPractical Low Power Digital VLSI Design, Boston:Springer, 1998., Boston:Springer, 1998. K.-S. Yeo and K. Roy, K.-S. Yeo and K. Roy, Low-Voltage Low-Power SubsystemsLow-Voltage Low-Power Subsystems, McGraw Hill, , McGraw Hill,

2004.2004.


Other Books Useful inOther Books Useful inLow-Power Design Low-Power Design

A. Chandrakasan, W. J. Bowhill and F. Fox, A. Chandrakasan, W. J. Bowhill and F. Fox, Design of High-Design of High-Performance Microprocessor Circuits, Performance Microprocessor Circuits, New York: IEEE New York: IEEE Press, 2001.Press, 2001.

N. H. E. Weste and D. Harris, N. H. E. Weste and D. Harris, CMOS VLSI Design, Third CMOS VLSI Design, Third EditionEdition, Reading, Massachusetts, Addison-Wesley, 2005., Reading, Massachusetts, Addison-Wesley, 2005.

S. M. Kang and Y. Leblebici, S. M. Kang and Y. Leblebici, CMOS Digital Integrated CMOS Digital Integrated CircuitsCircuits, New York: McGraw-Hill, 1996., New York: McGraw-Hill, 1996.

E. Larsson, E. Larsson, Introduction to Advanced System-on-Chip Introduction to Advanced System-on-Chip Test Design and OptimizationTest Design and Optimization, Springer, 2005., Springer, 2005.

J. M. Rabaey, A. Chandrakasan and B. Nikolić, J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Digital Integrated Circuits, Second EditionIntegrated Circuits, Second Edition, Upper Saddle , Upper Saddle River, New Jersey: Prentice-Hall, 2003.River, New Jersey: Prentice-Hall, 2003.

J. Segura and C. F. Hawkins, J. Segura and C. F. Hawkins, CMOS Electronics, How It CMOS Electronics, How It Works, How It FailsWorks, How It Fails, New York: IEEE Press, 2004. , New York: IEEE Press, 2004.

Documents

8/17/06 ELEC 5970-003/6970-003 Lecture 1 1 ELEC 5970-003/6970-003 (Fall 2006) Low-Power Design of Electronic Circuits (ELEC 5270/6270) Introduction Vishwani