CMS SLHC tracker, Feb 2007 1
1) some ideas on front end architectures for short strip readout
concentrating mainly on power issues
2) outline of plans for 3 year work program to develop a FE readout chip
CMS Outer Tracker Readout at SLHC
Mark Raymond – Imperial College
CMS SLHC tracker, Feb 2007 2
CMS LHC tracker FE system
current tracker readout analogue custom link driver chip at 40 Ms/s FED digitizes at 10 bits/sample
SLHC will most likely use fast (multi-Gbit/s) serial digital links
following industrial developmentsfor digital data transmission
can only retain analogue info if low power ADC on front end
CMS SLHC tracker, Feb 2007 3
SLHC FE architecture
generic pipeline chip architecture – where to go digital?
128:1 muxFE amp
pipelinereadoutpipeline
A) before pipelineADC on every channel – power issuesdigital multi-bit pipelinefast FE to achieve single bunch resolution
A
B
other possible FE chip featureson-chip sparsification
keep option open - maybe better to do further up the readout chain?
L1 trigger contributioncan short strip layers provide anything useful?would certainly place significant constraints on FE chip architecture
B) after muxADC power shared by 128 channelsanalog pipeline, analog muxcould keep slow FE + decon pipeline readout
serial digital O/P
ADC power drives choice of A or B
CMS SLHC tracker, Feb 2007 4
ADC power consumption
ADC power given by process,Effective No. Of Bits, andconversion frequency
based on general considerations(individual architecture dependent)
*from A. Marchioro talk at 2nd SLHC workshop
International Technology Roadmapfor Semiconductors (ITRS-2003) (forecast from the semiconductor industry with 15 year perspective)
*
90
130nm 65nm
8bits 6.4 2.5
6bits 1.6 0.6
ADC power @ 20 MHz [mW]ADC on every FE channel hard to do
8 bits @ 20 MHz -> 6.4 mW (0.13m)
ADC on every FE chip quite possible
6.4/128 -> 50 W/chan
CMS SLHC tracker, Feb 2007 5
front end power
how much power can be saved 0.25 -> 0.13?
can estimate, but learn more by trying to translate circuits
e.g. will show here results for APV preamp/shaper circuit
have tried to make straightforward translationbut one main difference for preamp
APV25: 3 supply rails (0, 1.25V, 2.5V)1.25V included to save power400μA (1.25V), 110 μA (2.5V) = 0.78 mW
propose not to do this again for SLHC use 2 rails only, 0 and 1.2V, and accept power penalty
APV25
0.13m
2.5V
1.25V
1.2V
1.2V
CMS SLHC tracker, Feb 2007 6
preamp/shaper design (1)
APV25 0.13m
460uA
60uA
50uA
50uA100uA
50uA25uA
10uA
25uA
noise & speed depend on input device transconductance (gain) gm
noise CDET/√gm
risetime CDETCL/Cfgm
shorter strips -> smaller CDET so lower gm tolerable
if choose to accept ~ factor 2 increase in noise slope (over APV25) then gm(0.13) = gm(0.25)/4
simulations show this achieved for ~ 100 A in 0.13 I/P device (W/L = 1000/0.24)
total preamp power (including source follower) = 125 A x 1.2 V = 0.15 mW
factor ~ 5 reduction from 0.78 mW (APV25 preamp only)
Preamp
gm COX(W/L)IDS S.I.
IDS W.I.
Cf
CL
CDET Cfs
CC CDET
Cf
CL
CC
Cfs
CMS SLHC tracker, Feb 2007 7
preamp/shaper design (2)
460uA
60uA
50uA
50uA100uA
50uA25uA
10uA
25uA
0.13 m architecture identical to APV25, 50 ns time const.
keep gain as high as possible
80 mV/mip c.f. 100 mV/mip for APV25 (1 mip = 4 fC here)
makes best use of available dynamic range, but will only work for one polarity (-ve input signal)
=> need alternative architecture for p-strip signals
total 0.13 m shaper power 42 W
factor 6 reduction from 250 W (APV25)
shaper
APV25
Cf
CL
CDET Cfs
CC
0.13m
CDET
Cf
CL
CC
Cfs
CMS SLHC tracker, Feb 2007 8
0.13 preamp/shaper simulated performance
1200
1000
800
600
400
200
0
EN
C [
e]
151050-5
Cadded [pF]0.98
0.96
0.94
0.92
0.90
0.88
0.86
[vo
lts]
50 ns/div.
13.5 pF 9 pF 4.5 pF 1.5 pF
1.0
0.9
0.8
0.7
0.6
[vo
lts]
50 ns/div.
1 - 5 mips ideal 50 ns CR-RC
simulated noise slope ~ 70 e/pF => I/P device noise=> input spectral density ~ 2.6 nV/√Hz, comparesquite well with transistor measurement ~ 2 nV//√Hz
with pulse shape tuning can cope with strips up to ~ 10 cm
overall preamp/shaper power consumption reduction 1.025 mW (APV25) -> 0.192 mW (0.13 m)
factor ~ 5
pulse shape vs. signal size
pulse shape vs. Cadded
noise vs. Cadded
CMS SLHC tracker, Feb 2007 9
further up the readout chain
digital link interface functionality
multiplexingsparsification here maybe?encoding and fast serialization
how many front end chips/ link? (currently 2 APVs/fibre)
depends on output link speed and data volume/FE chip
off-detector
slow(ish) digitalserial data
FE chips
CMS SLHC tracker, Feb 2007 10
some data rate numbers
L1 trigger rate 100 kHz, 10 sec spacing (on average)
current APV data frame duration 7 sec for 140 samples
digitize at 8 bits -> 1120 bits to shift out in 7 sec = 160 Mbits/sec
• this would be the transmission speed at FE chip output without sparsification
if 20 FE chips / digital optical link (for example)
=> 3.2 Gbits/sec raw data
if front end sparsification (or faster links) then FE chips / link can increase
digital header
128 analogue samples
APV O/P Frame
20 MHz readout -> 7 s
CMS SLHC tracker, Feb 2007 11
3 year work program
proposed SLHC upgrade date 2015 (~ 8 years away)
large scale manufacture of components has to start much sooner
=> need tested solutions ~ 2010/11
outline here a 3 year program to develop a FE chip for short strip readout at SLHC
CMS SLHC tracker, Feb 2007 12
3 year FE chip development program
Year 1 (2007 – 8)
develop FE chip specifications (can begin now)
investigate, design and submit solutions for:
different sensor technologies (polarity, strip length, AC/DC coupling, …)several FE variants to study here
one design to suit all likely to be inefficient (and difficult!)
low power ADC architecture
… not forgetting system issues
choice of powering scheme (serial/parallel)power supply rejection (DC-DC conversion)DC balanced digital interfaces (serial powering)
definition of system interfaces (control and readout)electrical standards, digital protocols, on-chip PLL
physical design of hybrid, module and rod/petal, and manufacturing issuese.g. sensor/FE chip/hybrid interconnection (bump-bonding?)
CMS SLHC tracker, Feb 2007 13
3 year work package for front end (cont’d)
Year 2 (2008 - 9)
extensive testing program
• functionality and performance• radiation (ionizing and SEE)
review specifications
design and submit ~ complete FE chip prototype
Year 3 (2009 - 10)
more testing
prototype module construction and evaluation
details depend on availability of other components
finalize 0.13 m chip design
final submission – pre-production circuit
CMS SLHC tracker, Feb 2007 14
resources
In UK we are currently preparing bid for funds for SLHC activitiesincluding outer tracker FE chip development
main FE electronics resources required:
funds to participate in 3 MPW runs (0.13 m)design effort (RAL)
probably more options to investigate than resources can support
=> either narrow down options => or devote more resources – scope for collaboration
CMS SLHC tracker, Feb 2007 15
conclusions
FE architecture
on-chip digitization required if want to retain analog info at SLHC
ADC on every channel seems not possible in 0.13 m
ADC per FE chip (after mux) is possible
slow (50 ns) FE preamp/shaper power can reduce substantially in 0.13 m technology
still maintaining good S/N for strips up to ~ 10 cm if required
3 year work program
need to establish a funded work program to pursue:
design studies to investigate and define architectures
hardware implementations of most promising candidate architectures
We (CMS-UK) are planning to bid for funds for outer tracker FE chip development
plenty of scope for collaboration
CMS SLHC tracker, Feb 2007 16
extra
CMS SLHC tracker, Feb 2007 17
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2001751501251007550250
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2001751501251007550250
APV25 architecture reminder
128:1 muxpreamp shaperAPSPanalogue
pipeline
differentialanalogueoutput
remember existing architecture was also driven by low power original target 2 mW/chan (~2.8 achieved)
slow 50 ns CR-RC shaping helps with input stage power but preamp/inverter/shaper power still dominates
implementing deconvolution in APSP pipeline readout circuit gives single bunch resolution with no extra power
relevance to SLHC? switchable weights to APSP could allow 20/40 MHz bunch crossing frequency adaptability without much
extra complexity
inverter
20 MHzw1=1, w2=-.74, w3=.14
50 ns CR-RC
50 ns / div
40 MHzw1=1, w2=-1.21, w3=.37
0.8 mW 0.5 mW 0.25 mW 0.2 mW 0.55 mW
(digital ~0.4 mW)
CMS SLHC tracker, Feb 2007 18
Power provision
0.25 m -> 0.13 m
chip supply voltages halve, so currents double for same power consumption => 2x power dissipated in cables and 2x voltage drop along cables
solution is to deliver power at higher voltage (lower current)=> local DC-DC conversion or serial powering -> both have implications for FE chip
M1IIN
IOUT
M2 M3 Mn
serial
chain of modules at different DC voltageslinear regulation on each moduleAC or opto-coupling of signals (readout & cntrl)
parallel
DC-DCconversion
VIN
GNDM1 M2 M3 Mn
module powering more conventionalDC-DC conversion the main issueFE chip supply rejection issues?
see DC to DC Power Conversion, Ely and Garcia-Sciveres, LECC 2006 (Valencia)
CMS SLHC tracker, Feb 2007 19
0.13 m input transistor choice
input device choice determined by:
speed: O/P risetime goes as CDET/gm thermal noise: goes as CDET/√gm
CDET strip length so lower gm possible
allowable bias currents put 0.13 μm devices in W.I.
gm ID with very weak W/L dependence
rigorous (complicated) optimisation required (including power)
make some simple choices here
lets say CDET reduces factor 4, => gm can also reduce factor 4 (so noise slope increases factor 2)
choose W/L = 1000/0.24 here and ID = 100μA, -> gm > 2 mA/V (APV25 I/P device gm ~ 8 mA/V)
10
8
6
4
2
0
gm
[m
A/V
]
16001400120010008006004002000W [um]
ID=100uA
ID=200uA
ID=400uA
0.13 m gm vs. W (L=0.12,0.24,0.36,0.48)
CMS SLHC tracker, Feb 2007 20
50/25 nsec
0.96
0.94
0.92
0.90
0.88
5004003002001000x10
-9
is 25 nsec pulse shape possible without changingshaper transistor dimensions?
yes - can speed up pulse shape using Isha/vfs only
but power penalty
CDET isha(50ns) P[W] isha(25ns) P[W]
0 10 12 20 244.5 10 12 25 309 12 15 35 4213.5 14 17 50 60
50/25 ns pulse shapes for different CDET values
CMS SLHC tracker, Feb 2007 21
50/25ns simulated noise performance
1400
1200
1000
800
600
400
200
0
151050-5
50 nsec shaping 160 + 70/pF
25 nsec shaping 200 + 90/pF
EN
C [
e]
Cadded
ENC vs, Cadded
CMS SLHC tracker, Feb 2007 22
straw man detector module designs
Present CMS Si-strip tracker modules come in many different variantsdifferent sensor pitches/shapes, different #’s of FE chips/ module, different mechanical designs
What will SLHC Si-strip modules eventually look like? don’t know, but things to consider are how much can be sacrificed for manufacturabilitybump-bonding is one common theme in above examples
Choices here will affect final FE chip design (but maybe not crucial to know the answers now)
Sandro Geoff
CMS SLHC tracker, Feb 2007 23
2 nV/√Hz @ 100 A
*
* from Manghisoni et al, Noise performance of 0.13m Technologies for detector front-end applicationsIEEE Trans.Nucl.Sci. Vol.53, no.4,Aug.2006 (2456-2462)
W/L = 1000/0.24 noise spectral density measurement