The Cathode Strip Chamber Data Acquisition Electronics for CMSNuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, Volume 600, Issue 3, Pages 661-672B. Bylsma, L. Durkin, J. Gilmore, J. Gu, T. Ling, C. Rush

CSC SLHC Electronics Upgrade Overview

Stan Durkin April 23, 2004

Overall View of Data Acquisition System

Cathode Front End Board (CFEB)

Inputs Signal 96 channels input from chamber strips LCT from DMB, if CLCT is available, CLCT-->DMB--

>CFEB, if CLCT is not available, -->FTC-->DMB-->CFEB, if Calibration mode, DMB-->CFEB

L1ACC From DAQMB, - if CCB is available, CCB-->DMB-->CFEB, or CCB-->FTC-->DMB-->CFEB - if CCB is not available, FTC (LCT delay)-->DMB-->CFEB, or, DMB (LCTdelay)-->CFEB, - if Calibration mode, DMB-->CFEB;

DAC 0-5V adjustable for external, internal charge injection for BUCKEYE from DAC on DMB

BUCKEYE +10V and -5V voltage references from DMB Outputs

DAQ data Strip charge ADC data, Through 21-bit channel link to DMB

Trigger data Comparator Triads through two 28-bit multiplexers to CLCT; End channel signals to neighboring boards, analog preamp signals and digital comparator signals

Monitor Temperature sensor output, to DMB, program done Controls

Global-reset from DMB, reset DMB and CFEBs, and synchronize the 50ns clock on DMB and CFEBs

Clock 40MHz, from DMB FPGA-program from DMB, re-program the FPGA from PROM on CFEB JTAG port from DMB, controls: BUCKEYE data shift, FPGA

resets, ISP-PROM download, CFEB status monitor, etc. Downloaded Constants

PREBLOCKEND (4 bits) Block Phase Shift PROM programming data (about 500K bits); BUCKEYE working mode (normal, internal capacitor select, external, kill, 3bits/channel); Comparator timing (3 bits), working mode (2 bits) and threshold

Power +6V: for BUCKEYE clean power (550-600mA) +5V: for SCA, ADC, comparator, etc. (900-1000mA) +3.3V: for FPGA, Channel link, CPLD, etc.(450-500mA) +5V and +3.3V power supplies are subject to change.

BUCKEYE (ASIC) - amplifies andshapes input pulse

SCA (ASIC) - analog storage for 20 MHz sampled input pulse

ADC - events with LVL1ACCdigitized and sent to DAQ Motherboard (25 nsec/word)

Controller FPGA - controls SCA storage and digitization

Comparator ASIC - generatestrigger hit primitives from shapedpulse

Input/Output

- 5 cfebs/chamber, 96 strips/cfeb- 96 switch capacitors/channel- system is self triggering

Optimized for Precision Position Measurement

- 6 Buckeyes serve 6 planes x 16 strips- 6 SCA’s serve 96 strips with 96 caps each 50 nsec/sampling no pedestals (< 1%)-6 ADC’s (150 nsec digitization) 12-bit + overflow bit output 1 strip charge/25 nsec 8 samples digitized for each of 96 strips-6 SCA’s (96 caps/strip) LVDS signaling no cap pedestals-Control FPGA 12 blocks of 8 caps each grey-code (1 bit flip) addressing (see movie for algorithm)

16 Cap Delay Cap Storage (Poisson) Cap Digization (Queue)

Beam Crossing PreLCT L1A·LCT

0.8sec 2.2sec 26sec

Caps can be usedfor storage whenall others in use

16 caps set aside forpossible use

For L1ALCT use LCT to choose which 8 capacitors to digitize

Done

CFEB 50 nsec Sampling and Digitization

Each Strip Amplifier Charge stored every 50 nsec in capacitors

Simulation Single Strip Capacitor Usage A Nontrivial FPGA Algorithm

Green – recently used Blue – set aside waiting for L1A Red- digitizing

16 Cap Delay Cap Storage (Poisson) Cap Digization (Queue)

Beam Crossing LCT L1A·LCT

0.8sec 2.2sec 26sec

Transfer toDMB Complete

Caps can be usedfor storage whenall others in use

For SLHC this is themain capacitor usage

Data Bottlenecks in CSC DAQ at SLHC

• CFEB’s 96 Capacitors/channel is main DAQ rate limiter

• DCC’s SLINK-64 is second DAQ rate limiter (already fixed)

Simple Model CFEB Capacitor Storage

Strip Channels

Source strength K=5 (25 kHz/channel)Time (50ns/bin)

Neutron/Gamma Background DominatesEvent from X5 Beam test (Aug 99)

Neutron/Gamma Background DominatesEvent from X5 Beam test (Aug 99)

SCA Occupancy: LHC Rate AssumptionsL1 Accept: 100 kHzLCT rate: 69 kHz per CFEB (worst case – ME1/1) Estimated LCT rate for 10**34 lumi (D. Acosta et al, 2001) Chamber Type LCT rate per CFEB (kHz) ME1/1 69 ME1/2 4 ME1/3 2 ME2/1 21 ME2/2 3 ME3/1 11 ME3/2 2 ME4/1 8 ME4/2 9

L1-LCT coincidence rate per CFEB: 100 kHz x 70 kHz x 75 ns = 0.5 kH

Digitization time (with 6 ADCs on each CFEB) 16 channels x 16 samples/channel x 100 ns = 26 s

Problem! ‘ME1/1 LCT 96kHz/chamber (20 kHz) CMS Note 2002-007’ Hauser

ME1/1 Effective SCA Buffer Occupancy at SLHC• At SLHC: use same L1 accept rate assuming rates go up linearly.

Maximum LCT rate is 700 kHz (ME1/1), L1-LCT match rate is 5.25 kHz.• Average number of LCTs during 5.2 s (=6s-0.8s) holding time for

2-blocks: =5.2x10-6x700x103=3.64• Average number of L1-LCT matches during 26 s digitization time:

=26x10-6x5.25x103=0.1365• Probability of overuse of SCA: 0.09 !!!!!!!!!

n Free Used P( ,n) Q( ,n)0 12 0 0.026 0.861 10 2 0.095 0.122 8 4 0.174 1.60E-023 6 6 0.211 2.10E-034 4 8 0.192 3.00E-045 2 10 1.40E-01 4.10E-056 0 12 8.50E-02 5.60E-06

Digital CFEB – A Nice Idea for the SLHCReplace Conventional ADC and SCA storage with Flash ADC and Digital Storage• New System Deadtimeless, Removes rate worries• Similar cost to old systemFairly Radical Design – Couldn’t build 8 Years Ago

ME4/2 Linked to ME1/1 Upgrade?

New ME4/2 chambers need boards.Propose 514 new cards ME1/1 Old cards to populate ME4/2 Upgrade

ME1/1• Handles highest particle flux• Most important for momentum resolution.• Removes ganged strips in ME1/1a

DCFEBs were designed for highLuminosity.

We haven’t measured neutron and gamma background rates yet.

Overall Scope of Upgrade ME1/1 Electronics Upgrade 504 DCFEBs OSU 0.5 FTE 72 DMBs 72 TMB (d.c.)TAMU+ULCA 1.0FTE 8 MPC 72 LVDB (+more power) 72 LVMB1008 Cables (default skewclear)

When installing new ME1/1 chambers many new boards required

Thus we make improvements:

Design a 7 CFEB Trigger Board – new FPGADesign a 7 CFEB DAQMB (possibly single ASIC)Improve Board-Board Communication Present Skew-Clear Cable responsible for ME1/1 board failures ME1/1 at maximum allowed lengthDesign a new Muon Port Card

In this Meeting We are still in R&D stage Discuss design prototypes, progress, new ideas … Hope to try and define responsibilities. Get a feeling for a Timeline for prototypes and production

What this meeting is about

Extra Slides

Digital CFEB R&D BoardDesigned to study (there will be issues): - Coupling single ended Buckeye Amp to bipolar flash SCAs - Fiber output versus Skewclear outputNoise on Analog-Digital boards can be problems - use old PC boards analog isolation

Rates SLHC ME1/1

CFEB LCT*L1A Rate 5250 HzCFEB Digitized Data Readout 67.2 Mbits/s

Readout All Digitized Data 16 Gbit/s

Anode Cathode Trigger Primitives

Cathode charges

Anode hits

Cathode Trigger Primitives- Precision position (~0.5 cm/plane) - ASIC discriminator determines half strip- descriminator setting 16 bit DAC- minimum threshold 0.2 mV- timing spread over 3 Bx

Anode Trigger Primitives- Precision timing- Set fine timing (1 nsec) so signal in a single Bx (see right)

Test Beam Data 2004

Bx