Capstone CDR
Group: AquaLung
Mir Minhaz Ali Wilfredo Oteromatos Greg Newcomb Robin Elliott
Presentation Overview
Minhaz Hardware Overview Bill of Materials Fiber and Camera Assembly CCD and Connection
Greg USB Interface Easy USB Chip Connection Device Driver to
handle USB Driver to GUI
Robin Software Functionality Software Flowchart AquaImage Program Launch and Menu Time Chart Milestone Tasks
Freddy CCD Parallel Interface CCD Serial Interface Functional Block Diagram Analog to Digital FPGA Connection
Complete Hardware Overview
Spartan 3 FPGA
CCD Image Sensor TC237B680 x 500 Pixel
Camera
1M long Optical Fiber
2 pin Analog output
12.5 MHz CLOCK
Clock Driver & CCD Logic
ADC8 bit
AD7825
Easy USB CHIPFT245BM
2 bits Device Driver
6 MHz Crystal Resonator
GUI(Graphics User
Interface)
Bill of Materials (BOM)
1 meter long optical fiber with built in camera Ti CCD Sensor (TC237B) Hi speed clock driver for CCD (EL7202C) Octal buffer for CCD serial driver ( 74ACT240NS) Spartan 3 FPGA with 1M-byte of Fast
Asynchronous USB Chip (FT245BM) USB Cable and connector 8bits ADC(AD7825) EPROM (93LC46B-I/P) Clock (12.5 MHz) (CSTLS6M00G53Z-B0) Crystal Resonator (6MHz) Variable output voltage regulator (PTN7800) Other hardware, Capacitor and resistor.
Optical Fiber and Camera
7000 pieces of fiber inside creating full color image.
0.5mm diameter glass fiber imaging bundle enables scope to bend around .
Very inexpensive(120$) for 1M long fiber with camera
2 Xeon light bulbs to illuminate the image.
Camera Tip
Eye Piece
1M long Optical Fiber
Charge Couple Device (CCD)
0.34M Pixels Per Field 658(H) x 469(v) Active Elements Multimode readout capability
Progressive Scan Duel Line readout Image Area line Summing
Low Dark Current 7.4µm x 7.4µm pixel size12.5 MHz Clock
Module 1: CCD
Four Functional Blocks: Image sensing area image storage area serial register gate low noise signal processing amplifier block
The storage area and serial gate are used to transfer charge line by line from storage area into serial register
After transfer the pixel are clocked out and sensed by charged detection node.
TC237
SAG1111
SAG1010
IAG22
IAG112
RST7
SUB99
SRG8
OUT26
OUT15
ADB4
SUB33
ODB1
ODB DRIVER
R10
3.3K
2.7KR
R12
1.5K
10R165.2K
R183.3K
Q11R1001
Q21R1001
R192K
CCD_ODB
U29A
74HC14
1 2
+15V
CCD_SAG
CCD_OUT1
CCD_OUT2
+12V
CCD_IAG1
CCD_IAG2
Module 2: CCD Parallel interface
Drivers: EL7202C (non-inverting) Image Area Gate (IAG) Storage Area Gate (SAG)
- Input: CLK(12.5MHz) Output: Logic signals to
control Image and Storage Areas.
Purpose: Activates the Image Area and Opens the Storage Area.
R111.8K
+5V
IAG1_CLK
PARALLEL DRIVER
SAG_CLK
IAG2_CLK
HN1A01F
E1
1
B12
C2
3
E2
4
B25
C1
6
HN1A01F
E1
1
B12
C2
3
E2
4
B25
C1
6
HN1A01F
E1
1
B12
C2
3
E2
4
B25
C1
6
R20
1.8k
R21
1.8k
R221.8K
R231.8k
R243.9k
R251.2k
R261.8K
+2v
CCD_SAG
-10V
U35
EL7202C
NC1
IN A2
GND3
IN B4
OUT B5
V+6 OUT A7 NC8
CCD_IAG1
CCD_IAG2
U36
EL7202C
NC1
IN A2
GND3
IN B4
OUT B5
V+6 OUT A7 NC8
CCD Driver
Module 3 : CCD Serial Driver
Progressive Scan Mode Two register available for
high speed data transfer Drives the Serial Register
Gate (SRG) 12.5Mhz clk. Signal. 74ACT240 Octal buffer Allows data to be pulled
from the serial registers. Input: CLK (12.5MHz) Output: Driving signal.
+2v
560 10k
10
2.2k
0.1u
C
0.1u
10K560
4.7
4.7
+2v
560 10k
10
2.2k
0.1u
C
0.1u
10K560
4.7
-10v
4.7
R52
R
R53
R
CCD_SRG
CCD_RST
SRT_CLK
SRG_CLK
0
+5VC14
C
0
C14
C
0
0
C14C
0
74ACT240
1OE1
1A12
2Y43
1A24
VCC20
2OE19
1Y118
2A417
1A36 1Y2
16
2A315
2A111
GND10
2Y35
2Y19
2Y27
1Y412
1Y314
2A213
1A48
-10v
Octal Buffer
Parallel Driver
Serial Driver
Functional Block Diagram
Analog to Digital Converter
AD 7825 2Msps 420nS conversion time PWR Dissipation 36mW Input: 2 AC signals from CCD out1 and 2. Output: 8 Bits Parallel to FPGA. Purpose: Conversion from CCD analog output to FPGA A-2 header.
U30
DB21DB12DB03
CONVST4
CS5
RD6EOC8
A19
A010
PD11
VIN412 VIN313 VIN214 VIN115
VMID16
VREFIN/OUT17
VDD18
DB720DB621DB522DB423DB324
AGND
19DGN
D7
ADC0ADC1ADC2ADC3ADC4ADC5ADC6ADC7
ADC[0:7]
C80.1uF10uF
5V
0
2.5v
CCD_OUT1
CCD_OUT2
ADC_EOCADC_RDADC_CONVSTADC_CSADC_A1ADC_A0
ADC_PD
Module 4 : Spartan III FPGA
FPGA: Spartan III Inputs:
Data from ADC End of Conversion
(EOC) signal from ADC. Outputs:
8 bits data to USB interface
Control signals to: ADC USB (interface) CCD
Function: Data timing issues resolutions and sampling.
ADC_EOC
ADC_RD
ADC_CONVSTADC_CS
ADC_PD
ADC_A1
ADC_A0
ADC4ADC5ADC6ADC7
ADC0ADC1ADC2ADC3
ADC[0:7]
USB_RD#
USB_WR
USB_TXE#
USB_RXF#
USB_PWREN#
USB[0..7] USB[0:7]
US
B0
US
B3
US
B2
US
B1
US
B6
US
B4
US
B5
US
B7
SPARTAN III
A1 EXPANSION
A2 EXPANSION
B1 EXPANSION
Spartan 3 Board
GND1
VU(+5V)2
Vcco(+3.3V)3
PB-ADR04
PB-DB05
PB-ADR16
PB-DB17
PB-ADR28
PB-DB29
PB-ADR310
PB-DB311
PB-ADR412
PB-DB413
PB-ADR514
PB-DB515
PB-WE16
PB-DB617
PB-OE18
PB-DB719
PB-CS20
PB-CLK21
MB1-DB022
MB1-DB123
MB1-DB224
MB1-DB325
MB1-DB426
MB1-DB527
MB1-DB628
MB1-DB729
MB1-ASTB30
MB1-DSTB31
MB1-WRITE32
MB1-WAIT33
MB1-RESET34
MB1-INT35
PROG-B36
DONE37
INIT38
CCLK39
DIN40
GN
D1
VU
(+5V
)2
Vcc
o(+3
.3V
)3
PA-IO
14
PA-IO
25
PA-IO
36
PA-IO
47
PA-IO
58
PA-IO
69
PA-IO
710
PA-IO
811
PA-IO
912
PA-IO
1013
PA-IO
1114
PA-IO
1215
PA-IO
1316
PA-IO
1417
PA-IO
1518
PA-IO
1619
PA-IO
1720
PA-IO
1821
MA
2-D
B0
22
MA
2-D
B1
23
MA
2-D
B2
24
MA
2-D
B3
25
MA
2-D
B4
26
MA
2-D
B5
27
MA
2-D
B6
28
MA
2-D
B7
29
MA
2-A
STB
30
MA
2-D
STB
31
MA
2-W
RIT
E32
MA
2-W
AIT
33
MA
2-R
ES
ET
34
MA
2-IN
T/G
CK
435
PR
OG
-B36
DO
NE
37
INIT
38
CC
LK39
DIN
40
GND1
VU(+5V)2
Vcco(+3.3V)3
ADR04
DB05
ADR16
DB17
ADR28
DB29
ADR310
DB311
ADR412
DB413
ADR514
DB515
WE16
DB617
OE18
DB719
CSA20
LSBCLK21
MA1-DB022
MA1-DB123
MA1-DB224
MA1-DB325
MA1-DB426
MA1-DB527
MA1-DB628
MA1-DB729
MA1-ASTB30
MA1-DSTB31
MA1-WRITE32
MA1-WAIT33
MA1-RESET34
MA1-INT35
JTAG Isolation36
TMS37
TCK38
TDO-ROM39
TDO-A40
Module 5 : USB Interface
C3C
C4C
VCC_3V??
VCC_5V
VCC_3VC5C
C6
C7C
1
6 MHz Resonator
R91M
R1
2.2K
R2
10K
VCC_BAR
U17
93C56B
CS1
CLK2
DI3
DO4
VCC8
VCC_BAR
USB_RD#
USB_WR
USB_TXE#
USB_RXF#
USB_PWREN#
US
B[0..7]
USB B CONNECTOR
1A2A3A4A
USB0
R3
27R
R4 27R
USB1
R54.7K
R610K
R71.5K
R8470
USB2USB3USB4USB5USB6USB7
RESET
USB_D0-D7
C1C
FT245BM
U26
EEDATA2
AVCC
30
VCC1
3
VCCI
O13
D124
D223
D520
D619
D718
RD#16
WR15
TXE#14
RXF#12
SI/WU11
PWREN#10
3V3OUT6
USBDM8
USBDP7
RSTOUT#5
RESET#4
XTIN27
EECS32
EESK1
TEST31
D421
AGND
29
GND
9
GND
17
XTOUT28
D025
D322
VCC
26VC
C26
C2C
Easy USB chip
FIFO Interface between FPGA and USB cable Bidirectional Transfer data rate 1M byte/sec
Entire USB protocol handled on-chip Simple to interface with FPGA USB 2.0 Compatible Cheap $$$ EEPROM optional (93LC46B)
Default setting or program with EEPROM 6 MHz Timing Chip required
(CSTLS6M00GS32-B0) With 8x clock multiplier, works at 48 MHz
Easy USB - FT245BMSingle Chip USB <=> parallel FIFO bi-directional data transfer
ClockEEPROM Interface
Control
Check TXE# Low
Easy USB - FT245BMSingle Chip USB <=> parallel FIFO bi-directional data transfer
Input
8 pin digital signal from FPGA (D0-D7)
ClockEEPROM Interface
Control
Write when TXE# Low
Easy USB - FT245BMSingle Chip USB <=> parallel FIFO bi-directional data transfer
Output
2 pin signal to USB Cable (USBDP & USBDM)
Input
8 pin digital signal from FPGA (D0-D7)
ClockEEPROM Interface
Control
Sending over USB cable
TXE# is Raised
Easy USB - FT245BM
Single Chip USB <=> parallel FIFO bi-directional data transfer
Physical Connection to USB pins
Pin FPGA Signal Name
1 +5 V VBUS
2 USBDM Data Minus
3 USBDP Data Plus
4 GND GND
From FPGA To PC
Type A/B USB cable
USB Cable
•USB 2.0 (“Full Speed”)
•Uses NRZI (Non Return to Zero Invert) encoding
•Not our problem!
Device Driver to Handle USB
Provided by FTDI free
Version for Windows XP
Will allow for plug & play
Driver to GUI Handoff
Notice Interrupt
Open File 1
Driver to GUI Handoff
Save 1st picture
Driver to GUI Handoff
Picture 1 saved
Close File 1
Notice File 1 is Full
Open File 1
Driver to GUI Handoff
Save next picture
Read Data from File 1
Driver to GUI Handoff
Save next picture
Finish Getting Data
Close File 1
Send image to monitor
Driver to GUI Handoff
Save next picture
Open File 2
Get Data
Software Functionality
Launch Program
Display “Moving” Image
Display Still ImageOr None at all
Exit Program
Pick UpEvent
Data?
Pick UpEvent
Y Option Buttons•Zoom•Color Contrast•Pause/Unpause•Auto Save•OpenSaved Image
N
Software Flow Chart
Launch Program•initialize software
•look for device driver
Display “Moving” Image•Patient name & ID
•Zoom/Contrast toggle•Zoom Level (if zoomed)
DisplayDriverError
Display Still Image•Patient name & ID
•Zoom/Contrast toggle•Zoom Level (if zoomed)
?Valid
MouseEvent
?
?DataFromDriver
?
Exit Program•Close all files
?ImageUpdateReady
?
DisplayNo Signal
?OpenSavedImage
?
Color Contrast Toggle•Turn off Zoom
Zoom Toggle•Turn off Color Contrast
?MovingImage
?
?Valid
MouseEvent
?
?Determine
Event?
Auto Save Image•Name, ID, date, time
Pause Current Image
Unpause the Image
Exit•Confirm
Y Y
Y
Y
Y
N
N
N
NN
N
NY
Open Saved Image
Y
?DeviceDriverFound
?
?Determine
Event?
About AquaImage
This is the “About” box seen in all Windows applications.
Program Launch
Screen seen at start-up. Circled items are customized features.
Menu Bar
Menu features included in AquaImage.
Time Chart
Milestone Tasks
Milestone 1 GUI Complete Device Driver Implemented/Not
Tested Prototyping and Modular Testing
Milestone 2 Static Interface Working Prototyping and Testing Complete PCB In House
Questions ??