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Topics
Wire and via structures.Wire parasitics.Transistor parasitics.Fabrication theory and practice.
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Copper interconnect
Much better electrical characteristics.Copper is poisonous to semiconductors---must be isolated from silicon. Bottom layer of interconnect is aluminum.
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Metal migration
Current-carrying capacity of metal wiredepends on cross-section. Height is fixed,so width determines current limit.Metal migration: when current is too high,electron flow pushes around metal grains.
Higher resistance increases metal migration,leading to destruction of wire.
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Metal migration problems andsolutions
Marginal wires will fail after a smalloperating period infant mortality .
Normal wires must be sized to accomodatemaximum current flow:Imax = 1.5 mA/ mm of metal width.
Mainly applies to V DD /VSS lines.
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Diffusion wire capacitance
Capacitances formed by p-n junctions:
n+ (N D)
depletion region
substrate (N A) bottomwallcapacitance
sidewallcapacitances
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Depletion region capacitance
Zero-bias depletion capacitance: C j0 = si/xd.
Depletion region width: xd0 = sqrt[(1/N A + 1/N D)2 siV bi/q].
Junction capacitance is function of voltageacross junction: C j(V r ) = C j0/sqrt(1 + V r /V bi)
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Poly/metal wire capacitance
Two components: parallel plate;
fringe.
plate
fringe
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Metal coupling capacitances
Can couple to adjacent wires on same layer,wires on above/below layers:
metal 2
metal 1 metal 1
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Example: parasitic capacitancemeasurement
n-diffusion: bottomwall=2 fF, sidewall=2fF.
metal: plate=0.15 fF,fringe=0.72 fF.
3 mm
0.75 mm 1 mm
1.5 mm
2.5 mm
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Wire resistance
Resistance of any size square is constant:
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Skin effect
At low frequencies, most of copper conductors cross section carries current.
As frequency increases, current moves toskin of conductor. Back EMF induces counter-current in body of
conductor.Skin effect most important at gigahertzfrequencies.
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Skin effect, contd
Isolated conductor: Conductor and ground:
Low frequency
High frequency
Low frequency
High frequency
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Skin depth
Skin depth is depth at which conductorscurrent is reduced to 1/3 = 37% of surface
value:d = 1/sqrt( p f m s )
f = signal frequency
m = magnetic permeabilitys = wire conducitvity
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Effect on resistance
Low frequency resistance of wire: R dc = 1/ s wt
High frequency resistance with skin effect: R hf = 1/2 s d (w + t)
Resistance per unit length: R ac = sqrt(R dc 2 + k R hf 2)
Typically k = 1.2.
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Transistor source/drain parasitics
Source/drain have significant capacitance,resistance.
Measured same way as for wires.Source/drain R, C may be included in Spicemodel rather than as separate parasitics.
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Why we need design rules
Masks are tooling for manufacturing.Manufacturing processes have inherentlimitations in accuracy.Design rules specify geometry of maskswhich will provide reasonable yields.Design rules are determined by experience.
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Design rules and yield
Design rules are determined bymanufacturing process characteristics.
Design rules should provide adequate yieldif followed.Types of design rules: Spacing. Separation. Composition.
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Yield
Gamma distribution for yield of a singletype of structure: Y i = [1/(1+A b i)]a i.Total yield for the process is the product of all yield components:
Y = P Y i.
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Manufacturing problems
Photoresist shrinkage, tearing.Variations in material deposition.Variations in temperature.Variations in oxide thickness.Impurities.Variations between lots.Variations across a wafer.
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Transistor problems
Varaiations in threshold voltage: oxide thickness;
ion implanatation; poly variations.
Changes in source/drain diffusion overlap.
Variations in substrate.
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Wiring problems
Diffusion: changes in doping -> variationsin resistance, capacitance.
Poly, metal: variations in height, width ->variations in resistance, capacitance.Shorts and opens:
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Oxide problems
Variations in height.Lack of planarity -> step coverage.
metal 1metal 2
metal 2
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Via problems
Via may not be cut all the way through.Undesize via has too much resistance.Via may be too large and create short.
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Scaling theory
Chips get better as features shrink inclassical scaling theory:
Capacitive load goes down faster than current.Classical scaling theory runs intocomplications at nanometer features.
Leakage. Smaller supply voltage.
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Scaling model
l l /x.W W/x, L L/x.tox tox /x.
Nd Nd/x.V
DD V
SS (V
DD V
SS)/x.
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Interconnect scaling
Two varieties of interconnect scaling: Ideal scaling reduces vertical and horizontal
dimensions equally. Constant dimension does not change wiring
sizes.
Higher levels of interconnect are constantdimension---same as older technologies.
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Interconnect scaling trends
Ideal scaling Constant dimension
Line width/spacing S 1
Wire thickness S 1
Interlevel dielectric S 1Wire length 1/sqrt(S) 1/sqrt(S)
Resistance/unit length 1/S 2 1
Capacitance/unit length 1 1
RC delay 1/S3
1/SCurrent density 1/S S
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ITRS roadmap
Semiconductor industry projects fabricationtrends.
Helps plan future technologies.Roadmap describes features, technologyrequired to get to those goals.
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M d VLSI D i 4 Ch t 2 C i ht 2009 P ti H ll PTR
ITRS roadmap 2005-2012
2005 2006 2007 2008 2009 2010 2011 2012
CPUmetal
pitch
90 75 68 59 52 45 40 36
CPUgatelength
32 28 25 23 20 18 16 14
ASICgatelength
45 38 32 28 25 23 20 18