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Advanced Analog Integrated Circuits
Operational Transconductance Amplifier IIMulti-Stage Designs
Bernhard E. BoserUniversity of California, Berkeley
Copyright © 2016 by Bernhard Boser
EE240B – OTA II: Multi-Stage
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Voltage Gain
EE240B – OTA II: Multi-Stage
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Power Dissipation
Voltage gain stage
EE240B – OTA II: Multi-Stage
Single Multiple
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Frequency Compensation
• Cascaded amplifiers– Each stage contributes a pole– Stability: only one “dominant pole” (𝑓" < 𝑓$of𝑇 𝑠 )– Ensuring this is called “compensation”
• Main compensation techniques– Narrowbanding– Feedback zero– Miller– Feedforward
EE240B – OTA II: Multi-Stage
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Narrowbanding
EE240B – OTA II: Multi-Stage
𝑇 𝑠
logω
𝑇-𝜔"/
𝜔"0
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Feedback Zero
• LHP zero adds “lead”
• Closed-loop response modified above zero
• Compensation only marginally reduces bandwidth
Ref: Feedback, Op Amps and Compensation, AN 9415.3, Intersil, Nov. 1996.
EE240B – OTA II: Multi-Stage
𝐻 𝑠
logω
𝑎 𝑠𝑇 𝑠
𝑓 𝑠
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Miller Compensation
EE240B – OTA II: Multi-Stage
𝜔"/ 𝜔"0
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Intuitive Appreciation of Pole Splitting
• Capacitive feedback splits the poles
EE240B – OTA II: Multi-Stage
𝐻 𝑠
logω
𝑎 𝑠 𝜔"/𝜔"0
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Compensated a(s)
𝑝/ ≅ −1
𝑅/ 𝑔90𝑅0Millergain
𝐶A
𝑝0 ≅ −𝑔90
𝐶0 1 + 𝐶/𝐶A+ 𝐶/
≅ −𝑔90𝐶0
𝑧 = +𝑔90𝐶A
GBW = 𝜔$ ≅ 𝜔"/ 𝑇- = 𝛽𝑔9/𝐶A
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Bandwidth Comparison
Single voltage gain stage Two voltage gain stages
EE240B – OTA II: Multi-Stage
𝜔$ ≅ 𝛽𝑔9/𝐶I
𝜔JK ≅𝜔L3
𝜔$ ≅ 𝛽𝑔9/𝐶A
𝜔JK = 𝜔"0 ≅𝑔90𝐶I
=𝑔90𝐶/NOPQ
𝐶/𝐶IRS/?
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Advanced Analog Integrated Circuits
Miller Zero
Bernhard E. BoserUniversity of California, Berkeley
Copyright © 2016 by Bernhard Boser
EE240B – OTA II: Multi-Stage
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Root Locus
Ignoring zero With zero
EE240B – OTA II: Multi-Stage
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Bode Plot
EE240B – OTA II: Multi-Stage
𝑝/
𝑝0
𝑧
+180
/To
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Intuitive Appreciation of Zero
EE240B – OTA II: Multi-Stage
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Mitigating Impact of Zero
EE240B – OTA II: Multi-Stage
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Nulling Resistor
𝑇 𝑠 = 𝑇-1 − 𝑠𝐶A
1𝑔90
− 𝑅U
1 − 𝑠𝑝/
1 − 𝑠𝑝0
1 − 𝑠𝑝V
• 𝑅U can be used to “tune” the zero
• Poles 𝑝/ and 𝑝0 unchanged
• Additional pole 𝑝V ≅ − /XYZ[
EE240B – OTA II: Multi-Stage
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Choices for Rz
EE240B – OTA II: Multi-Stage
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Ahuja Compensation
EE240B – OTA II: Multi-Stage
( )
!"!#$1usually
12
2*2
12
22
0
1
1221 1
1
>
+=
+-»
-»+
-»
CC
CCCp
CC
CCgp
Cag
CRRgp
c
c
c
c
m
cv
m
cm
• No zero (ideal cascode)
• p2 at higher frequency
• Translates into smaller Ccfor given C2
• Problems:– Current I2 (extra power)– Mismatch (in I2 sources)
causes offset– I2 limits slew rate
[ Ahuja, IEEE JSSC, 12/1983 ]
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Ribner Variant
• Uses 1st stage cascodeto make feedback unilateral
• No extra power or slewing limitation
• 3rd order response– very challenging design
problem
EE240B – OTA II: Multi-Stage
[ Ribner, IEEE JSSC, 12/1984 ]
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Noise Analysis
• For full treatment, seeA. Dastgheib and B. Murmann, “Calculation of total integrated noise in analog circuits,” IEEE TCAS I, Nov. 2008, pp. 2988-93.
EE240B – OTA II: Multi-Stage
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Advanced Analog Integrated Circuits
Design Example
Bernhard E. BoserUniversity of California, Berkeley
Copyright © 2016 by Bernhard Boser
EE240B – OTA II: Multi-Stage
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Design Example
EE240B – OTA II: Multi-Stage
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Specification
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Unknowns
• Topology
• Device parameters:– M1: 𝑔9/, 𝑉/∗, 𝑓L/ ⟹ 𝐼a/, 𝐿/, 𝑊/– M2: 𝑔90, 𝑉0∗, 𝑓L0 ⟹ 𝐼a0, 𝐿0, 𝑊0
• Compensation capacitance, 𝐶A• Noise excess factors, 𝛼/, 𝛼0• Output voltage range
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Structural Parameters
• Guess (and iterate):
• Now calculate remaining design parameters …
EE240B – OTA II: Multi-Stage
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Gain and Feedback Factor
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Dynamic Range
EE240B – OTA II: Multi-Stage
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Settling
EE240B – OTA II: Multi-Stage
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Power Dissipation
EE240B – OTA II: Multi-Stage
Close to weak inversion:• increase L1 (higher gain)• reduce rgg1 (lower power?)
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Iteration: rgg1 = 0.1
EE240B – OTA II: Multi-Stage
was 8.8 mW
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Sanity Check: Single Gain Stage
• About half the power of 2-stage– Provided gain & dynamic range can be met– Practical “lower bound”
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Finalize Design
• Iterate over all parameters (use Matlab “lookup”)
• Estimate and add extrinsic capacitances
• Other design elements– Static settling error– Slewing– Biasing– Device geometry– Corners– Layout …
EE240B – OTA II: Multi-Stage
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Advanced Analog Integrated Circuits
Special OTA Topologies
Bernhard E. BoserUniversity of California, Berkeley
Copyright © 2016 by Bernhard Boser
EE240B – OTA II: Multi-Stage
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Nested Miller Compensation
Ref: R. Eschauzier et al, “A 100-MHz 100-dB operational amplifier with multipath nested Miller compensation structure”, IEEE JSSC, Dec. 1992, pp. 1709-1717.
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Settling Behavior
• Very challenging design problem
• Accurate and fast settling (nearly?) impossible
• Good choice for broad-band, high gain & other situations that do not require fast settling
EE240B – OTA II: Multi-Stage
PM = 85o
Ref: Nguyen & Murmann, “The Design of Fast-Settling Three-Stage Amplifiers Using the Open-Loop Damping Factor as a Design Parameter”, IEEE TCAS I, June 2010, pp. 1244-54.
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Feedforward OTA
EE240B – OTA II: Multi-Stage
Ref: Shibata et al, “A DC-to-1 GHz Tunable RF DS ADC Achieving DR=74dB and BW=150MHz at fo=450MHz Using 550 mW”, JSSC 12/2012, pp. 2888-97.