M11 MOS Switches - University of California, Berkeleyboser/courses/240B/lectures/M11 … · Ideal Track and Hold EE240B –MOS Switches. B. E. Boser 4 Sampling versus Charge Processing

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Advanced Analog Integrated Circuits

MOS Switches

Bernhard E. BoserUniversity of California, Berkeley

[email protected]

Copyright © 2016 by Bernhard Boser

EE240B – MOS Switches

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MOS Switches


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Ideal Track and Hold


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Sampling versus Charge Processing

Sampling

• Input varies (often rapidly)

Charge Processing (SC)

• Input ~constant


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Signal Nomenclature


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MOS Sample & Hold (Track & Hold)


(simplest realization)

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Switch Nonidealities


[email protected]



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Nonidealities


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Switch on-resistance


Ron

0 VDD

NMOS PMOS CMOS

VTHVi

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Signal Dependent on-resistance


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Hold-Mode Feedthrough


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Hold-Mode Leakage


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Gate Leakage

• 65nm CMOS: ~ 1V/ms droop– Addressed in sub-65nm technologies with high-k dielectrics

Ref: A. Annema et al, “Analog circuits in ultra-deep-submicron CMOS,” IEEE JSSC, Jan. 2005, pp. 132-43.


Min

imum

f s

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Thermal Noise


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Clock Jitter


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Charge Injection and Clock Feedthrough


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Charge Injection and Clock Feedthrough


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Slow Gating


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Slow Gating Model


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Fast Gating


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Charge Split Ratio a

Ref: G. Wegemann et al, “Charge injection in analog MOS switches,” IEEE JSSC, June 1987, pp. 1091-7.


𝑅#$𝐶&𝑇(

�

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Slow Switching or Fast Switching?


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Fast Gating Model


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Fast à Slow Gating Errors


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Technology Scaling


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Mitigating Charge Injection Error


[email protected]



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Mitigating Charge Injection Error


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Charge Cancellation

Ref: Ch. Eigenberger et al, “Dummy Transistor compensation of analog MOS switches,” JSSC Aug 1989, pp. 1140-6.


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Charge Cancellation Example

• ~ 6-Bit accuracy

Ref: M. Choi et al, “A 6-b 1.3-Gsample/s A/D converter in 0.35mm CMOS.” JSSC Dec 2001, pp. 1847-58.


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CMOS Switch


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Differential Sampling


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Clock Bootstrapping


[email protected]



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Clock Bootstrapping


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Input and Clock Waveforms


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Booster Circuit


𝑅*$ ≅1

𝜇$𝐶*.𝑊𝐿

𝐶1𝐶1 + 𝐶345

𝑉77 −𝐶345

𝐶1 + 𝐶345𝑉#$ − 𝑉9: 𝑉#$

(square law model)

Cpar

Vin

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Booster Performance Example

• Good to ~ 10 Bits

Ref: S. Louwsma et al, “A 1.35 GS/s, 10 b, 175 mW time-interleaved AD converter in 0.13 um CMOS”, JSSC April 2008, pp. 778-86.


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Bottom Plate Sampling


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Bottom Plate Sampling

• References– D. G. Haigh and B. Singh, “A switching scheme for SC filters which reduces the

effect of parasitic capacitances associated with switch control terminals,” ISCAS 1983, pp. 586-9.

– K.-L. Lee and R. G. Meyer, “Low-distortion switched-capacitor filter design techniques,” IEEE JSSC, Dec 1985, pp. 1103-13.


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1) Sample


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2) Disconnect CH


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Charge at Node X


DQ1

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Open-Loop Charge Processing


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Closed-Loop Charge Processing


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Charge Conservation Analysis


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Cancelling the Offset: Fully Differential


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Sampling Network


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SC Gain with Common-Mode Cancellation

Ref: S. H. Lewis and P. R. Gray, “A pipelined 5 MSample/s 9-bit analog-to-digital converter,” IEEE JSSC Dec 1987, pp. 954-61.


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Flip-Around T/H


Ref: W. Yang et al, “A 3-V 340-mW 14-b 75-MSample/s CMOS ADC with 85-dB SFDR at Nyquist input,” IEEE JSSC Dec 2001, pp. 1931-36.

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Sampling Network Design


Ref: Y.-M. Lin et al., “A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-um CMOS,” IEEE JSSC April 1991, pp. 628-36.

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Realization of Shorting Switch


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Capacitors


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Capacitors


Ref: C. H. Ng et al, “MIM capacitor integration for mixed-signal/RF applications,” IEEE Trans ED, July 2005, pp. 1399-1409.

Ref: R. Aparicio et al, “Capacity Limits and Matching Properties of Integrated Capacitors,” IEEE JSSC, March 2002, pp. 384-93.

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Capacitor Top and Bottom Parasitics


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Connection of Capacitors


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M11 MOS Switches - University of California, Berkeleyboser/courses/240B/lectures/M11 … · Ideal Track and Hold EE240B –MOS Switches. B. E. Boser 4 Sampling versus Charge Processing