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Laboratory for Reliable Computing (LaRC)Department of Electrical EngineeringNational Tsing Hua UniversityHsinchu, Taiwan 30013
A BIST Scheme for
FPGA InterconnectDelay Faults
Chun-Chieh Wang, Jing-Jia Liou,
Yen-Lin Peng, Chih-Tsun Huang, and
Cheng-Wen Wu
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Outline
Introduction
Objective Proposed BIST architectures
Experimental results
Conclusions
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Introduction
The causes of FPGA delay fault
More circuits operating at high speed
DSM processes have resulted in more
defects affecting the delay FPGA delay testing problem
Path delay fault model is not appropriate
Segment delay fault model is used
At-speed testing is practically difficult
Need BIST approach
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Objective
Why test the interconnects of FPGA?
Delay faults are mostly associated withinterconnects
Universal testing method
Application-independent testingmethodology
The objective: A BIST scheme for interconnect delay
faults with minimal clock skew effects
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Clock Skew Effect
D Q
FF1
D Q
FF2
A B
CLK
TAB
TCLKTCLK-TSkew
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Proposed BIST Design (BIST1) Assumptions:
The PUT has to be the longest path amongall paths in the BIST
Ignore skew between FFs in a CLB
Falling
D1 Q1
EC
D2 Q2
EC
PUT
TPG
Controller
1
101100
110CLB
0
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Test Result Observation Readback mechanism
The two phase approach
D1 Q1
EC
CLB for BIST
CLB for ORA
GoNoGo
BIST BIST BIST
ORA ORA ORA
BIST BIST BIST
First phase
BIST BIST BIST
ORA ORA ORA
ORA ORA ORA
Second phase
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WE and NS Switch Testing Issues
The loop-back PUTs targeting WE and NS are
too long
Shorter PUTs are connected between different
CLBs
Need to validate clock skews
CLB CLBWE
PUT
CLB CLBWE
PUT
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Clock Skew Validation
Using tested paths to validate clock
Change test clock: TCLK = TCLK + TSkew
Violations can be detected when they causestrobe time to be earlier than TPath
Shortest path has small TSlack to detectsmall violations
TCLK
Undetectable
TCLK
detectable
TPath TSlack
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Modified BIST Design (BIST2)
Assumptions:
The clock skews have been validated
The PUT is longest
Other paths have been tested
D1 Q1
EC
D3 Q3
EC
D2 Q2
ECCLB1
011
01
CLB2
110
001PUT
0
000
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Experimental Results
Target device: a 14x14 Xilinx Spartan SeriesFPGA
Only single-length lines are considered
After TC reduction
BIST1 has lower utilization than BIST2
BIST1
BIST2
BIST type
1
1
1
2
2
All wire segments
NE, WS, WN, and ES switches
All wire segments
NE, WS, WN, and ES switches
Clock skew between 2 adjacent CLBs
All WE, NS switches
All WE & NS switches
Target segments # of TCs Total
16
24
16
4
16
40
36
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Segment Coverage
Effective segment coverage
Segment coverage
Switches used
Tracks used
I/O pins used
CLB pins used
CLB block used
9392/10800
3360/3840
0/112
1568/1568
196/196
87.89%
100%
BIST1 BIST1&2196/196
1568/1568
0/112
3360/3840
9392/10800
87.89%
100%
Array size: 14 x 14
A metric to measure how much resources are
covered by test configurations BIST-based methods never cover segments
involved with IOB
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Statistical Delay Defect Coverage
Use Poisson distribution to model the fault
distribution
Adopt a Monte Carlo process to produce
samples
Effective statistical delay defect coverage
(ESDDC) = Sdetected / Sfailed
Sdetected: total failed samples that have
been detected
Sfailed: total failed samples
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ESDDC
95.0%
96.0%
97.0%
98.0%
99.0%
100.0%
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
The Mean Value of Defect Size (unit time)
DefectCo
verage(%)
BIST1 BIST1&2
Sample count: 10K Defect count (mean): 1.3
Slack: 10% of segment spec. FPGA size: 14 x 14
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Conclusions and Future Work
We have proposed new BIST designs forFPGA interconnect delay faults
At-speed testing
Without being affected by clock skew
Easy implementation on different FPGAarchitectures
Test configurations are generatedautomatically
Future work: interconnect delay fault diagnosis